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362 lines
15 KiB
Python
362 lines
15 KiB
Python
#
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# This is a LPC slave front end. It runs the LPC statemachine for FW
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# and IO Read and write cycles. It's clocked off the LPC lclk and no
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# other clock is needed. The LPC/front end is just the
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# LAD/lframe/lreset lines.
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#
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# This collects address/data/cmd info and presents it to a back end
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# interface which is split into a write and read interface. Incoming
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# LPC transactions are presented on the write interface via
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# LPCWRCMDInterface. The back end reponds via the read interface via
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# LPCRDCMDInterface. Both of these interfaces use the LPC clock.
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#
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# To ensure that the back end can respond to requests, the LPC sync
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# cycle is held in a long wait until the be back end responds. If
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# there is an error in the back end (eg an address doesn't exist),
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# the error signal can be asserted, and the SYNC cycle will ERROR and
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# then release the LAD lines. If there is no error, the SYNC will
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# respond with READY and finish the LPC transaction. This happens on
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# both LPC reads and writes.
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#
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# DMA and MEM read/write cycles are not supported currently. LPC
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# interrupts (SERIRQ) is also not supported currently
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#
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from enum import Enum, unique
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from nmigen import Signal, Elaboratable, Module, unsigned, Cat
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from nmigen.back import verilog
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import math
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@unique
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class LPCStates(Enum):
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START = 0
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CYCLETYPE = 1 # IO
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IOADDR = 2
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FWIDSEL = 3 # FW
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FWADDR = 4
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FWMSIZE = 5
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RDTAR1 = 6 # Reads
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RDSYNC = 7
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RDDATA = 8
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WRDATA = 9 # Writes
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WRTAR1 = 10
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WRSYNC = 11
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TAR2 = 12 # End common for Reads and Writes
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@unique
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class LPCCycletype(Enum):
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IORD = 0
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IOWR = 1
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FWRD = 2
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FWWR = 3
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class LPCStartType():
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MEMIODMA = 0b0000
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FWRD = 0b1101
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FWWR = 0b1110
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class LPCSyncType():
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READY = 0b0000
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SHORT_WAIT = 0b0101
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LONG_WAIT = 0b0110
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ERROR = 0b1010
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LPC_IO_DATA_WIDTH = 8
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LPC_IO_ADDR_WIDTH = 16
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LPC_FW_DATA_WIDTH = 32
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LPC_FW_ADDR_WIDTH = 28
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class LPCWRCMDInterface():
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def __init__(self, *, addr_width, data_width):
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self.addr = Signal(addr_width)
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self.data = Signal(data_width)
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self.cmd = Signal(LPCCycletype)
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self.size = Signal(2) # upto 4 bytes
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self.rdy = Signal()
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self.en = Signal()
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self.rst = Signal()
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# width of fifo needed to transport this
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def width(self):
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return self.addr.width + self.data.width + self.cmd.width + self.size.width
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class LPCRDCMDInterface():
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def __init__(self, *, data_width):
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self.data = Signal(data_width)
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self.error = Signal()
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self.rdy = Signal() # data is ready
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self.en = Signal() # data has been read
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self.rst = Signal()
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# width of fifo needed to transport this
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def width(self):
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return self.data.width + self.error.width
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class lpcfront(Elaboratable):
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"""
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LPC slave
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"""
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def __init__(self):
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# Ports
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self.lframe = Signal()
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self.lad_in = Signal(4)
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self.lad_out = Signal(4)
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self.lad_en = Signal()
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self.lreset = Signal()
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# synthetic tristate signals
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self.lad_tri = Signal(4)
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self.wrcmd = LPCWRCMDInterface(addr_width=LPC_FW_ADDR_WIDTH,
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data_width=LPC_FW_DATA_WIDTH)
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self.rdcmd = LPCRDCMDInterface(data_width=LPC_FW_DATA_WIDTH)
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def elaborate(self, platform):
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m = Module()
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state = Signal(LPCStates)
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statenext = Signal(LPCStates)
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cycletype = Signal(LPCCycletype)
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# FW data is 32 bites with 4 bits per cycle = 8 cycles
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cyclecount = Signal(math.ceil(math.log2(LPC_FW_DATA_WIDTH/4)))
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addr = Signal(LPC_FW_ADDR_WIDTH)
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data = Signal(LPC_FW_DATA_WIDTH)
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size = Signal(unsigned(2)) # 1, 2 or 4 bytes
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lframesync = Signal()
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# fifo interface
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m.d.comb += self.wrcmd.addr.eq(addr)
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m.d.comb += self.wrcmd.data.eq(data)
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m.d.comb += self.wrcmd.size.eq(size)
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m.d.comb += self.wrcmd.en.eq(0) # default, also set below
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m.d.comb += self.rdcmd.en.eq(0) # default, also set below
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m.d.sync += state.eq(statenext) # state machine
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m.d.comb += self.lad_en.eq(0) # set below also
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# run the states
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m.d.comb += statenext.eq(state) # stay where we are by default
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with m.Switch(state):
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# with m.Case(LPCStates.START):
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# this is handled at the end as an override since lframe
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# can be aserted at any point
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with m.Case(LPCStates.CYCLETYPE):
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m.d.comb += statenext.eq(LPCStates.IOADDR)
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m.d.sync += cyclecount.eq(3)
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with m.Switch(self.lad_in):
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with m.Case("000-"):
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m.d.sync += cycletype.eq(LPCCycletype.IORD)
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with m.Case("001-"):
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m.d.sync += cycletype.eq(LPCCycletype.IOWR)
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with m.Default():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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with m.Case(LPCStates.IOADDR):
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m.d.sync += cyclecount.eq(cyclecount - 1)
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m.d.sync += addr.eq(Cat(self.lad_in, addr[:24]))
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# Make sure the read fifo is cleared out of any
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# entries before adding another. This could happen on
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# an LPC transaction abort (ie. when lframe/lreset is
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# asserted during a transaction).
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m.d.comb += self.rdcmd.en.eq(1)
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with m.If(cyclecount == 0):
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m.d.sync += size.eq(0) # IO cycles are 1 byte
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m.d.sync += cyclecount.eq(1) # TAR 2 cycles
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with m.If(cycletype == LPCCycletype.IORD):
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m.d.comb += statenext.eq(LPCStates.RDTAR1)
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with m.Elif(cycletype == LPCCycletype.IOWR):
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m.d.comb += statenext.eq(LPCStates.WRDATA)
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with m.Else():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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with m.Case(LPCStates.FWIDSEL):
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# Respond to any IDSEL
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m.d.comb += statenext.eq(LPCStates.FWADDR)
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m.d.sync += cyclecount.eq(6) # 7 cycle FW addr
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with m.Case(LPCStates.FWADDR):
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m.d.comb += statenext.eq(LPCStates.FWADDR)
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m.d.sync += addr.eq(Cat(self.lad_in, addr[:24]))
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# Make sure the read fifo is cleared out of any
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# entries before adding another. This could happen on
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# an LPC transaction abort (ie. when lframe/lreset is
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# asserted during a transaction).
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m.d.comb += self.rdcmd.en.eq(1)
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m.d.sync += cyclecount.eq(cyclecount - 1)
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with m.If(cyclecount == 0):
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m.d.comb += statenext.eq(LPCStates.FWMSIZE)
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with m.Case(LPCStates.FWMSIZE):
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with m.Switch(self.lad_in):
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with m.Case(0b0000): # 1 byte
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m.d.sync += size.eq(0)
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m.d.sync += cyclecount.eq(1) # 1 byte = 2 nibbles
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with m.Case(0b0001): # 2 bytes
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m.d.sync += size.eq(1)
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m.d.sync += cyclecount.eq(3) # 2 byte = 2 nibbles
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with m.Case(0b0010): # 4 bytes
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m.d.sync += size.eq(3)
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m.d.sync += cyclecount.eq(7) # 4 byte = 8 nibbles
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with m.Default():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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with m.If(cycletype == LPCCycletype.FWRD):
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m.d.sync += cyclecount.eq(1) # TAR 2 cycles
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m.d.comb += statenext.eq(LPCStates.RDTAR1)
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with m.Elif(cycletype == LPCCycletype.FWWR):
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m.d.comb += statenext.eq(LPCStates.WRDATA)
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with m.Else():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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# LPC FW and IO reads
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with m.Case(LPCStates.RDTAR1):
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# send off the command to the fifo in the first cycle
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m.d.comb += self.wrcmd.en.eq(cyclecount == 1)
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with m.If(cycletype == LPCCycletype.IORD):
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m.d.comb += self.wrcmd.cmd.eq(LPCCycletype.IORD)
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with m.Else():
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m.d.comb += self.wrcmd.cmd.eq(LPCCycletype.FWRD)
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m.d.sync += cyclecount.eq(cyclecount - 1)
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with m.If(cyclecount == 0):
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m.d.comb += statenext.eq(LPCStates.RDSYNC)
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with m.Case(LPCStates.RDSYNC):
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m.d.comb += self.lad_out.eq(LPCSyncType.LONG_WAIT)
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m.d.comb += self.lad_en.eq(1)
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with m.If(self.rdcmd.rdy):
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m.d.comb += self.rdcmd.en.eq(1)
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m.d.comb += statenext.eq(LPCStates.RDDATA)
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m.d.comb += self.lad_out.eq(LPCSyncType.READY) # Ready
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with m.Switch(size):
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with m.Case(0): # 1 byte
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m.d.sync += cyclecount.eq(1) # 1 byte = 2 nibbles
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m.d.sync += data.eq(Cat(self.rdcmd.data[0:8],0))
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with m.Case(1): # 2 bytes
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m.d.sync += cyclecount.eq(3) # 2 byte = 2 nibbles
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m.d.sync += data.eq(Cat(self.rdcmd.data[0:16],0))
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with m.Case(3): # 4 bytes
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m.d.sync += cyclecount.eq(7) # 4 byte = 8 nibbles
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m.d.sync += data.eq(self.rdcmd.data) # grab the data
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with m.Default():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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# we shouldn't get FW errors, but here for completeness
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with m.If(self.rdcmd.error):
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m.d.comb += statenext.eq(LPCStates.START)
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m.d.comb += self.lad_out.eq(LPCSyncType.ERROR)
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with m.Case(LPCStates.RDDATA):
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m.d.comb += self.lad_en.eq(1)
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m.d.sync += data.eq(Cat(data[4:], data[:28]))
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m.d.comb += self.lad_out.eq(data[:4])
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m.d.sync += cyclecount.eq(cyclecount - 1)
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with m.If(cyclecount == 0):
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m.d.comb += statenext.eq(LPCStates.TAR2)
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m.d.sync += cyclecount.eq(1) # TAR cycles = 2
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# LPC IO and FW writes
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with m.Case(LPCStates.WRDATA):
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with m.Switch(size):
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with m.Case(0): # 1 byte
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m.d.sync += data.eq(Cat(data[4:8],self.lad_in))
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with m.Case(1): # 2 bytes
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m.d.sync += data.eq(Cat(data[4:16],self.lad_in))
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with m.Case(3): # 4 bytes
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m.d.sync += data.eq(Cat(data[4:32],self.lad_in))
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with m.Default():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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m.d.sync += cyclecount.eq(cyclecount - 1)
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with m.If(cyclecount == 0):
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m.d.sync += cyclecount.eq(1) # 2 cycle tar
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m.d.comb += statenext.eq(LPCStates.WRTAR1)
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with m.Case(LPCStates.WRTAR1):
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# send off the command to the fifo in the first cycle
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m.d.comb += self.wrcmd.en.eq(cyclecount == 1)
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with m.If(cycletype == LPCCycletype.IOWR):
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m.d.comb += self.wrcmd.cmd.eq(LPCCycletype.IOWR)
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with m.Else():
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m.d.comb += self.wrcmd.cmd.eq(LPCCycletype.FWWR)
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m.d.sync += cyclecount.eq(cyclecount - 1)
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with m.If(cyclecount == 0):
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m.d.comb += statenext.eq(LPCStates.WRSYNC)
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with m.Case(LPCStates.WRSYNC):
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m.d.comb += self.lad_out.eq(LPCSyncType.LONG_WAIT)
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m.d.comb += self.lad_en.eq(1)
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with m.If(self.rdcmd.rdy): # wait for ack
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m.d.comb += self.rdcmd.en.eq(1)
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m.d.comb += statenext.eq(LPCStates.TAR2)
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m.d.comb += self.lad_out.eq(LPCSyncType.READY)
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m.d.sync += cyclecount.eq(1) # 2 cycle tar
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# we shouldn't get FW errors, but here for completeness
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with m.If(self.rdcmd.error):
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m.d.comb += statenext.eq(LPCStates.START)
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m.d.comb += self.lad_out.eq(LPCSyncType.ERROR)
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with m.Case(LPCStates.TAR2):
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m.d.comb += self.lad_en.eq(1)
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m.d.comb += self.lad_out.eq(0b1111)
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m.d.sync += cyclecount.eq(cyclecount - 1)
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with m.If(cyclecount == 0):
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m.d.comb += self.lad_en.eq(0)
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m.d.comb += statenext.eq(LPCStates.START) # Done
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with m.Default():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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# reset override
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with m.If(self.lreset == 0):
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m.d.comb += statenext.eq(LPCStates.START)
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m.d.comb += self.lad_en.eq(0) # override us driving
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# Start cycle can happen anywhere
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with m.If(self.lframe == 0):
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m.d.comb += self.wrcmd.rst.eq(1)
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m.d.comb += self.rdcmd.rst.eq(1)
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m.d.comb += self.lad_en.eq(0) # override us driving
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with m.Switch(self.lad_in):
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with m.Case(LPCStartType.MEMIODMA):
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m.d.comb += statenext.eq(LPCStates.CYCLETYPE)
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with m.Case(LPCStartType.FWRD):
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m.d.comb += statenext.eq(LPCStates.FWIDSEL)
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m.d.sync += cycletype.eq(LPCCycletype.FWRD)
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with m.Case(LPCStartType.FWWR):
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m.d.comb += statenext.eq(LPCStates.FWIDSEL)
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m.d.sync += cycletype.eq(LPCCycletype.FWWR)
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with m.Default():
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m.d.comb += statenext.eq(LPCStates.START) # Bail
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# fifo reset needs to be held for two cycles
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m.d.sync += lframesync.eq(self.lframe)
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m.d.comb += self.wrcmd.rst.eq(0)
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m.d.comb += self.rdcmd.rst.eq(0)
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with m.If((self.lframe == 0) | (lframesync == 0)):
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m.d.comb += self.wrcmd.rst.eq(1)
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m.d.comb += self.rdcmd.rst.eq(1)
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# Synthetic tristate LAD for looking at in Simulation. Can be removed.
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with m.If(self.lad_en):
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m.d.comb += self.lad_tri.eq(self.lad_out)
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with m.Else():
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m.d.comb += self.lad_tri.eq(self.lad_in)
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return m
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if __name__ == "__main__":
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top = lpcfront()
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with open("lpcfront.v", "w") as f:
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f.write(verilog.convert(top))
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