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import math
from nmigen import Elaboratable, Module, Memory
from nmigen_soc.wishbone import Interface
from nmigen.back import verilog
class ROM(Elaboratable, Interface):
def __init__(self, data, data_width=32): = data
self.size = len(data)
self.data_width = data_width
# Initialize wishbone interface
addr_width = math.ceil(math.log2(self.size + 1))
super().__init__(data_width=data_width, addr_width=addr_width)
def elaborate(self, platform):
m = Module()
data = Memory(width=self.data_width, depth=self.size,
read_port = data.read_port() = read_port
m.d.comb += [
# Ack cycle after cyc and stb are asserted
m.d.sync += self.ack.eq(self.cyc & self.stb)
return m
if __name__ == "__main__":
data = [0x11111111, 0x22222222, 0x33333333, 0x44444444]
top = ROM(data=data)
with open("ROM.v", "w") as f: