forked from librebmc/lpcperipheral
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66 lines
1.9 KiB
Python
66 lines
1.9 KiB
Python
from nmigen import Signal, Elaboratable, Module
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from nmigen.back import verilog
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from nmigen.lib.fifo import SyncFIFOBuffered
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from .vuart import VUart
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class VUartJoined(Elaboratable):
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"""
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Two Virtual UARTs connected together via a FIFO. Presents two 16550
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style interfaces over two wishbone slaves
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Parameters
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----------
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Attributes
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----------
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"""
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def __init__(self, depth=8):
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self.depth = depth
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self.irq_a = Signal()
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self.wb_a = WishboneInterface(data_width=32, addr_width=3, granularity=8)
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self.irq_b = Signal()
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self.wb_b = WishboneInterface(data_width=8, addr_width=3, granularity=8)
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def elaborate(self, platform):
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m = Module()
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m.submodules.fifo_a = fifo_a = SyncFIFOBuffered(width=8, depth=self.depth)
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m.submodules.fifo_b = fifo_b = SyncFIFOBuffered(width=8, depth=self.depth)
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m.submodules.vuart_a = vuart_a = VUart()
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m.submodules.vuart_b = vuart_b = VUart()
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m.d.comb += [
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fifo_a.w_data.eq(vuart_a.w_data),
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vuart_a.w_rdy.eq(fifo_a.w_rdy),
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fifo_a.w_en.eq(vuart_a.w_en),
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vuart_a.r_data.eq(fifo_b.r_data),
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vuart_a.r_rdy.eq(fifo_b.r_rdy),
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fifo_b.r_en.eq(vuart_a.r_en),
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fifo_b.w_data.eq(vuart_b.w_data),
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vuart_b.w_rdy.eq(fifo_b.w_rdy),
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fifo_b.w_en.eq(vuart_b.w_en),
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vuart_b.r_data.eq(fifo_a.r_data),
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vuart_b.r_rdy.eq(fifo_a.r_rdy),
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fifo_a.r_en.eq(vuart_b.r_en),
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self.irq_a.eq(vuart_a.irq),
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self.irq_b.eq(vuart_b.irq),
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self.wb_a.connect(vuart_a.wb),
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self.wb_b.connect(vuart_b.wb),
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]
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return m
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if __name__ == "__main__":
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top = VUartJoined()
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with open("vuart_joined.v", "w") as f:
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f.write(verilog.convert(top))
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