forked from librebmc/lpcperipheral
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318 lines
12 KiB
Python
318 lines
12 KiB
Python
from enum import IntEnum, unique
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from nmigen import Signal, Elaboratable, Module, ResetInserter, Cat
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen.lib.fifo import SyncFIFOBuffered
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from nmigen.back import verilog
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@unique
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class RegEnum(IntEnum):
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BT_CTRL = 0
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BMC2HOST_HOST2BMC = 1
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BT_INTMASK = 2
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@unique
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class BMCRegEnum(IntEnum):
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IRQ_MASK = 0
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IRQ_STATUS = 1
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BT_CTRL = 4
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BMC2HOST_HOST2BMC = 5
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@unique
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class StateEnum(IntEnum):
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IDLE = 0
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ACK = 1
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@unique
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class BMCIRQEnum(IntEnum):
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TARGET_TO_BMC_ATTN = 0
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TARGET_NOT_BUSY = 1
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class IPMI_BT(Elaboratable):
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def __init__(self, depth=64):
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self.depth = depth
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self.bmc_wb = WishboneInterface(data_width=32, addr_width=3, granularity=8)
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self.bmc_irq = Signal()
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self.target_wb = WishboneInterface(data_width=8, addr_width=2)
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self.target_irq = Signal()
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def elaborate(self, platform):
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m = Module()
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# Reset signals for the FIFOs, since BT_CTRL needs to be able to clear them
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reset_from_bmc_fifo = Signal()
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reset_from_target_fifo = Signal()
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m.d.sync += [
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reset_from_bmc_fifo.eq(0),
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reset_from_target_fifo.eq(0)
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]
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# BMC -> Target FIFO
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m.submodules.from_bmc_fifo = from_bmc_fifo = ResetInserter(
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reset_from_bmc_fifo)(SyncFIFOBuffered(width=8, depth=self.depth))
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# Target -> BMC FIFO
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m.submodules.from_target_fifo = from_target_fifo = ResetInserter(
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reset_from_target_fifo)(SyncFIFOBuffered(width=8, depth=self.depth))
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# Wire up wishbone to FIFO write
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m.d.comb += [
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from_bmc_fifo.w_data.eq(self.bmc_wb.dat_w),
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from_target_fifo.w_data.eq(self.target_wb.dat_w)
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]
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# Some wishbone helpers
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is_bmc_write = Signal()
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is_bmc_read = Signal()
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m.d.comb += [
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is_bmc_write.eq(self.bmc_wb.stb & self.bmc_wb.cyc & self.bmc_wb.we),
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is_bmc_read.eq(self.bmc_wb.stb & self.bmc_wb.cyc & ~self.bmc_wb.we)
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]
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is_target_read = Signal()
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is_target_write = Signal()
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m.d.comb += [
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is_target_write.eq(self.target_wb.stb & self.target_wb.cyc & self.target_wb.we),
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is_target_read.eq(self.target_wb.stb & self.target_wb.cyc & ~self.target_wb.we)
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]
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# BMC and target wishbone state machine
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bmc_state = Signal(StateEnum, reset=StateEnum.IDLE)
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target_state = Signal(StateEnum, reset=StateEnum.IDLE)
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m.d.sync += [
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from_bmc_fifo.w_en.eq(0),
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from_bmc_fifo.r_en.eq(0),
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from_target_fifo.w_en.eq(0),
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from_target_fifo.r_en.eq(0)
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]
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m.d.sync += [
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self.bmc_wb.ack.eq(0),
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self.target_wb.ack.eq(0)
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]
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# Don't read from empty FIFOs
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from_bmc_fifo_read_data = Signal(8)
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m.d.comb += from_bmc_fifo_read_data.eq(0)
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with m.If(from_bmc_fifo.r_rdy):
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m.d.comb += from_bmc_fifo_read_data.eq(from_bmc_fifo.r_data)
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from_target_fifo_read_data = Signal(8)
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m.d.comb += from_target_fifo_read_data.eq(0)
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with m.If(from_target_fifo.r_rdy):
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m.d.comb += from_target_fifo_read_data.eq(from_target_fifo.r_data)
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# BT_CTRL bits
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target_to_bmc_attn = Signal()
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bmc_to_target_attn = Signal()
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sms_attn = Signal()
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platform_reserved = Signal()
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bmc_busy = Signal()
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target_busy = Signal()
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bt_ctrl = Signal(8)
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m.d.comb += bt_ctrl.eq(Cat(0, 0, target_to_bmc_attn, bmc_to_target_attn,
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sms_attn, platform_reserved, target_busy,
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bmc_busy))
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# BT_INTMASK (target interrupt mask) bits
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bmc_to_target_irq_en = Signal()
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bmc_to_target_irq = Signal()
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m.d.comb += self.target_irq.eq(bmc_to_target_irq_en & bmc_to_target_irq)
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# BMC interrupt bits. These are not architected by the IPMI BT spec. The
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# Linux driver expects to get an interrupt whenever target_to_bmc_attn
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# goes high (ready to read) or target_busy goes low (ready to write). We
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# don't interrupt on bmc_to_target_attn going low (which is also required
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# for ready to write) but rely on the target driver setting target_busy low
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# right after it sets bmc_to_target_attn low.
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bmc_irq_en = Signal(2)
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bmc_irq = Signal(2)
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m.d.comb += self.bmc_irq.eq(bmc_irq_en & bmc_irq)
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# Target wishbone state machine
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with m.Switch(target_state):
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with m.Case(StateEnum.IDLE):
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with m.If(is_target_write):
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with m.Switch(self.target_wb.adr):
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with m.Case(RegEnum.BT_CTRL):
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# Bit 0, write 1 to clear the write fifo (ie from_target_fifo)
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with m.If(self.target_wb.dat_w[0]):
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m.d.sync += reset_from_target_fifo.eq(1)
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# Bit 1 is meant to set the read FIFO to the next valid
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# position, but since we only have a single buffer this
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# doesn't need to do anything.
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with m.If(self.target_wb.dat_w[2]):
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# Trigger an interrupt whenever we set target_to_bmc_attn
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with m.If(bmc_irq_en[BMCIRQEnum.TARGET_TO_BMC_ATTN]):
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m.d.sync += bmc_irq[BMCIRQEnum.TARGET_TO_BMC_ATTN].eq(1)
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m.d.sync += target_to_bmc_attn.eq(1)
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# Bit 3, write 1 to clear bmc_to_target_attn
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with m.If(self.target_wb.dat_w[3]):
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m.d.sync += bmc_to_target_attn.eq(0)
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# Bit 4, write 1 to clear sms_attn
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with m.If(self.target_wb.dat_w[4]):
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m.d.sync += sms_attn.eq(0)
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# Bit 5, write 1 to set platform reserved
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with m.If(self.target_wb.dat_w[5]):
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m.d.sync += platform_reserved.eq(1)
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# Bit 6, write 1 to toggle target_busy
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with m.If(self.target_wb.dat_w[6]):
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# Trigger an interrupt whenever we clear target_busy
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with m.If(target_busy & bmc_irq_en[BMCIRQEnum.TARGET_NOT_BUSY]):
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m.d.sync += bmc_irq[BMCIRQEnum.TARGET_NOT_BUSY].eq(1)
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m.d.sync += target_busy.eq(~target_busy)
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# Bit 7, read only
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with m.Case(RegEnum.BMC2HOST_HOST2BMC):
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# Only assert write if there is space
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m.d.sync += from_target_fifo.w_en.eq(from_target_fifo.w_rdy)
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with m.Case(RegEnum.BT_INTMASK):
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# Bit 0, 0/1 write
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m.d.sync += bmc_to_target_irq_en.eq(self.target_wb.dat_w[0])
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# Bit 1, write 1 to clear interrupt
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with m.If(self.target_wb.dat_w[1]):
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m.d.sync += bmc_to_target_irq.eq(0)
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m.d.sync += [
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self.target_wb.ack.eq(1),
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target_state.eq(StateEnum.ACK)
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]
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with m.If(is_target_read):
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with m.Switch(self.target_wb.adr):
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with m.Case(RegEnum.BT_CTRL):
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m.d.sync += self.target_wb.dat_r.eq(bt_ctrl)
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with m.Case(RegEnum.BMC2HOST_HOST2BMC):
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m.d.sync += [
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self.target_wb.dat_r.eq(from_bmc_fifo_read_data),
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from_bmc_fifo.r_en.eq(from_bmc_fifo.r_rdy),
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]
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with m.Case(RegEnum.BT_INTMASK):
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m.d.sync += self.target_wb.dat_r.eq(Cat(bmc_to_target_irq_en, bmc_to_target_irq))
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m.d.sync += [
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self.target_wb.ack.eq(1),
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target_state.eq(StateEnum.ACK)
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]
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with m.Case(StateEnum.ACK):
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m.d.sync += [
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self.target_wb.ack.eq(0),
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target_state.eq(StateEnum.IDLE),
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]
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# BMC wishbone state machine
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with m.Switch(bmc_state):
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with m.Case(StateEnum.IDLE):
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with m.If(is_bmc_write):
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with m.Switch(self.bmc_wb.adr):
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with m.Case(BMCRegEnum.BT_CTRL):
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# Bit 0, write 1 to clear the write fifo (ie from_bmc_fifo)
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with m.If(self.bmc_wb.dat_w[0]):
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m.d.sync += reset_from_bmc_fifo.eq(1)
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# Bit 1 is meant to set the read FIFO to the next valid
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# position, but since we only have a single buffer this
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# doesn't need to do anything.
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# Bit 2, write to clear target_to_bmc_attn
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with m.If(self.bmc_wb.dat_w[2]):
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m.d.sync += target_to_bmc_attn.eq(0)
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# Bit 3, write 1 to set bmc_to_target_attn
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with m.If(self.bmc_wb.dat_w[3]):
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# Trigger an interrupt whenever we set bmc_to_target_attn
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with m.If(bmc_to_target_irq_en):
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m.d.sync += bmc_to_target_irq.eq(1)
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m.d.sync += bmc_to_target_attn.eq(1)
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# Bit 4, write 1 to set sms_attn
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with m.If(self.bmc_wb.dat_w[4]):
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# Trigger an interrupt whenever we set sms_attn
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with m.If(bmc_to_target_irq_en):
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m.d.sync += bmc_to_target_irq.eq(1)
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m.d.sync += sms_attn.eq(1)
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# Bit 5, write 1 to clear platform reserved
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with m.If(self.bmc_wb.dat_w[5]):
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m.d.sync += platform_reserved.eq(0)
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# Bit 6, read only
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# Bit 7, write 1 to toggle bmc_busy
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with m.If(self.bmc_wb.dat_w[7]):
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m.d.sync += bmc_busy.eq(~bmc_busy)
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with m.Case(BMCRegEnum.BMC2HOST_HOST2BMC):
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# Only assert write if there is space
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m.d.sync += from_bmc_fifo.w_en.eq(from_bmc_fifo.w_rdy)
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with m.Case(BMCRegEnum.IRQ_MASK):
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m.d.sync += bmc_irq_en.eq(self.bmc_wb.dat_w)
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with m.Case(BMCRegEnum.IRQ_STATUS):
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m.d.sync += bmc_irq.eq(self.bmc_wb.dat_w)
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m.d.sync += [
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self.bmc_wb.ack.eq(1),
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bmc_state.eq(StateEnum.ACK)
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]
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with m.If(is_bmc_read):
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with m.Switch(self.bmc_wb.adr):
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with m.Case(BMCRegEnum.BT_CTRL):
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m.d.sync += self.bmc_wb.dat_r.eq(bt_ctrl)
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with m.Case(BMCRegEnum.BMC2HOST_HOST2BMC):
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m.d.sync += [
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self.bmc_wb.dat_r.eq(from_target_fifo_read_data),
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from_target_fifo.r_en.eq(from_target_fifo.r_rdy),
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]
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with m.Case(BMCRegEnum.IRQ_MASK):
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m.d.sync += self.bmc_wb.dat_r.eq(bmc_irq_en)
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with m.Case(BMCRegEnum.IRQ_STATUS):
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m.d.sync += self.bmc_wb.dat_r.eq(bmc_irq)
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m.d.sync += [
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self.bmc_wb.ack.eq(1),
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bmc_state.eq(StateEnum.ACK)
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]
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with m.Case(StateEnum.ACK):
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m.d.sync += [
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self.bmc_wb.ack.eq(0),
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bmc_state.eq(StateEnum.IDLE),
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]
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return m
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if __name__ == "__main__":
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top = IPMI_BT()
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with open("ipmi_bt.v", "w") as f:
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f.write(verilog.convert(top))
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