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152 lines
5.3 KiB
Python
152 lines
5.3 KiB
Python
import unittest
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from nmigen.sim import Simulator
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from lpcperipheral.vuart import VUart, RegEnum, LCR_DLAB
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from .helpers import Helpers
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class TestSum(unittest.TestCase, Helpers):
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def setUp(self):
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self.dut = VUart()
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def test_vuart(self):
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def bench():
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yield
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# Test reading and writing to LCR, MCR, MSR, SCR
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val = 0xF
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for r in (RegEnum.LCR, RegEnum.MCR, RegEnum.MSR, RegEnum.SCR):
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yield from self.wishbone_write(self.dut.wb, r, val)
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yield from self.wishbone_read(self.dut.wb, r, val)
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val = val + 1
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# Test writing to FCR (write only)
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yield from self.wishbone_write(self.dut.wb, RegEnum.IIR_FCR, val)
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# Test reading from LSR (THRE and TEMT bits should be set)
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yield from self.wishbone_read(self.dut.wb, RegEnum.LSR, 0b01100000)
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# Test reading from LSR with data ready (RD, THRE and TEMT bits should be set)
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yield self.dut.r_rdy.eq(1)
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yield from self.wishbone_read(self.dut.wb, RegEnum.LSR, 0b01100001)
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# Set DLAB bit
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yield from self.wishbone_write(self.dut.wb, RegEnum.LCR, 1 << LCR_DLAB)
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# Test reading and writing to DLL and DLM
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for r in (RegEnum.RXTX_DLL, RegEnum.IER_DLM):
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yield from self.wishbone_write(self.dut.wb, r, val)
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yield from self.wishbone_read(self.dut.wb, r, val)
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val = val + 1
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# Clear DLAB bit
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yield from self.wishbone_write(self.dut.wb, RegEnum.LCR, 0x00)
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# Test read from non empty FIFO
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yield self.dut.r_rdy.eq(1)
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yield self.dut.r_data.eq(0x45)
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yield from self.wishbone_read(self.dut.wb, RegEnum.RXTX_DLL, 0x45)
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self.assertEqual((yield self.dut.r_en), 1)
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self.assertEqual((yield self.dut.r_data), 0x45)
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yield
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self.assertEqual((yield self.dut.r_en), 0)
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# Test read from empty FIFO, check we don't attempt a read from the FIFO
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# and we return 0 over wishbone
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yield self.dut.r_rdy.eq(0)
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yield self.dut.r_data.eq(0x33)
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yield from self.wishbone_read(self.dut.wb, RegEnum.RXTX_DLL, 0x00)
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self.assertEqual((yield self.dut.r_en), 0)
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yield
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self.assertEqual((yield self.dut.r_en), 0)
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# Test write to non full FIFO
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yield self.dut.w_rdy.eq(1)
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yield from self.wishbone_write(self.dut.wb, RegEnum.RXTX_DLL, 0x65)
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self.assertEqual((yield self.dut.w_en), 1)
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self.assertEqual((yield self.dut.w_data), 0x65)
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yield
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self.assertEqual((yield self.dut.w_en), 0)
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# Test write to full FIFO
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yield self.dut.w_rdy.eq(0)
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yield from self.wishbone_write(self.dut.wb, RegEnum.RXTX_DLL, 0x77)
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self.assertEqual((yield self.dut.w_en), 0)
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# XXX Need to test ier lsr
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# IIR - read only
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# IER
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_vuart.vcd"):
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sim.run()
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def test_vuart_irqs(self):
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def bench():
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yield
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# Clear DLAB bit
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yield from self.wishbone_write(self.dut.wb, RegEnum.LCR, 0x00)
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# Test RX irq
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# No irqs if IER=0
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yield from self.wishbone_write(self.dut.wb, RegEnum.IER_DLM, 0x0)
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self.assertEqual((yield self.dut.irq), 0)
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yield from self.wishbone_read(self.dut.wb, RegEnum.IIR_FCR, 0b0001)
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# Set RX FIFO not empty
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yield self.dut.r_rdy.eq(1)
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yield self.dut.r_data.eq(0x45)
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yield
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self.assertEqual((yield self.dut.irq), 0)
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yield from self.wishbone_read(self.dut.wb, RegEnum.IIR_FCR, 0b0001)
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# RX irq if bit 1 is set
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yield from self.wishbone_write(self.dut.wb, RegEnum.IER_DLM, 0x1)
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yield
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self.assertEqual((yield self.dut.irq), 1)
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yield from self.wishbone_read(self.dut.wb, RegEnum.IIR_FCR, 0b0100)
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# No RX irq if IER=1 but empty RX FIFO
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yield self.dut.r_rdy.eq(0)
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yield self.dut.r_data.eq(0x00)
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yield
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self.assertEqual((yield self.dut.irq), 0)
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yield from self.wishbone_read(self.dut.wb, RegEnum.IIR_FCR, 0b0001)
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# Test TX irq
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# TX irq whenever IER bit 2 is set
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yield from self.wishbone_write(self.dut.wb, RegEnum.IER_DLM, 0x2)
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yield
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self.assertEqual((yield self.dut.irq), 1)
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yield from self.wishbone_read(self.dut.wb, RegEnum.IIR_FCR, 0b0010)
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# Test TX and RX irq together
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# Test RX irq priority over TX
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yield from self.wishbone_write(self.dut.wb, RegEnum.IER_DLM, 0x3)
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yield self.dut.r_rdy.eq(1)
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yield self.dut.r_data.eq(0x45)
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yield
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self.assertEqual((yield self.dut.irq), 1)
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yield from self.wishbone_read(self.dut.wb, RegEnum.IIR_FCR, 0b0100)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_vuart_irqs.vcd"):
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sim.run()
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if __name__ == '__main__':
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unittest.main()
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