forked from librebmc/lpcperipheral
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251 lines
13 KiB
Python
251 lines
13 KiB
Python
import unittest
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from nmigen.sim import Simulator
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from lpcperipheral.ipmi_bt import IPMI_BT, RegEnum, BMCRegEnum
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from .helpers import Helpers
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class TestSum(unittest.TestCase, Helpers):
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def setUp(self):
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self.dut = IPMI_BT(depth=64)
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def test_fifo(self):
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def bench():
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yield
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# Write one byte from target and read from BMC
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0x12)
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yield
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0x12)
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# Write 64 bytes from target and read from BMC
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for i in range(0, 64):
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, i)
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for i in range(0, 64):
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, i)
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# Write one byte from BMC and read from target
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0x12)
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yield
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0x12)
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# Write 64 bytes from BMC and read from target
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for i in range(0, 64):
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, i)
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for i in range(0, 64):
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, i)
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# Read from empty FIFO (should read 0)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0)
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# Write to full FIFO (should do nothing)
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for i in range(0, 65):
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, i)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, i)
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for i in range(0, 64):
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, i)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, i)
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# Test reset of target fifo from target
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for i in range(0, 64):
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0x5a)
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 0x1)
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0x98)
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yield # Need a cycle between writing the FIFO and reading it
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0x98)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0)
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# Test reset of BMC fifo from BMC
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for i in range(0, 64):
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0xa5)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 0x1)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BMC2HOST_HOST2BMC, 0x78)
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yield # Need a cycle between writing the FIFO and reading it
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0x78)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BMC2HOST_HOST2BMC, 0)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_ipmi_bt_fifo.vcd"):
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sim.run()
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def test_ctrl(self):
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def bench():
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# Init value for BT_CTRL
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 0)
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# BT_CTRL bits 2, 5: target set, BMC clear
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for b in (2, 5):
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0x0)
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# Write 1 on BMC, should do nothing
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 0)
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# Write 1 from target
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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# Check for 1 on target and bmc
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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# Write 1 on target, should do nothing
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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# Write 1 on bmc, should clear bit
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 0)
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# BT_CTRL bits 3, 4: BMC set, target clear
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for b in (3, 4):
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0x0)
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# Write 1 on target, should do nothing
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0)
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# Write 1 from BMC
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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# Check for 1 on target and bmc
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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# Write 1 on BMC, should do nothing
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << b)
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# Write 1 on target, should clear bit
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << b)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0)
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# BT_CTRL bit 6
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# Set bit, read from both target and BMC
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 6)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 6)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 6)
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# Writing from BMC should do nothing
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 6)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 6)
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# Writing from target should clear
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 6)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0)
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# BT_CTRL bit 7
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# Set bit, read from both target and BMC
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 7)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 7)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 7)
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# Writing from target should do nothing
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 7)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 7)
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# Writing from BMC should clear
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 7)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0)
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# Read and write all bits in BT_CTRL from the target side
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 0xff)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_CTRL, 0x64)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_ipmi_bt_ctrl.vcd"):
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sim.run()
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def test_target_interrupts(self):
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def bench():
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# Test reading/writing BT_INTMASK from target. Only the bottom bit should be
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# writeable
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_INTMASK, 0xff)
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yield from self.wishbone_read(self.dut.target_wb, RegEnum.BT_INTMASK, 0x1)
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_INTMASK, 0x0)
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# With interrupts masked, shouldn't get an interrupt
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self.assertEqual((yield self.dut.target_irq), 0)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 3)
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self.assertEqual((yield self.dut.target_irq), 0)
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# With interrupt unmasked, should get interrupt, but only on a 0-1 transition
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_INTMASK, 1 << 0)
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self.assertEqual((yield self.dut.target_irq), 0)
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# Clear
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 3)
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self.assertEqual((yield self.dut.target_irq), 0)
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# and reassert
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 3)
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self.assertEqual((yield self.dut.target_irq), 1)
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# Test the interrupt masking bit
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_INTMASK, 0x0)
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self.assertEqual((yield self.dut.target_irq), 0)
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_INTMASK, 0x1)
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self.assertEqual((yield self.dut.target_irq), 1)
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# Finally ack it
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_INTMASK, 0x2)
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self.assertEqual((yield self.dut.target_irq), 0)
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_ipmi_bt_target_interrupts.vcd"):
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sim.run()
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def test_bmc_interrupts(self):
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def bench():
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# Test reading/writing IRQ_MASK from BMC. Only the bottom two bits should be
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# writeable
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_MASK, 0xff)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.IRQ_MASK, 0x3)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_MASK, 0x0)
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# Test reading/writing IRQ_STATUS from BMC. Only the bottom two bits should be
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# writeable
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_STATUS, 0xff)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.IRQ_STATUS, 0x3)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_STATUS, 0x0)
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# With interrupts masked, shouldn't get an interrupt
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self.assertEqual((yield self.dut.bmc_irq), 0)
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yield from self.wishbone_write(self.dut.target_wb, BMCRegEnum.BT_CTRL, 1 << 2)
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self.assertEqual((yield self.dut.bmc_irq), 0)
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# With interrupt unmasked, should get interrupt, but only on a 0-1 transition
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_MASK, 1 << 0)
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self.assertEqual((yield self.dut.bmc_irq), 0)
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# Clear
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.BT_CTRL, 1 << 2)
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self.assertEqual((yield self.dut.bmc_irq), 0)
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# and reassert
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yield from self.wishbone_write(self.dut.target_wb, RegEnum.BT_CTRL, 1 << 2)
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self.assertEqual((yield self.dut.bmc_irq), 1)
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# Test the interrupt masking bit
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_MASK, 0x0)
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self.assertEqual((yield self.dut.bmc_irq), 0)
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_MASK, 0x1)
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self.assertEqual((yield self.dut.bmc_irq), 1)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.IRQ_STATUS, 0x1)
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# Finally ack it
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yield from self.wishbone_write(self.dut.bmc_wb, BMCRegEnum.IRQ_STATUS, 0x0)
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self.assertEqual((yield self.dut.bmc_irq), 0)
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yield from self.wishbone_read(self.dut.bmc_wb, BMCRegEnum.IRQ_STATUS, 0x0)
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# Test target busy goes low interrupt
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(bench)
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with sim.write_vcd("test_ipmi_bt_target_interrupts.vcd"):
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sim.run()
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if __name__ == '__main__':
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unittest.main()
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