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200 lines
9.0 KiB
Python
200 lines
9.0 KiB
Python
#
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# This is an LPC slave to wishbone interface
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#
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# LPC Clock | System Clock
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#
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# +---------+ +------------+ +--------+
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# LPC | | | ASYNC | | | Wishbone
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# pins | +---->| FIFO WR +---->| | IO Space
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# | LPC | | | | |<-------->
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# <------>| Front | +------------+ | LOGIC |
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# | | | |
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# | | +------------+ | | Wishbone
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# | | | ASYNC | | | FW Space
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# | |<----+ FIFO RD |<----+ |<-------->
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# | | | | | |
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# +---------+ +------------+ +--------+
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#
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# It takes the lpcfront and and turns it into IO and FW wishbone
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# interfaces. The lpcfront operates on the lpc clock domain and the
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# wishbone interfaces operate on the standard "sync" domain.
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#
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# To cross the clock domains async fifos are used. The write fifo
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# takes write commands from the lpc interface. The read fifo gets
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# information back to respond to these write commands.
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#
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# The write fifo turns the write commands into either an IO or FW
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# wishbone transaction. The read fifo takes the wishbone transaction
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# reponses and sends them back to the LPC.
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#
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# If an address doesn't exist on the wishbone interfaces (common on
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# the IO bus), the wishbone interface asserts the err signal (rather
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# than the ack). When this occurs the read fifo send an error back to
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# the LPC.
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#
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from nmigen import Signal, Elaboratable, Module
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from nmigen import ClockSignal, Cat, DomainRenamer, ResetSignal, ResetInserter
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from nmigen.lib.fifo import AsyncFIFO
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen.back import verilog
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from .lpcfront import lpcfront, LPCCycletype, LPC_FW_DATA_WIDTH, LPC_FW_ADDR_WIDTH, LPC_IO_DATA_WIDTH, LPC_IO_ADDR_WIDTH
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class lpc2wb(Elaboratable):
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def __init__(self):
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# LPC clock pin
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self.lclk = Signal()
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self.lframe = Signal()
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self.lad_in = Signal(4)
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self.lad_out = Signal(4)
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self.lad_en = Signal()
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self.lreset = Signal()
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self.io_wb = WishboneInterface(data_width=LPC_IO_DATA_WIDTH,
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addr_width=LPC_IO_ADDR_WIDTH,
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granularity=8,
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features = ["err"])
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# 32 bit bus, so address only need to address words
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self.fw_wb = WishboneInterface(data_width=LPC_FW_DATA_WIDTH,
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addr_width=LPC_FW_ADDR_WIDTH - 2,
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granularity=8)
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def elaborate(self, platform):
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m = Module()
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# hook up lclk port to lclk domain
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m.d.comb += ClockSignal("lclk").eq(self.lclk)
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# Use main reset to reset lclk domain
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m.d.comb += ResetSignal("lclk").eq(ResetSignal())
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# create lpc front end wth right clock domain
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m.submodules.lpc = lpc = DomainRenamer("lclk")(lpcfront())
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wr_data = Signal(lpc.wrcmd.data.width)
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wr_addr = Signal(lpc.wrcmd.addr.width)
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wr_cmd = Signal(lpc.wrcmd.cmd.width)
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wr_size = Signal(lpc.wrcmd.size.width)
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wr_rdy = Signal()
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# hook up lclk port to lclk domain
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m.d.comb += ClockSignal("lclkrst").eq(self.lclk)
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# Use main reset to reset lclk domain
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m.d.comb += ResetSignal("lclkrst").eq(lpc.wrcmd.rst)
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# hook up external lpc interface
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m.d.comb += lpc.lframe.eq(self.lframe)
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m.d.comb += lpc.lreset.eq(self.lreset)
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m.d.comb += lpc.lad_in.eq(self.lad_in)
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m.d.comb += self.lad_en.eq(lpc.lad_en)
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m.d.comb += self.lad_out.eq(lpc.lad_out)
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# We have two fifo
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# 1) fifowr for getting commands from the LPC and transferring them
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# to the wishbone. This has address for writes and reads, data
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# for writes and cmd (IO read/write)
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# 2) fiford for getting read data from the wishbone back to the LPC.
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fifowr = AsyncFIFO(width=lpc.wrcmd.width(), depth=2,
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r_domain="sync",
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w_domain="lclkrst")
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m.submodules += fifowr
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fiford = AsyncFIFO(width=lpc.rdcmd.width(), depth=2,
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r_domain="lclkrst",
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w_domain="sync")
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m.submodules += fiford
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# lpc clock side
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m.d.comb += fifowr.w_data[ 0:32].eq(lpc.wrcmd.data)
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m.d.comb += fifowr.w_data[32:60].eq(lpc.wrcmd.addr)
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m.d.comb += fifowr.w_data[60:62].eq(lpc.wrcmd.cmd)
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m.d.comb += fifowr.w_data[62:64].eq(lpc.wrcmd.size)
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m.d.comb += lpc.wrcmd.rdy.eq(fifowr.w_rdy)
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m.d.comb += fifowr.w_en.eq(lpc.wrcmd.en)
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# system clock side
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m.d.comb += wr_data.eq(fifowr.r_data[ 0:32]) # sliced as above
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m.d.comb += wr_addr.eq(fifowr.r_data[32:60]) # sliced as above
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m.d.comb += wr_cmd.eq (fifowr.r_data[60:62]) # sliced as above
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m.d.comb += wr_size.eq(fifowr.r_data[62:64]) # sliced as above
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m.d.comb += wr_rdy.eq(fifowr.r_rdy)
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m.d.comb += fifowr.r_en.eq(0) # See below for wishbone acks
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# turn fifowr into IO wishbone master
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m.d.comb += self.io_wb.adr.eq(wr_addr[0:16])
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m.d.comb += self.io_wb.dat_w.eq(wr_data[0:8])
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m.d.comb += self.io_wb.sel.eq(1)
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m.d.comb += self.io_wb.we.eq(wr_cmd == LPCCycletype.IOWR)
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with m.If ((wr_cmd == LPCCycletype.IORD) | (wr_cmd == LPCCycletype.IOWR)):
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# The fiford should always be ready here but check anyway
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m.d.comb += self.io_wb.cyc.eq(wr_rdy & fiford.w_rdy)
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m.d.comb += self.io_wb.stb.eq(wr_rdy & fiford.w_rdy)
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# turn fifowr into FW wishbone master
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m.d.comb += self.fw_wb.adr.eq(wr_addr[2:28])
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# data comes in the MSB so we need to shift it down for smaller sizes
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m.d.comb += self.fw_wb.dat_w.eq(wr_data)
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with m.If (wr_size == 3):
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m.d.comb += self.fw_wb.sel.eq(0b1111)
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with m.If (wr_size == 1):
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with m.If (wr_addr[1] == 0b0):
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m.d.comb += self.fw_wb.sel.eq(0b0011)
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with m.If (wr_addr[1] == 0b1):
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m.d.comb += self.fw_wb.sel.eq(0b1100)
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m.d.comb += self.fw_wb.dat_w.eq(wr_data << 16)
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with m.If (wr_size == 0):
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with m.If (wr_addr[0:2] == 0b00):
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m.d.comb += self.fw_wb.sel.eq(0b0001)
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with m.If (wr_addr[0:2] == 0b01):
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m.d.comb += self.fw_wb.sel.eq(0b0010)
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m.d.comb += self.fw_wb.dat_w.eq(wr_data << 8)
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with m.If (wr_addr[0:2] == 0b10):
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m.d.comb += self.fw_wb.sel.eq(0b0100)
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m.d.comb += self.fw_wb.dat_w.eq(wr_data << 16)
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with m.If (wr_addr[0:2] == 0b11):
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m.d.comb += self.fw_wb.sel.eq(0b1000)
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m.d.comb += self.fw_wb.dat_w.eq(wr_data << 24)
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m.d.comb += self.fw_wb.we.eq(wr_cmd == LPCCycletype.FWWR)
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with m.If ((wr_cmd == LPCCycletype.FWRD) | (wr_cmd == LPCCycletype.FWWR)):
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# The fiford should always be ready here but check anyway
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m.d.comb += self.fw_wb.cyc.eq(wr_rdy & fiford.w_rdy)
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m.d.comb += self.fw_wb.stb.eq(wr_rdy & fiford.w_rdy)
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# Arbitrate the acks back into the fifo
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with m.If ((wr_cmd == LPCCycletype.IORD) | (wr_cmd == LPCCycletype.IOWR)):
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m.d.comb += fifowr.r_en.eq(self.io_wb.ack | self.io_wb.err)
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m.d.comb += fiford.w_data[32].eq(self.io_wb.err)
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with m.If ((wr_cmd == LPCCycletype.FWRD) | (wr_cmd == LPCCycletype.FWWR)):
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m.d.comb += fifowr.r_en.eq(self.fw_wb.ack)
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m.d.comb += fiford.w_data[32].eq(0)
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# sending data back from IO/FW wishbones to fiford
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with m.If (wr_cmd == LPCCycletype.IORD):
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m.d.comb += fiford.w_data[0:32].eq(self.io_wb.dat_r)
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with m.Elif (wr_cmd == LPCCycletype.FWRD):
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m.d.comb += fiford.w_data[0:32].eq(self.fw_wb.dat_r)
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with m.If (wr_size == 1):
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with m.If (wr_addr[1] == 0b1):
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m.d.comb += fiford.w_data[0:16].eq(self.fw_wb.dat_r[16:32])
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with m.If (wr_size == 0):
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with m.If (wr_addr[0:2] == 0b01):
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m.d.comb += fiford.w_data[0:8].eq(self.fw_wb.dat_r[8:16])
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with m.If (wr_addr[0:2] == 0b10):
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m.d.comb += fiford.w_data[0:8].eq(self.fw_wb.dat_r[16:24])
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with m.If (wr_addr[0:2] == 0b11):
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m.d.comb += fiford.w_data[0:8].eq(self.fw_wb.dat_r[24:32])
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m.d.comb += fiford.w_en.eq(self.io_wb.ack | self.fw_wb.ack | self.io_wb.err)
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# lpc side of read fiford
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m.d.comb += fiford.r_en.eq(lpc.rdcmd.en)
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m.d.comb += lpc.rdcmd.data.eq(fiford.r_data[0:32])
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m.d.comb += lpc.rdcmd.error.eq(fiford.r_data[32])
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m.d.comb += lpc.rdcmd.rdy.eq(fiford.r_rdy)
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return m
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if __name__ == "__main__":
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top = lpc2wb()
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with open("lpc2wb.v", "w") as f:
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f.write(verilog.convert(top))
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