forked from librebmc/lpcperipheral
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99 lines
3.9 KiB
Python
99 lines
3.9 KiB
Python
from nmigen import Elaboratable, Module, Signal
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from nmigen.back import verilog
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from nmigen_soc.wishbone import Decoder as WishboneDecoder
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from nmigen_soc.wishbone import Interface as WishboneInterface
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from nmigen_soc.memory import MemoryMap
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from .ipmi_bt import IPMI_BT
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from .vuart_joined import VUartJoined
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class IOSpace(Elaboratable):
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def __init__(self, vuart_depth=2048, bmc_vuart_addr=0x0, bmc_ipmi_addr=0x1000,
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bmc_lpc_ctrl_addr=0x2000,
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target_vuart_addr=0x3f8, target_ipmi_addr=0xe4):
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self.vuart_depth = vuart_depth
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self.bmc_vuart_addr = bmc_vuart_addr
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self.bmc_ipmi_addr = bmc_ipmi_addr
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self.bmc_lpc_ctrl_addr = bmc_lpc_ctrl_addr
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self.target_vuart_addr = target_vuart_addr
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self.target_ipmi_addr = target_ipmi_addr
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self.bmc_vuart_irq = Signal()
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self.bmc_ipmi_irq = Signal()
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self.bmc_wb = WishboneInterface(addr_width=14, data_width=32, granularity=8)
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self.lpc_ctrl_wb = WishboneInterface(addr_width=3, data_width=32, granularity=8)
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self.target_vuart_irq = Signal()
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self.target_ipmi_irq = Signal()
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self.target_wb = WishboneInterface(addr_width=16, data_width=8, features=["err"])
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self.error_wb = WishboneInterface(addr_width=2, data_width=8,
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features=["err"])
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def elaborate(self, platform):
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m = Module()
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m.submodules.vuart_joined = vuart_joined = VUartJoined(depth=self.vuart_depth)
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m.submodules.ipmi_bt = ipmi_bt = IPMI_BT()
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# BMC address decode
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m.submodules.bmc_decode = bmc_decode = WishboneDecoder(addr_width=14, data_width=32, granularity=8)
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bmc_ipmi_bus = ipmi_bt.bmc_wb
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bmc_ipmi_bus.memory_map = MemoryMap(addr_width=5, data_width=8)
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bmc_decode.add(bmc_ipmi_bus, addr=self.bmc_ipmi_addr)
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bmc_vuart_bus = vuart_joined.wb_a
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bmc_vuart_bus.memory_map = MemoryMap(addr_width=5, data_width=8)
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bmc_decode.add(bmc_vuart_bus, addr=self.bmc_vuart_addr)
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lpc_ctrl_bus = self.lpc_ctrl_wb
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lpc_ctrl_bus.memory_map = MemoryMap(addr_width=5, data_width=8)
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bmc_decode.add(lpc_ctrl_bus, addr=self.bmc_lpc_ctrl_addr)
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m.d.comb += [
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self.bmc_ipmi_irq.eq(ipmi_bt.bmc_irq),
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self.bmc_vuart_irq.eq(vuart_joined.irq_a),
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self.bmc_wb.connect(bmc_decode.bus)
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]
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# Target address decode
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m.submodules.target_decode = target_decode = WishboneDecoder(addr_width=16, data_width=8, granularity=8, features=["err"])
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target_ipmi_bus = ipmi_bt.target_wb
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target_ipmi_bus.memory_map = MemoryMap(addr_width=2, data_width=8)
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target_decode.add(target_ipmi_bus, addr=self.target_ipmi_addr)
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target_vuart_bus = vuart_joined.wb_b
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target_vuart_bus.memory_map = MemoryMap(addr_width=3, data_width=8)
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target_decode.add(target_vuart_bus, addr=self.target_vuart_addr)
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target_error_bus = self.error_wb
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target_error_bus.memory_map = MemoryMap(addr_width=2, data_width=8)
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# Generate a signal when we'd expect an ACK on the target bus
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ack_expected = Signal()
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m.d.sync += ack_expected.eq(self.target_wb.sel & self.target_wb.cyc &
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~ack_expected)
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# Generate an error if no ack from ipmi_bt or vuart
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m.d.comb += self.error_wb.err.eq(0)
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with m.If (ack_expected):
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m.d.comb += self.error_wb.err.eq(~ipmi_bt.target_wb.ack &
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~vuart_joined.wb_b.ack)
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target_decode.add(target_error_bus, addr=0x0)
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m.d.comb += [
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self.target_ipmi_irq.eq(ipmi_bt.target_irq),
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self.target_vuart_irq.eq(vuart_joined.irq_b),
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self.target_wb.connect(target_decode.bus)
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]
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return m
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if __name__ == "__main__":
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top = IOSpace()
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with open("io_map.v", "w") as f:
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f.write(verilog.convert(top))
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