From 0d4c7bd55a8adba6afcf5750525c249cf5a91604 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Tue, 5 Oct 2021 12:41:23 +1100 Subject: [PATCH] ci: add github actions workflow Add running the unit tests and building the verilog output. Signed-off-by: Michael Neuling --- .github/workflows/test.yml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 0000000..a1327f5 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,18 @@ +name: test +on: [push] +jobs: + Unittests: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - run: pip3 install 'git+https://github.com/nmigen/nmigen.git' + - run: pip3 install 'git+https://github.com/nmigen/nmigen-soc.git' + - run: python -m unittest -v + + Verilog: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - run: pip install git+https://github.com/nmigen/nmigen.git#egg=nmigen[builtin-yosys] + - run: pip3 install 'git+https://github.com/nmigen/nmigen-soc.git' + - run: python -m lpcperipheral.lpcperipheral \ No newline at end of file