Fix LPC CTRL I/O wishbone, and remove hard coded values

We weren't hooking up the I/O wishbone to the LPC CTRL interface.
Also remove the base/offset values we hardcoded during bringup.

Signed-off-by: Anton Blanchard <anton@ozlabs.org>
master^2
Anton Blanchard 2 years ago
parent 4eee8df8e6
commit 51f6c5882d

@ -26,11 +26,11 @@ class LPC_Ctrl(Elaboratable):
m = Module()

base_lo_csr = CSRElement(32, "rw")
base_lo = Signal(32, reset=192*1024*1024)
base_lo = Signal(32)
# Leave space for upper 32 bits, unused for now
base_hi_csr = CSRElement(32, "rw")
mask_lo_csr = CSRElement(32, "rw")
mask_lo = Signal(32, reset=0x3FFFFFF)
mask_lo = Signal(32)
# Leave space for upper 32 bits, unused for now
mask_hi_csr = CSRElement(32, "rw")

@ -56,7 +56,7 @@ class LPC_Ctrl(Elaboratable):

m.d.comb += [
self.lpc_wb.connect(self.dma_wb),
# bask/mask are in bytes, so convert to wishbone addresses
# base/mask are in bytes, so convert to wishbone addresses
self.dma_wb.adr.eq((self.lpc_wb.adr & (mask_lo >> 2)) | (base_lo >> 2))
]


@ -98,9 +98,12 @@ class LPCPeripheral(Elaboratable):
lpc_ctrl.dma_wb.dat_r.eq(self.dma_dat_r),
lpc_ctrl.dma_wb.ack.eq(self.dma_ack),

# LPC to LPC CTRL wishbone
# LPC to LPC CTRL DMA wishbone
lpc.fw_wb.connect(lpc_ctrl.lpc_wb),

# LPC CTRL I/O wishbone
io.lpc_ctrl_wb.connect(lpc_ctrl.io_wb),

# LPC
lpc.lclk.eq(self.lclk),
lpc.lframe.eq(self.lframe),

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