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105 lines
2.9 KiB
VHDL
105 lines
2.9 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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ENTITY fuq_tblmul_bthdcd IS
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PORT(
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i0 :in std_ulogic;
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i1 :in std_ulogic;
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i2 :in std_ulogic;
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s_neg :out std_ulogic;
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s_x :out std_ulogic;
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s_x2 :out std_ulogic
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);
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END fuq_tblmul_bthdcd;
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ARCHITECTURE fuq_tblmul_bthdcd OF fuq_tblmul_bthdcd IS
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signal s_add :std_ulogic;
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signal sx1_a0_b :std_ulogic;
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signal sx1_a1_b :std_ulogic;
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signal sx1_t :std_ulogic;
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signal sx1_i :std_ulogic;
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signal sx2_a0_b :std_ulogic;
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signal sx2_a1_b :std_ulogic;
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signal sx2_t :std_ulogic;
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signal sx2_i :std_ulogic;
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signal i0_b, i1_b, i2_b :std_ulogic;
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BEGIN
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u_0i: i0_b <= not( i0 );
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u_1i: i1_b <= not( i1 );
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u_2i: i2_b <= not( i2 );
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u_add: s_add <= not( i0 );
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u_sub: s_neg <= not( s_add );
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u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ;
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u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ;
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u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ;
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u_sx1_i: sx1_i <= not( sx1_t );
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u_sx1_ii: s_x <= not( sx1_i );
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u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ;
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u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ;
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u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ;
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u_sx2_i: sx2_i <= not( sx2_t );
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u_sx2_ii: s_x2 <= not( sx2_i );
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END;
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