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429 lines
18 KiB
VHDL
429 lines
18 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity fuq_lza is
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generic( expand_type: integer := 2 );
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port(
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vdd :inout power_logic;
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gnd :inout power_logic;
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clkoff_b :in std_ulogic;
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act_dis :in std_ulogic;
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flush :in std_ulogic;
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delay_lclkr :in std_ulogic_vector(3 to 4);
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mpw1_b :in std_ulogic_vector(3 to 4);
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mpw2_b :in std_ulogic_vector(0 to 0);
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sg_1 :in std_ulogic;
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thold_1 :in std_ulogic;
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fpu_enable :in std_ulogic;
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nclk :in clk_logic;
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f_lza_si :in std_ulogic;
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f_lza_so :out std_ulogic;
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ex1_act_b :in std_ulogic;
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f_sa3_ex3_s :in std_ulogic_vector( 0 to 162);
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f_sa3_ex3_c :in std_ulogic_vector(53 to 161);
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f_alg_ex2_effsub_eac_b :in std_ulogic;
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f_lze_ex2_lzo_din :in std_ulogic_vector(0 to 162);
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f_lze_ex3_sh_rgt_amt :in std_ulogic_vector(0 to 7);
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f_lze_ex3_sh_rgt_en :in std_ulogic ;
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f_lza_ex4_no_lza_edge :out std_ulogic;
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f_lza_ex4_lza_amt :out std_ulogic_vector(0 to 7);
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f_lza_ex4_lza_dcd64_cp1 :out std_ulogic_vector(0 to 2);
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f_lza_ex4_lza_dcd64_cp2 :out std_ulogic_vector(0 to 1);
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f_lza_ex4_lza_dcd64_cp3 :out std_ulogic_vector(0 to 0);
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f_lza_ex4_sh_rgt_en :out std_ulogic;
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f_lza_ex4_sh_rgt_en_eov :out std_ulogic;
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f_lza_ex4_lza_amt_eov :out std_ulogic_vector(0 to 7)
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);
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end fuq_lza;
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architecture fuq_lza of fuq_lza is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal thold_0_b, thold_0, forcee :std_ulogic;
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signal sg_0 :std_ulogic;
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signal ex2_act :std_ulogic;
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signal ex3_act :std_ulogic;
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signal ex1_act :std_ulogic;
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signal act_spare_unused :std_ulogic_vector(0 to 3);
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signal act_so :std_ulogic_vector(0 to 5);
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signal act_si :std_ulogic_vector(0 to 5);
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signal ex3_lzo_so :std_ulogic_vector(0 to 162);
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signal ex3_lzo_si :std_ulogic_vector(0 to 162);
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signal ex3_sub_so :std_ulogic_vector(0 to 0);
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signal ex3_sub_si :std_ulogic_vector(0 to 0);
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signal ex4_amt_so :std_ulogic_vector(0 to 15);
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signal ex4_amt_si :std_ulogic_vector(0 to 15);
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signal ex4_dcd_so :std_ulogic_vector(0 to 8);
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signal ex4_dcd_si :std_ulogic_vector(0 to 8);
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signal ex3_lza_any_b :std_ulogic;
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signal ex3_effsub :std_ulogic;
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signal ex4_no_edge :std_ulogic;
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signal ex3_no_edge_b :std_ulogic;
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signal ex3_lzo :std_ulogic_vector(0 to 162);
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signal ex3_lza_amt_b :std_ulogic_vector(0 to 7);
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signal ex4_amt_eov :std_ulogic_vector(0 to 7);
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signal ex4_amt :std_ulogic_vector(0 to 7);
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signal ex3_sum :std_ulogic_vector(0 to 162);
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signal ex3_car :std_ulogic_vector(53 to 162);
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signal ex3_lv0_or :std_ulogic_vector(0 to 162);
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signal ex3_sh_rgt_en_b :std_ulogic;
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signal ex3_lv6_or_0_b , ex3_lv6_or_1_b , ex3_lv6_or_0_t , ex3_lv6_or_1_t :std_ulogic;
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signal ex3_lza_dcd64_0_b , ex3_lza_dcd64_1_b , ex3_lza_dcd64_2_b :std_ulogic;
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signal ex4_lza_dcd64_cp1 :std_ulogic_vector(0 to 2);
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signal ex4_lza_dcd64_cp2 :std_ulogic_vector(0 to 1);
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signal ex4_lza_dcd64_cp3 :std_ulogic_vector(0 to 0);
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signal ex4_sh_rgt_en :std_ulogic;
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signal ex4_sh_rgt_en_eov :std_ulogic;
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signal ex2_effsub_eac, ex2_effsub_eac_b :std_ulogic;
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signal ex3_lzo_b, ex3_lzo_l2_b :std_ulogic_vector(0 to 162);
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signal ex3_lv6_or_0, ex3_lv6_or_1 :std_ulogic;
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signal ex3_rgt_amt_b :std_ulogic_vector(0 to 7);
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signal lza_ex4_d1clk , lza_ex4_d2clk :std_ulogic ;
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signal lza_ex3_d1clk , lza_ex3_d2clk :std_ulogic ;
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signal lza_ex4_lclk :clk_logic ;
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signal lza_ex3_lclk :clk_logic ;
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begin
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thold_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => thold_1,
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q(0) => thold_0 );
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sg_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => sg_1 ,
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q(0) => sg_0 );
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lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
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clkoff_b => clkoff_b,
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thold => thold_0,
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sg => sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => thold_0_b );
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ex1_act <= not ex1_act_b;
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act_lat: tri_rlmreg_p generic map (width=> 6, expand_type => expand_type, needs_sreset => 0) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(3) ,
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mpw1_b => mpw1_b(3) ,
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mpw2_b => mpw2_b(0) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => fpu_enable,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => act_so ,
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scin => act_si ,
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din(0) => act_spare_unused(0),
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din(1) => act_spare_unused(1),
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din(2) => ex1_act,
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din(3) => ex2_act,
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din(4) => act_spare_unused(2),
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din(5) => act_spare_unused(3),
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dout(0) => act_spare_unused(0),
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dout(1) => act_spare_unused(1),
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dout(2) => ex2_act,
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dout(3) => ex3_act,
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dout(4) => act_spare_unused(2) ,
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dout(5) => act_spare_unused(3) );
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lza_ex3_lcb : tri_lcbnd generic map (expand_type => expand_type) port map(
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delay_lclkr => delay_lclkr(3) ,
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mpw1_b => mpw1_b(3) ,
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mpw2_b => mpw2_b(0) ,
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forcee => forcee,
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nclk => nclk ,
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vd => vdd ,
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gd => gnd ,
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act => ex2_act ,
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sg => sg_0 ,
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thold_b => thold_0_b ,
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d1clk => lza_ex3_d1clk ,
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d2clk => lza_ex3_d2clk ,
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lclk => lza_ex3_lclk );
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lza_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map(
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delay_lclkr => delay_lclkr(4) ,
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mpw1_b => mpw1_b(4) ,
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mpw2_b => mpw2_b(0) ,
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forcee => forcee,
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nclk => nclk ,
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vd => vdd ,
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gd => gnd ,
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act => ex3_act ,
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sg => sg_0 ,
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thold_b => thold_0_b ,
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d1clk => lza_ex4_d1clk ,
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d2clk => lza_ex4_d2clk ,
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lclk => lza_ex4_lclk );
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ex3_lzo_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 163, btr => "NLI0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map (
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vd => vdd ,
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gd => gnd ,
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LCLK => lza_ex3_lclk ,
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D1CLK => lza_ex3_d1clk ,
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D2CLK => lza_ex3_d2clk ,
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SCANIN => ex3_lzo_si ,
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SCANOUT => ex3_lzo_so ,
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D => f_lze_ex2_lzo_din(0 to 162),
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QB => ex3_lzo_l2_b(0 to 162) );
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zobx: ex3_lzo (0 to 162) <= not ex3_lzo_l2_b(0 to 162);
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zob: ex3_lzo_b(0 to 162) <= not ex3_lzo (0 to 162);
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ex2_effsub_eac <= not f_alg_ex2_effsub_eac_b ;
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ex2_effsub_eac_b <= not ex2_effsub_eac ;
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ex3_sub_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 1, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map (
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vd => vdd ,
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gd => gnd ,
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LCLK => lza_ex3_lclk ,
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D1CLK => lza_ex3_d1clk ,
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D2CLK => lza_ex3_d2clk ,
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SCANIN(0) => ex3_sub_si(0) ,
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SCANOUT(0) => ex3_sub_so(0) ,
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D(0) => ex2_effsub_eac_b ,
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QB(0) => ex3_effsub );
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ex3_sum(0 to 52) <= f_sa3_ex3_s(0 to 52) ;
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ex3_sum(53 to 162) <= f_sa3_ex3_s(53 to 162);
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ex3_car(53 to 162) <= f_sa3_ex3_c(53 to 161) & tidn;
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lzaej: entity work.fuq_lza_ej(fuq_lza_ej) port map(
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effsub => ex3_effsub ,
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sum(0 to 162) => ex3_sum(0 to 162) ,
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car(53 to 162) => ex3_car(53 to 162) ,
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lzo_b(0 to 162) => ex3_lzo_b(0 to 162) ,
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edge(0 to 162) => ex3_lv0_or(0 to 162) );
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lzaclz: entity work.fuq_lza_clz(fuq_lza_clz) port map(
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lv0_or(0 to 162) => ex3_lv0_or(0 to 162) ,
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lv6_or_0 => ex3_lv6_or_0 ,
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lv6_or_1 => ex3_lv6_or_1 ,
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lza_any_b => ex3_lza_any_b ,
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lza_amt_b(0 to 7) => ex3_lza_amt_b(0 to 7) );
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ex3_no_edge_b <= not ex3_lza_any_b ;
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ex3_rgt_amt_b(0 to 7) <= not f_lze_ex3_sh_rgt_amt(0 to 7);
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ex3_sh_rgt_en_b <= not f_lze_ex3_sh_rgt_en ;
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lzdz0b: ex3_lv6_or_0_b <= not ex3_lv6_or_0 ;
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lzdz1b: ex3_lv6_or_1_b <= not ex3_lv6_or_1 ;
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lzdz0t: ex3_lv6_or_0_t <= not ex3_lv6_or_0_b ;
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lzdz1t: ex3_lv6_or_1_t <= not ex3_lv6_or_1_b ;
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lzd0b: ex3_lza_dcd64_0_b <= not(ex3_lv6_or_0_t and ex3_sh_rgt_en_b);
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lzd1b: ex3_lza_dcd64_1_b <= not(ex3_lv6_or_0_b and ex3_lv6_or_1_t and ex3_sh_rgt_en_b);
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lzd2b: ex3_lza_dcd64_2_b <= not(ex3_lv6_or_0_b and ex3_lv6_or_1_b and ex3_sh_rgt_en_b);
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ex4_dcd_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 9, btr => "NLI0001_X2_A12TH" , expand_type => expand_type, needs_sreset => 0 ) port map (
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vd => vdd ,
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gd => gnd ,
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LCLK => lza_ex4_lclk ,
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D1CLK => lza_ex4_d1clk ,
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D2CLK => lza_ex4_d2clk ,
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SCANIN => ex4_dcd_si(0 to 8) ,
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SCANOUT => ex4_dcd_so(0 to 8) ,
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D( 0) => ex3_lza_dcd64_0_b ,
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D( 1) => ex3_lza_dcd64_0_b ,
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D( 2) => ex3_lza_dcd64_0_b ,
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D( 3) => ex3_lza_dcd64_1_b ,
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D( 4) => ex3_lza_dcd64_1_b ,
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D( 5) => ex3_lza_dcd64_2_b ,
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D( 6) => ex3_sh_rgt_en_b ,
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D( 7) => ex3_sh_rgt_en_b ,
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D( 8) => ex3_no_edge_b ,
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QB( 0) => ex4_lza_dcd64_cp1(0),
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QB( 1) => ex4_lza_dcd64_cp2(0),
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QB( 2) => ex4_lza_dcd64_cp3(0),
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QB( 3) => ex4_lza_dcd64_cp1(1),
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QB( 4) => ex4_lza_dcd64_cp2(1),
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QB( 5) => ex4_lza_dcd64_cp1(2),
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QB( 6) => ex4_sh_rgt_en ,
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QB( 7) => ex4_sh_rgt_en_eov ,
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QB( 8) => ex4_no_edge );
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ex4_amt_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 16, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map (
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vd => vdd ,
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gd => gnd ,
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LCLK => lza_ex4_lclk ,
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D1CLK => lza_ex4_d1clk ,
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D2CLK => lza_ex4_d2clk ,
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SCANIN => ex4_amt_si(0 to 15) ,
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SCANOUT => ex4_amt_so(0 to 15) ,
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A1( 0) => ex3_lza_amt_b(0) ,
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A1( 1) => ex3_lza_amt_b(0) ,
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A1( 2) => ex3_lza_amt_b(1) ,
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A1( 3) => ex3_lza_amt_b(1) ,
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A1( 4) => ex3_lza_amt_b(2) ,
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A1( 5) => ex3_lza_amt_b(2) ,
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A1( 6) => ex3_lza_amt_b(3) ,
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A1( 7) => ex3_lza_amt_b(3) ,
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A1( 8) => ex3_lza_amt_b(4) ,
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A1( 9) => ex3_lza_amt_b(4) ,
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A1(10) => ex3_lza_amt_b(5) ,
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A1(11) => ex3_lza_amt_b(5) ,
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A1(12) => ex3_lza_amt_b(6) ,
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A1(13) => ex3_lza_amt_b(6) ,
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A1(14) => ex3_lza_amt_b(7) ,
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A1(15) => ex3_lza_amt_b(7) ,
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A2( 0) => ex3_rgt_amt_b(0) ,
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A2( 1) => ex3_rgt_amt_b(0) ,
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A2( 2) => ex3_rgt_amt_b(1) ,
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A2( 3) => ex3_rgt_amt_b(1) ,
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A2( 4) => ex3_rgt_amt_b(2) ,
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A2( 5) => ex3_rgt_amt_b(2) ,
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A2( 6) => ex3_rgt_amt_b(3) ,
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A2( 7) => ex3_rgt_amt_b(3) ,
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A2( 8) => ex3_rgt_amt_b(4) ,
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A2( 9) => ex3_rgt_amt_b(4) ,
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A2(10) => ex3_rgt_amt_b(5) ,
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A2(11) => ex3_rgt_amt_b(5) ,
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A2(12) => ex3_rgt_amt_b(6) ,
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A2(13) => ex3_rgt_amt_b(6) ,
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A2(14) => ex3_rgt_amt_b(7) ,
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A2(15) => ex3_rgt_amt_b(7) ,
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QB( 0) => ex4_amt(0) ,
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QB( 1) => ex4_amt_eov(0) ,
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QB( 2) => ex4_amt(1) ,
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QB( 3) => ex4_amt_eov(1) ,
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QB( 4) => ex4_amt(2) ,
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QB( 5) => ex4_amt_eov(2) ,
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QB( 6) => ex4_amt(3) ,
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QB( 7) => ex4_amt_eov(3) ,
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QB( 8) => ex4_amt(4) ,
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QB( 9) => ex4_amt_eov(4) ,
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QB(10) => ex4_amt(5) ,
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QB(11) => ex4_amt_eov(5) ,
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QB(12) => ex4_amt(6) ,
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QB(13) => ex4_amt_eov(6) ,
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QB(14) => ex4_amt(7) ,
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QB(15) => ex4_amt_eov(7) );
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f_lza_ex4_sh_rgt_en <= ex4_sh_rgt_en ;
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f_lza_ex4_sh_rgt_en_eov <= ex4_sh_rgt_en_eov ;
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f_lza_ex4_lza_amt <= ex4_amt(0 to 7) ;
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f_lza_ex4_lza_dcd64_cp1(0 to 2) <= ex4_lza_dcd64_cp1(0 to 2);
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f_lza_ex4_lza_dcd64_cp2(0 to 1) <= ex4_lza_dcd64_cp2(0 to 1);
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f_lza_ex4_lza_dcd64_cp3(0) <= ex4_lza_dcd64_cp3(0) ;
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f_lza_ex4_lza_amt_eov <= ex4_amt_eov(0 to 7) ;
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f_lza_ex4_no_lza_edge <= ex4_no_edge ;
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ex3_lzo_si (0 to 162) <= ex3_lzo_so (1 to 162) & f_lza_si ;
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ex3_sub_si (0) <= ex3_lzo_so (0);
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ex4_amt_si (0 to 15) <= ex4_amt_so (1 to 15) & ex3_sub_so (0);
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ex4_dcd_si (0 to 8) <= ex4_dcd_so (1 to 8) & ex4_amt_so (0);
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act_si (0 to 5) <= act_so (1 to 5) & ex4_dcd_so (0);
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f_lza_so <= act_so (0);
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end;
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