add source

rel/build/a2x/a2x_impl_step.tcl

@@ -0,0 +1,20 @@
+#synth_design -top a2x_axi_bd_wrapper -part xcvu3p-ffvc1517-2-e -verbose
+#source ila_axi.tcl
+set version v0
+
+write_checkpoint -force a2x_axi_synth_${version}.dcp
+
+opt_design -retarget -propconst -bram_power_opt 
+place_design -directive Explore
+phys_opt_design -directive Explore
+route_design -directive Explore
+phys_opt_design -directive Explore
+write_checkpoint -force a2x_axi_routed_${version}.dcp 
+
+report_utilization -file  utilization_route_design_${version}.rpt
+report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt
+
+write_bitstream -force -bin_file a2x_axi_${version}
+write_debug_probes -force a2x_axi_${version}
+write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2x_axi_${version}.bit" a2x_axi_${version}
+

rel/build/a2x/bd/hdl/a2x_axi_bd_wrapper.v

@@ -0,0 +1,24 @@
+//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2019.1.3_CR1055600 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+//Date        : Wed Apr  8 10:49:50 2020
+//Host        : apdegl15aa.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.5 (Maipo)
+//Command     : generate_target a2x_axi_bd_wrapper.bd
+//Design      : a2x_axi_bd_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module a2x_axi_bd_wrapper
+   (clk_in1_n_0,
+    clk_in1_p_0);
+  input clk_in1_n_0;
+  input clk_in1_p_0;
+
+  wire clk_in1_n_0;
+  wire clk_in1_p_0;
+
+  a2x_axi_bd a2x_axi_bd_i
+       (.clk_in1_n_0(clk_in1_n_0),
+        .clk_in1_p_0(clk_in1_p_0));
+endmodule

rel/build/a2x/fixup_a2x_bd.tcl

@@ -0,0 +1,50 @@
+open_bd_design "[get_property DIRECTORY [current_project]]/proj_a2x_axi.srcs/sources_1/bd/a2x_axi_bd/a2x_axi_bd.bd"
+
+set_property SCREENSIZE {1 1} [get_bd_cells /pain]
+set_property location {5 1506 2372} [get_bd_cells pain]
+set_property SCREENSIZE {1 1} [get_bd_cells /thold_0]
+set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_0]
+set_property location {6 2778 2069} [get_bd_cells xlconstant_0]
+set_property SCREENSIZE {1 1} [get_bd_cells /xlconstant_1]
+set_property location {6 2734 2210} [get_bd_cells xlconstant_1]
+
+# so xil actually connects as bus
+set_property SCREENSIZE {1 1} [get_bd_cells /mchk_rv]
+set_property location {6 2767 2847} [get_bd_cells mchk_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /rcov_rv]
+set_property location {6 2777 2748} [get_bd_cells rcov_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /checkstop_rv]
+set_property location {7 2850 2630} [get_bd_cells rcov_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /scomdata_rv]
+set_property location {4 1355 2564} [get_bd_cells scomdata_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /thread_running_rv]
+set_property location {5 2152 2682} [get_bd_cells thread_running_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /axi_reg00_rv]
+set_property location {7 3176 2490} [get_bd_cells axi_reg00_rv]
+set_property SCREENSIZE {1 1} [get_bd_cells /reverserator_4_0]
+set_property location {7 2156 2797} [get_bd_cells reverserator_4_0]
+
+
+
+set_property SCREENSIZE {600 600} [get_bd_cells /a2x_axi_1]
+set_property location {5 2000 1000} [get_bd_cells /a2x_axi_1]
+set_property location {4 1306 1980} [get_bd_cells a2x_dbug]
+
+set_property location {4.5 1482 792} [get_bd_cells jtag_axi_0]
+
+set_property location {4 1259 2326} [get_bd_cells vio_dbug] ;# no orientation, highlight, etc.
+set_property location {5 1957 2377} [get_bd_cells vio_ctrl]
+set_property location {6 2704 2401} [get_bd_cells vio_terror]
+set_property location {7 3253 2629} [get_bd_cells vio_reg]
+
+set_property location {10.5 4307 861} [get_bd_cells blk_mem_gen_1]
+set_property location {11 4297 974} [get_bd_cells blk_mem_gen_2]
+
+set_property location {6 2034 684} [get_bd_cells axi_smc]
+
+set_property location {7 3129 422} [get_bd_cells ila_axi]
+set_property location {9 3542 548} [get_bd_cells ila_axi_protocol]
+set_property location {7 3173 580} [get_bd_cells axi_protocol_checker]
+
+save_bd_design
+

rel/build/a2x/readme.md

@@ -0,0 +1,31 @@
+# create/build project
+
+```
+$VIVADO -mode tcl -source create_a2x_project.tcl
+
+$VIVADO proj/proj_a2x_axi.xpr
+
+source ./fixup_a2x_bd.tcl
+
+>run synthesis (synth_2)
+>open synthesized design
+
+source ./ila_axi.tcl
+>set up debug 
+>   all clk
+>   8192/3 
+
+source ./a2x_impl_step.tcl
+```
+
+```
+a2x_axi_routed_v0.dcp
+a2x_axi_synth_v0.dcp
+a2x_axi_v0.bin
+a2x_axi_v0.bit
+a2x_axi_v0.ltx
+a2x_axi_v0_primary.bin
+a2x_axi_v0_primary.prm
+a2x_axi_v0_secondary.bin
+a2x_axi_v0_secondary.prm
+```

rel/build/a2x/xdc

@@ -0,0 +1 @@
+../xdc

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux16.vhdl

@@ -0,0 +1,154 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support; use support.power_logic_pkg.all;
+
+entity c_debug_mux16 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group4         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group5         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group6         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group7         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group8         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group9         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group10        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group11        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group12        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group13        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group14        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group15        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux16;
+
+
+architecture c_debug_mux16 of c_debug_mux16 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+signal unused                   : std_ulogic;
+
+begin
+
+    unused <= select_bits(4);
+
+    with select_bits(0 to 3) select debug_grp_selected <= 
+      dbg_group0    when "0000",
+      dbg_group1    when "0001",
+      dbg_group2    when "0010",
+      dbg_group3    when "0011",
+      dbg_group4    when "0100",
+      dbg_group5    when "0101",
+      dbg_group6    when "0110",
+      dbg_group7    when "0111",
+      dbg_group8    when "1000",
+      dbg_group9    when "1001",
+      dbg_group10   when "1010",
+      dbg_group11   when "1011",
+      dbg_group12   when "1100",
+      dbg_group13   when "1101",
+      dbg_group14   when "1110",
+      dbg_group15   when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux16;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux32.vhdl

@@ -0,0 +1,184 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support;
+use support.power_logic_pkg.all;
+
+entity c_debug_mux32 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group4         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group5         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group6         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group7         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group8         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group9         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group10        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group11        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group12        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group13        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group14        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group15        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group16        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group17        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group18        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group19        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group20        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group21        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group22        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group23        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group24        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group25        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group26        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group27        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group28        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group29        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group30        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group31        : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux32;
+
+
+architecture c_debug_mux32 of c_debug_mux32 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+begin
+
+
+    with select_bits(0 to 4) select debug_grp_selected <= 
+      dbg_group0    when "00000",
+      dbg_group1    when "00001",
+      dbg_group2    when "00010",
+      dbg_group3    when "00011",
+      dbg_group4    when "00100",
+      dbg_group5    when "00101",
+      dbg_group6    when "00110",
+      dbg_group7    when "00111",
+      dbg_group8    when "01000",
+      dbg_group9    when "01001",
+      dbg_group10   when "01010",
+      dbg_group11   when "01011",
+      dbg_group12   when "01100",
+      dbg_group13   when "01101",
+      dbg_group14   when "01110",
+      dbg_group15   when "01111",
+      dbg_group16   when "10000",
+      dbg_group17   when "10001",
+      dbg_group18   when "10010",
+      dbg_group19   when "10011",
+      dbg_group20   when "10100",
+      dbg_group21   when "10101",
+      dbg_group22   when "10110",
+      dbg_group23   when "10111",
+      dbg_group24   when "11000",
+      dbg_group25   when "11001",
+      dbg_group26   when "11010",
+      dbg_group27   when "11011",
+      dbg_group28   when "11100",
+      dbg_group29   when "11101",
+      dbg_group30   when "11110",
+      dbg_group31   when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux32;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux4.vhdl

@@ -0,0 +1,131 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support;
+use support.power_logic_pkg.all;
+
+entity c_debug_mux4 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux4;
+
+
+architecture c_debug_mux4 of c_debug_mux4 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+signal unused                   : std_ulogic;
+
+begin
+
+    unused <= select_bits(2) or select_bits(3) or select_bits(4);
+
+    with select_bits(0 to 1) select debug_grp_selected <= 
+      dbg_group0    when "00",
+      dbg_group1    when "01",
+      dbg_group2    when "10",
+      dbg_group3    when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux4;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_debug_mux8.vhdl

@@ -0,0 +1,139 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all;
+library support;
+use support.power_logic_pkg.all;
+
+entity c_debug_mux8 is
+generic( DBG_WIDTH      : integer := 88         
+);         
+port(
+     vd                 : inout power_logic;
+     gd                 : inout power_logic;
+
+     select_bits        : in std_ulogic_vector(0 to 15);
+     trace_data_in      : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_in    : in std_ulogic_vector(0 to 11);
+
+     dbg_group0         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group1         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group2         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group3         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group4         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group5         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group6         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+     dbg_group7         : in std_ulogic_vector(0 to DBG_WIDTH-1);
+
+     trg_group0         : in std_ulogic_vector(0 to 11);
+     trg_group1         : in std_ulogic_vector(0 to 11);
+     trg_group2         : in std_ulogic_vector(0 to 11);
+     trg_group3         : in std_ulogic_vector(0 to 11);
+
+     trace_data_out     : out std_ulogic_vector(0 to DBG_WIDTH-1);
+     trigger_data_out   : out std_ulogic_vector(0 to 11)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_debug_mux8;
+
+
+architecture c_debug_mux8 of c_debug_mux8 is
+
+constant DBG_1FOURTH            : positive := DBG_WIDTH/4;
+constant DBG_2FOURTH            : positive := DBG_WIDTH/2;
+constant DBG_3FOURTH            : positive := 3*DBG_WIDTH/4;
+
+signal debug_grp_selected       : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal debug_grp_rotated        : std_ulogic_vector(0 to DBG_WIDTH-1);
+signal trigg_grp_selected       : std_ulogic_vector(0 to 11);
+signal trigg_grp_rotated        : std_ulogic_vector(0 to 11);
+
+signal unused                   : std_ulogic;
+
+begin
+
+    unused <= select_bits(3) or select_bits(4);
+
+    with select_bits(0 to 2) select debug_grp_selected <= 
+      dbg_group0    when "000",
+      dbg_group1    when "001",
+      dbg_group2    when "010",
+      dbg_group3    when "011",
+      dbg_group4    when "100",
+      dbg_group5    when "101",
+      dbg_group6    when "110",
+      dbg_group7    when others;
+
+   with select_bits(5 to 6) select 
+       debug_grp_rotated  <=  debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
+                              debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
+                              debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
+                              debug_grp_selected(0 to DBG_WIDTH-1)                                                    when others;
+
+
+   with select_bits(7)  select trace_data_out(0 to DBG_1FOURTH-1) <= 
+      trace_data_in(0 to DBG_1FOURTH-1)                 when '0',
+      debug_grp_rotated(0 to DBG_1FOURTH-1)             when others;
+
+   with select_bits(8)  select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <= 
+      trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1)   when others;
+
+   with select_bits(9)  select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <= 
+      trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1)       when '0',
+      debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1)   when others;
+
+   with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <= 
+      trace_data_in(DBG_3FOURTH to DBG_WIDTH-1)         when '0',
+      debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1)     when others;
+
+
+
+   with select_bits(11 to 12) select trigg_grp_selected <= 
+      trg_group0    when "00",
+      trg_group1    when "01",
+      trg_group2    when "10",
+      trg_group3    when others;
+
+   with select_bits(13) select 
+       trigg_grp_rotated  <=  trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
+                              trigg_grp_selected(0 to 11)                              when others;
+
+   with select_bits(14) select trigger_data_out(0 to 5) <=
+      trigger_data_in(0 to 5)       when '0',
+      trigg_grp_rotated(0 to 5)     when others;
+
+   with select_bits(15) select trigger_data_out(6 to 11) <=
+      trigger_data_in(6 to 11)      when '0',
+      trigg_grp_rotated(6 to 11)    when others;
+
+
+end c_debug_mux8;

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_event_mux.vhdl

@@ -0,0 +1,146 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,support,ibm;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+
+entity c_event_mux is
+  generic( events_in      : integer := 32;  
+           events_out     : integer := 8 ); 
+  port(
+     vd             : inout power_logic;
+     gd             : inout power_logic;
+     t0_events      : in  std_ulogic_vector(0 to events_in/4-1);
+     t1_events      : in  std_ulogic_vector(0 to events_in/4-1);
+     t2_events      : in  std_ulogic_vector(0 to events_in/4-1);
+     t3_events      : in  std_ulogic_vector(0 to events_in/4-1);
+
+     select_bits    : in  std_ulogic_vector(0 to ((events_in/64+4)*events_out)-1);
+
+     event_bits     : out std_ulogic_vector(0 to events_out-1)
+);
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+end c_event_mux;
+
+
+architecture c_event_mux of c_event_mux is
+
+  constant INCR                 : natural := events_in/64+4;    
+  constant SIZE                 : natural := events_in/64+1;    
+
+
+  signal inMuxDec               : std_ulogic_vector(0 to events_out*events_in/4-1);
+  signal inMuxOut               : std_ulogic_vector(0 to events_out*events_in/4-1);
+
+  signal thrd_sel               : std_ulogic_vector(0 to events_out-1);
+  signal inMux_sel              : std_ulogic_vector(0 to ((events_in/64+3)*events_out)-1);
+
+
+begin
+  thrd_sel    <= select_bits(0*INCR) & select_bits(1*INCR) &
+                 select_bits(2*INCR) & select_bits(3*INCR) &
+                 select_bits(4*INCR) & select_bits(5*INCR) &
+                 select_bits(6*INCR) & select_bits(7*INCR) ;
+
+  inMux_sel   <= select_bits(0*INCR+1 to (0+1)*INCR-1) &
+                 select_bits(1*INCR+1 to (1+1)*INCR-1) &
+                 select_bits(2*INCR+1 to (2+1)*INCR-1) &
+                 select_bits(3*INCR+1 to (3+1)*INCR-1) &
+                 select_bits(4*INCR+1 to (4+1)*INCR-1) &
+                 select_bits(5*INCR+1 to (5+1)*INCR-1) &
+                 select_bits(6*INCR+1 to (6+1)*INCR-1) &
+                 select_bits(7*INCR+1 to (7+1)*INCR-1) ;
+
+
+  decode: for X in 0 to events_out-1 generate
+    Mux32: if (events_in = 32) generate
+        inMuxDec(X*events_in/4 to X*events_in/4+7)  <= decode_3to8(inMux_sel(X*3 to X*3+2));
+    end generate Mux32;
+
+    Mux64: if (events_in = 64) generate
+        inMuxDec(X*events_in/4 to X*events_in/4+15) <= decode_4to16(inMux_sel(X*4 to X*4+3));
+    end generate Mux64;
+
+    Mux128: if (events_in = 128) generate
+        inMuxDec(X*events_in/4 to X*events_in/4+31) <= decode_5to32(inMux_sel(X*5 to X*5+4));
+    end generate Mux128;
+  end generate decode;
+
+
+  inpMuxHi: for X in 0 to events_out/2-1 generate
+      eventSel: for I in 0 to events_in/4-1 generate
+          inMuxOut(X*events_in/4 + I) <=
+              ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t0_events(I)) or  
+               (inMuxDec(X*events_in/4 + I) and     thrd_sel(X) and t1_events(I)) );  
+      end generate eventSel;
+  end generate inpMuxHi;
+
+  inpMuxLo: for X in events_out/2 to events_out-1 generate
+      eventSel: for I in 0 to events_in/4-1 generate
+          inMuxOut(X*events_in/4 + I) <=
+              ((inMuxDec(X*events_in/4 + I) and not thrd_sel(X) and t2_events(I)) or  
+               (inMuxDec(X*events_in/4 + I) and     thrd_sel(X) and t3_events(I)) ); 
+      end generate eventSel;
+  end generate inpMuxLo;
+
+
+  bitOutHi: for X in 0 to events_out/2-1 generate
+    Mux32: if (events_in = 32) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
+    end generate Mux32;
+
+    Mux64: if (events_in = 64) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
+    end generate Mux64;
+
+    Mux128: if (events_in = 128) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
+    end generate Mux128;
+  end generate bitOutHi;
+
+  bitOutLo: for X in events_out/2 to events_out-1 generate
+    Mux32: if (events_in = 32) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 7));
+    end generate Mux32;
+
+    Mux64: if (events_in = 64) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 15));
+    end generate Mux64;
+
+    Mux128: if (events_in = 128) generate
+        event_bits(X) <= or_reduce(inMuxOut(X*events_in/4 to X*events_in/4 + 31));
+    end generate Mux128;
+  end generate bitOutLo;
+
+end c_event_mux;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_bthmx.vhdl

@@ -0,0 +1,97 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; use support.power_logic_pkg.all;
+
+ENTITY c_prism_bthmx IS
+    GENERIC ( btr : string := "BTHMX_X1_A12TH"  );
+    PORT(
+     X      : IN  STD_ULOGIC;
+     SNEG   : IN  STD_ULOGIC; 
+     SX     : IN  STD_ULOGIC; 
+     SX2    : IN  STD_ULOGIC; 
+     RIGHT  : IN  STD_ULOGIC; 
+     LEFT   : OUT STD_ULOGIC; 
+     Q      : OUT STD_ULOGIC; 
+     vd     : inout power_logic;
+     gd     : inout power_logic
+  );
+
+-- synopsys translate_off
+
+
+    ATTRIBUTE PIN_BIT_INFORMATION of c_prism_bthmx : entity is
+      (
+        1 => ("   ","X       ","SAME","PIN_BIT_SCALAR"),
+        2 => ("   ","SNEG    ","SAME","PIN_BIT_SCALAR"),
+        3 => ("   ","SX      ","SAME","PIN_BIT_SCALAR"),
+        4 => ("   ","SX2     ","SAME","PIN_BIT_SCALAR"),
+        5 => ("   ","RIGHT   ","SAME","PIN_BIT_SCALAR"),
+        6 => ("   ","LEFT    ","SAME","PIN_BIT_SCALAR"),
+        7 => ("   ","Q       ","SAME","PIN_BIT_SCALAR"),
+        8 => ("   ","VDD     ","SAME","PIN_BIT_SCALAR"),
+        9 => ("   ","VSS     ","SAME","PIN_BIT_SCALAR")
+        );
+-- synopsys translate_on
+END                               c_prism_bthmx;
+
+ARCHITECTURE c_prism_bthmx OF c_prism_bthmx IS
+
+   SIGNAL CENTER :STD_ULOGIC;
+   SIGNAL XN     :STD_ULOGIC;
+   SIGNAL SPOS   :STD_ULOGIC;
+
+
+BEGIN
+
+   XN <= NOT X;
+
+   SPOS <= NOT SNEG;
+
+   CENTER <= NOT( ( XN AND SPOS ) OR 
+                  ( X  AND SNEG )   );
+
+   LEFT <= CENTER; 
+
+
+   Q <= ( CENTER AND  SX  ) OR 
+        ( RIGHT  AND  SX2 ) ;
+
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa32.vhdl

@@ -0,0 +1,82 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; use support.power_logic_pkg.all;
+
+ENTITY c_prism_csa32 IS
+   GENERIC ( btr : string := "CSA32_A2_A12TH" );
+   PORT(
+   A       : IN  std_ulogic;
+   B       : IN  std_ulogic;
+   C       : IN  std_ulogic;
+   CAR     : OUT std_ulogic;
+   SUM     : OUT std_ulogic;
+   vd      : inout power_logic;
+   gd      : inout power_logic
+  );
+
+-- synopsys translate_off
+
+
+   ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa32 : entity is
+     (
+       1 => ("   ","A       ","SAME","PIN_BIT_SCALAR"),
+       2 => ("   ","B       ","SAME","PIN_BIT_SCALAR"),
+       3 => ("   ","C       ","SAME","PIN_BIT_SCALAR"),
+       4 => ("   ","CAR     ","SAME","PIN_BIT_SCALAR"),
+       5 => ("   ","SUM     ","SAME","PIN_BIT_SCALAR"),
+       6 => ("   ","VDD     ","SAME","PIN_BIT_SCALAR"),
+       7 => ("   ","VSS     ","SAME","PIN_BIT_SCALAR")
+       );
+-- synopsys translate_on
+END                               c_prism_csa32;
+
+ARCHITECTURE c_prism_csa32 OF c_prism_csa32 IS
+
+
+BEGIN
+
+  sum <= a  XOR b  XOR c ;
+
+  car <= (a  AND b ) OR
+         (a  AND c ) OR
+         (b  AND c );
+
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_prism_csa42.vhdl

@@ -0,0 +1,96 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ; 
+library support;
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+  use support.power_logic_pkg.all;
+
+ENTITY c_prism_csa42 IS
+  GENERIC ( btr : string := "CSA42_A2_A12TH" );
+  PORT( 
+   A       : IN  std_ulogic;
+   B       : IN  std_ulogic;
+   C       : IN  std_ulogic;
+   D       : IN  std_ulogic;
+   KI      : IN  std_ulogic;
+   KO      : OUT std_ulogic;
+   CAR     : OUT std_ulogic;
+   SUM     : OUT std_ulogic;
+   vd      : inout power_logic;
+   gd      : inout power_logic
+  );
+
+-- synopsys translate_off
+
+
+   ATTRIBUTE PIN_BIT_INFORMATION of c_prism_csa42 : entity is
+     (
+       1  => ("   ","A       ","SAME","PIN_BIT_SCALAR"),
+       2  => ("   ","B       ","SAME","PIN_BIT_SCALAR"),
+       3  => ("   ","C       ","SAME","PIN_BIT_SCALAR"),
+       4  => ("   ","D       ","SAME","PIN_BIT_SCALAR"),
+       5  => ("   ","KI      ","SAME","PIN_BIT_SCALAR"),
+       6  => ("   ","KO      ","SAME","PIN_BIT_SCALAR"),
+       7  => ("   ","CAR     ","SAME","PIN_BIT_SCALAR"),
+       8  => ("   ","SUM     ","SAME","PIN_BIT_SCALAR"),
+       9  => ("   ","VDD     ","SAME","PIN_BIT_SCALAR"),
+       10 => ("   ","VSS     ","SAME","PIN_BIT_SCALAR")
+       );
+-- synopsys translate_on
+END                              c_prism_csa42;
+
+ARCHITECTURE c_prism_csa42 OF c_prism_csa42 IS
+
+ signal s1 : std_ulogic;
+
+BEGIN
+
+  s1    <= b  XOR c  XOR d ;
+  sum   <= s1 XOR a  XOR ki;
+
+  car   <= (s1 AND a ) OR
+           (s1 AND ki) OR
+           (a  AND ki);
+
+  ko   <= (b  AND c ) OR
+          (b  AND d ) OR
+          (c  AND d );
+
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/clib/c_scom_addr_decode.vhdl

@@ -0,0 +1,70 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+library ieee,ibm,latches,clib, support;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+
+entity c_scom_addr_decode is
+   generic( satid_nobits  : positive := 5        
+          ; use_addr           : std_ulogic_vector := "1"
+          ; addr_is_rdable     : std_ulogic_vector := "1"
+          ; addr_is_wrable     : std_ulogic_vector := "1"
+          );
+   port( sc_addr     : in  std_ulogic_vector(0 to 11-satid_nobits-1) 
+       ; scaddr_dec  : out std_ulogic_vector(0 to use_addr'length-1) 
+       ; sc_req      : in  std_ulogic                                
+       ; sc_r_nw     : in  std_ulogic                                
+       ; scaddr_nvld : out std_ulogic                                
+       ; sc_wr_nvld  : out std_ulogic                                
+       ; sc_rd_nvld  : out std_ulogic                                
+       ; vd : inout power_logic
+       ; gd : inout power_logic
+       );
+
+end c_scom_addr_decode;
+
+
+
+architecture c_scom_addr_decode of c_scom_addr_decode is
+   signal address : std_ulogic_vector(0 to use_addr'length-1);
+begin
+   decode_it : for i in 0 to use_addr'length-1 generate
+      address(i) <= ((sc_addr = tconv(i,sc_addr'length)) and (use_addr(i)='1'));
+   end generate decode_it;
+
+   scaddr_dec  <= address;
+   scaddr_nvld <= sc_req and not or_reduce(address);
+   sc_wr_nvld  <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw;
+   sc_rd_nvld  <= not or_reduce(address and addr_is_rdable) and sc_req and     sc_r_nw;
+end c_scom_addr_decode;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/ibm/std_ulogic_unsigned.vhdl

@@ -0,0 +1,374 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+--***************************************************************************
+-- Copyright 2020 International Business Machines
+--
+-- Licensed under the Apache License, Version 2.0 (the “License”);
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- The patent license granted to you in Section 3 of the License, as applied
+-- to the “Work,” hereby includes implementations of the Work in physical form.
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an “AS IS” BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+--***************************************************************************
+library IEEE, IBM;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IBM.std_ulogic_support.all;
+
+package std_ulogic_unsigned is
+
+    function "+"(l: std_ulogic_vector; 	r: std_ulogic_vector) return std_ulogic_vector;
+    function "+"(l: std_ulogic_vector; 	r: integer)          return std_ulogic_vector;
+    function "+"(l: integer; 		r: std_ulogic_vector) return std_ulogic_vector;
+    function "+"(l: std_ulogic_vector;	r: std_ulogic)        return std_ulogic_vector;
+    function "+"(l: std_ulogic; 		r: std_ulogic_vector) return std_ulogic_vector;
+
+    function "-"(l: std_ulogic_vector; 	r: std_ulogic_vector) return std_ulogic_vector;
+    function "-"(l: std_ulogic_vector; 	r: integer)          return std_ulogic_vector;
+    function "-"(l: integer; 		r: std_ulogic_vector) return std_ulogic_vector;
+    function "-"(l: std_ulogic_vector; 	r: std_ulogic)        return std_ulogic_vector;
+    function "-"(l: std_ulogic; 		r: std_ulogic_vector) return std_ulogic_vector;
+
+    function "+"(l: std_ulogic_vector)                        return std_ulogic_vector;
+
+    function "*"(l: std_ulogic_vector; 	r: std_ulogic_vector) return std_ulogic_vector;
+
+  function "=" ( l : natural;          r : std_ulogic_vector) return boolean;
+  function "/="( l : natural;          r : std_ulogic_vector) return boolean;
+  function "<" ( l : natural;          r : std_ulogic_vector) return boolean;
+  function "<="( l : natural;          r : std_ulogic_vector) return boolean;
+  function ">" ( l : natural;          r : std_ulogic_vector) return boolean;
+  function ">="( l : natural;          r : std_ulogic_vector) return boolean;
+
+  function "=" ( l : std_ulogic_vector; r : natural)          return boolean;
+  function "/="( l : std_ulogic_vector; r : natural)          return boolean;
+  function "<" ( l : std_ulogic_vector; r : natural)          return boolean;
+  function "<="( l : std_ulogic_vector; r : natural)          return boolean;
+  function ">" ( l : std_ulogic_vector; r : natural)          return boolean;
+  function ">="( l : std_ulogic_vector; r : natural)          return boolean;
+  
+  function "=" ( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function "/="( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function "<" ( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function "<="( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function ">" ( l : natural;          r : std_ulogic_vector) return std_ulogic;
+  function ">="( l : natural;          r : std_ulogic_vector) return std_ulogic;
+
+  function "=" ( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function "/="( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function "<" ( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function "<="( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function ">" ( l : std_ulogic_vector; r : natural)          return std_ulogic;
+  function ">="( l : std_ulogic_vector; r : natural)          return std_ulogic;
+
+  function to_integer( d : std_ulogic_vector ) return natural;
+  -- synopsys translate_off
+  attribute type_convert        of to_integer : function is true;
+  attribute btr_name            of to_integer : function is "PASS";
+  attribute pin_bit_information of to_integer : function is
+           (1 => ("   ","A0      ","INCR","PIN_BIT_SCALAR"),
+            2 => ("   ","10      ","INCR","PIN_BIT_SCALAR"));
+  -- synopsys translate_on
+  
+  -- synopsys translate_off
+  function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector;
+  attribute type_convert        of to_std_ulogic_vector : function is true;
+  attribute btr_name            of to_std_ulogic_vector : function is "PASS";
+  attribute pin_bit_information of to_std_ulogic_vector : function is
+           (1 => ("   ","A0      ","INCR","PIN_BIT_SCALAR"),
+            2 => ("   ","10      ","INCR","PIN_BIT_SCALAR"));
+  -- synopsys translate_on
+  
+end std_ulogic_unsigned;
+
+package body std_ulogic_unsigned is
+
+    function maximum(L, R: INTEGER) return INTEGER is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        constant length : INTEGER := maximum(L'length, R'length);
+        variable result : UNSIGNED(length-1 downto 0);
+        -- pragma label_applies_to plus
+    begin
+        result  := UNSIGNED(L) + UNSIGNED(R);  -- pragma label plus
+        return   std_ulogic_vector(result);
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is
+       variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to plus
+    begin
+        result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus
+        return  result ;
+    end;
+
+    function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to plus
+    begin
+        result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus
+        return  result;
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to plus
+    begin
+        if R = '1' then
+           result := std_ulogic_vector( UNSIGNED(L) + 1 );
+        else
+           result := L;
+        end if; 
+        return result ;
+    end;
+
+    function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to plus
+    begin
+        if L = '1' then
+           result := std_ulogic_vector( UNSIGNED(R) + 1 );
+        else
+           result := R;
+        end if; 
+        return result ;
+    end;
+
+    function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to plus
+    begin
+        result := L;
+        return result ;
+    end;
+
+    function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_ULOGIC_VECTOR (length-1 downto 0);
+        -- pragma label_applies_to minus
+    begin
+        result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus
+        return  result ;
+    end;
+
+    function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to minus
+    begin
+        result  := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus
+        return  result ;
+    end;
+
+    function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to minus
+    begin
+        result  := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus
+        return   result ;
+    end;
+
+    function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (L'range);
+        -- pragma label_applies_to minus
+    begin
+        if R = '1' then
+           result  := std_ulogic_vector( UNSIGNED(L) - 1 );
+        else
+           result  := L;
+        end if;
+        return  result ;
+    end;
+
+    function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        variable result  : STD_ULOGIC_VECTOR (R'range);
+        -- pragma label_applies_to minus
+    begin
+        if L = '1' then
+           result  := std_ulogic_vector( 1 - UNSIGNED(R) );
+        else
+           result  := std_ulogic_vector( 0 - UNSIGNED(R) );
+        end if;
+        return  result ;
+    end;
+
+    function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0);
+        -- pragma label_applies_to mult
+    begin
+        result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult
+        return result ;
+    end;
+
+  function "=" ( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l = unsigned(r);
+  end "=";
+  
+  function "/="( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l /= unsigned(r);
+  end "/=";
+  
+  function "<" ( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l < unsigned(r);
+  end "<";
+  
+  function "<="( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l <= unsigned(r);
+  end "<=";
+  
+  function ">" ( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l > unsigned(r);
+  end ">";
+  
+  function ">="( l : natural;          r : std_ulogic_vector) return boolean is
+  begin
+    return l >= unsigned(r);
+  end ">=";
+  
+  function "=" ( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) = r;
+  end "=";
+  
+  function "/="( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) /= r;
+  end "/=";
+  
+  function "<" ( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) < r;
+  end "<";
+  
+  function "<="( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) <= r;
+  end "<=";
+  
+  function ">" ( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) > r;
+  end ">";
+  
+  function ">="( l : std_ulogic_vector; r : natural)          return boolean is
+  begin
+    return unsigned(l) >= r;
+  end ">=";
+  
+  function "=" ( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l = unsigned(r) );
+  end "=";
+  
+  function "/="( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l /= unsigned(r) );
+  end "/=";
+  
+  function "<" ( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l < unsigned(r) );
+  end "<";
+  
+  function "<="( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l <= unsigned(r) );
+  end "<=";
+  
+  function ">" ( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l > unsigned(r) );
+  end ">";
+  
+  function ">="( l : natural;          r : std_ulogic_vector) return std_ulogic is
+  begin
+    return tconv( l >= unsigned(r) );
+  end ">=";
+  
+  function "=" ( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) = r );
+  end "=";
+  
+  function "/="( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) /= r );
+  end "/=";
+  
+  function "<" ( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) < r );
+  end "<";
+  
+  function "<="( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) <= r );
+  end "<=";
+  
+  function ">" ( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) > r );
+  end ">";
+  
+  function ">="( l : std_ulogic_vector; r : natural)          return std_ulogic is
+  begin
+    return tconv( unsigned(l) >= r );
+  end ">=";
+  
+  function to_integer( d : std_ulogic_vector ) return natural is
+  begin
+    return tconv( d );
+  end to_integer;
+  
+  function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is
+  begin
+    return tconv( d, w );
+  end to_std_ulogic_vector;
+  
+end std_ulogic_unsigned;

rel/build/ip_user/a2x_axi/a2x_axi/src/support/power_logic_pkg.vhdl

@@ -0,0 +1,38 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package power_logic_pkg is
+
+  subtype power_logic is std_logic;
+  subtype power_logic_vector is std_logic_vector;
+  
+end package power_logic_pkg;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s18_s18.vhdl

@@ -0,0 +1,360 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm; 
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+entity RAMB16_S18_S18 is
+	generic (
+		INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_A : bit_vector := X"000000000";
+		INIT_B : bit_vector := X"000000000";
+		SIM_COLLISION_CHECK : string := "ALL";   
+		SRVAL_A : bit_vector := X"000000000";
+		SRVAL_B : bit_vector := X"000000000";
+		WRITE_MODE_A : string := "WRITE_FIRST";  
+		WRITE_MODE_B : string := "WRITE_FIRST"   
+	);
+	port (
+		DOA : out std_logic_vector(15 downto 0);
+		DOB : out std_logic_vector(15 downto 0);
+		DOPA : out std_logic_vector(1 downto 0);
+		DOPB : out std_logic_vector(1 downto 0);
+		ADDRA : in std_logic_vector(9 downto 0);
+		ADDRB : in std_logic_vector(9 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(15 downto 0);
+		DIB : in std_logic_vector(15 downto 0);
+		DIPA : in std_logic_vector(1 downto 0);
+		DIPB : in std_logic_vector(1 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+end RAMB16_S18_S18;
+
+architecture RAMB16_S18_S18 of RAMB16_S18_S18 is
+
+signal DINA, DINB     : std_logic_vector(17 downto 0);
+signal DOUTA, DOUTB   : std_logic_vector(17 downto 0);
+signal SSRA_t, SSRB_t : std_logic;
+signal WEA_t, WEB_t   : std_logic_vector(1 downto 0);
+
+begin
+
+DINA   <= DIPA & DIA;
+DOPA   <= DOUTA(17 downto 16);
+DOA    <= DOUTA(15 downto 0);
+
+DINB   <= DIPB & DIB;
+DOPB   <= DOUTB(17 downto 16);
+DOB    <= DOUTB(15 downto 0);
+
+SSRA_t <= SSRA;
+SSRB_t <= SSRB;
+WEA_t  <= WEA & WEA;
+WEB_t  <= WEB & WEB;
+
+
+
+
+   
+   BRAM_0 : BRAM_TDP_MACRO
+   generic map (
+      BRAM_SIZE => "18Kb", 
+      DEVICE => "7SERIES", 
+      DOA_REG => 0, 
+      DOB_REG => 0, 
+      INIT_A => INIT_A, 
+      INIT_B => INIT_B, 
+      INIT_FILE => "NONE",
+      READ_WIDTH_A => 18,   
+      READ_WIDTH_B => 18,   
+      SIM_COLLISION_CHECK => "NONE",
+      SRVAL_A => SRVAL_A,   
+      SRVAL_B => SRVAL_A,   
+      WRITE_MODE_A => WRITE_MODE_A, 
+      WRITE_MODE_B => WRITE_MODE_B, 
+      WRITE_WIDTH_A => 18, 
+      WRITE_WIDTH_B => 18, 
+      INIT_00 => INIT_00,
+      INIT_01 => INIT_01,
+      INIT_02 => INIT_02,
+      INIT_03 => INIT_03,
+      INIT_04 => INIT_04,
+      INIT_05 => INIT_05,
+      INIT_06 => INIT_06,
+      INIT_07 => INIT_07,
+      INIT_08 => INIT_08,
+      INIT_09 => INIT_09,
+      INIT_0A => INIT_0A,
+      INIT_0B => INIT_0B,
+      INIT_0C => INIT_0C,
+      INIT_0D => INIT_0D,
+      INIT_0E => INIT_0E,
+      INIT_0F => INIT_0F,
+      INIT_10 => INIT_10,
+      INIT_11 => INIT_11,
+      INIT_12 => INIT_12,
+      INIT_13 => INIT_13,
+      INIT_14 => INIT_14,
+      INIT_15 => INIT_15,
+      INIT_16 => INIT_16,
+      INIT_17 => INIT_17,
+      INIT_18 => INIT_18,
+      INIT_19 => INIT_19,
+      INIT_1A => INIT_1A,
+      INIT_1B => INIT_1B,
+      INIT_1C => INIT_1C,
+      INIT_1D => INIT_1D,
+      INIT_1E => INIT_1E,
+      INIT_1F => INIT_1F,
+      INIT_20 => INIT_20,
+      INIT_21 => INIT_21,
+      INIT_22 => INIT_22,
+      INIT_23 => INIT_23,
+      INIT_24 => INIT_24,
+      INIT_25 => INIT_25,
+      INIT_26 => INIT_26,
+      INIT_27 => INIT_27,
+      INIT_28 => INIT_28,
+      INIT_29 => INIT_29,
+      INIT_2A => INIT_2A,
+      INIT_2B => INIT_2B,
+      INIT_2C => INIT_2C,
+      INIT_2D => INIT_2D,
+      INIT_2E => INIT_2E,
+      INIT_2F => INIT_2F,
+      INIT_30 => INIT_30,
+      INIT_31 => INIT_31,
+      INIT_32 => INIT_32,
+      INIT_33 => INIT_33,
+      INIT_34 => INIT_34,
+      INIT_35 => INIT_35,
+      INIT_36 => INIT_36,
+      INIT_37 => INIT_37,
+      INIT_38 => INIT_38,
+      INIT_39 => INIT_39,
+      INIT_3A => INIT_3A,
+      INIT_3B => INIT_3B,
+      INIT_3C => INIT_3C,
+      INIT_3D => INIT_3D,
+      INIT_3E => INIT_3E,
+      INIT_3F => INIT_3F,
+      
+      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      
+      INITP_00 => INITP_00,
+      INITP_01 => INITP_01,
+      INITP_02 => INITP_02,
+      INITP_03 => INITP_03,
+      INITP_04 => INITP_04,
+      INITP_05 => INITP_05,
+      INITP_06 => INITP_06,
+      INITP_07 => INITP_07,
+      
+      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
+   )
+   port map (
+      DOA => DOUTA,     
+      DOB => DOUTB,     
+      ADDRA => ADDRA,   
+      ADDRB => ADDRB,   
+      CLKA => CLKA,     
+      CLKB => CLKB,     
+      DIA => DINA,      
+      DIB => DINB,      
+      ENA => ENA,       
+      ENB => ENB,       
+      REGCEA => '1',    
+      REGCEB => '1',    
+      RSTA => SSRA_t,   
+      RSTB => SSRB_t,   
+      WEA => WEA_t,     
+      WEB => WEB_t      
+   );
+   
+
+
+end RAMB16_S18_S18;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s36_s36.vhdl

@@ -0,0 +1,364 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm; 
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+entity RAMB16_S36_S36 is
+	generic (
+		INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_A : bit_vector := X"000000000";
+		INIT_B : bit_vector := X"000000000";
+		SIM_COLLISION_CHECK : string := "ALL";   
+		SRVAL_A : bit_vector := X"000000000";
+		SRVAL_B : bit_vector := X"000000000";
+		WRITE_MODE_A : string := "WRITE_FIRST";  
+		WRITE_MODE_B : string := "WRITE_FIRST"   
+	);
+	port (
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+end RAMB16_S36_S36;
+
+architecture RAMB16_S36_S36 of RAMB16_S36_S36 is
+
+signal ADDRA_10, ADDRB_10 : std_logic_vector(9 downto 0);
+signal DINA, DINB     : std_logic_vector(35 downto 0);
+signal DOUTA, DOUTB   : std_logic_vector(35 downto 0);
+signal SSRA_t, SSRB_t : std_logic;
+signal WEA_t, WEB_t   : std_logic_vector(3 downto 0);
+
+begin
+
+ADDRA_10 <= '0' & ADDRA;
+ADDRB_10 <= '0' & ADDRB;
+
+DINA   <= DIPA & DIA;
+DOPA   <= DOUTA(35 downto 32);
+DOA    <= DOUTA(31 downto 0);
+
+DINB   <= DIPB & DIB;
+DOPB   <= DOUTB(35 downto 32);
+DOB    <= DOUTB(31 downto 0);
+
+SSRA_t <= SSRA;
+SSRB_t <= SSRB;
+WEA_t  <= WEA & WEA & WEA & WEA;
+WEB_t  <= WEB & WEB & WEB & WEB;
+
+
+
+
+   
+   BRAM_0 : BRAM_TDP_MACRO
+   generic map (
+      BRAM_SIZE => "36Kb", 
+      DEVICE => "7SERIES", 
+      DOA_REG => 0, 
+      DOB_REG => 0, 
+      INIT_A => INIT_A, 
+      INIT_B => INIT_B, 
+      INIT_FILE => "NONE",
+      READ_WIDTH_A => 36,   
+      READ_WIDTH_B => 36,   
+      SIM_COLLISION_CHECK => "NONE",
+      SRVAL_A => SRVAL_A,   
+      SRVAL_B => SRVAL_A,   
+      WRITE_MODE_A => WRITE_MODE_A, 
+      WRITE_MODE_B => WRITE_MODE_B, 
+      WRITE_WIDTH_A => 36, 
+      WRITE_WIDTH_B => 36, 
+      INIT_00 => INIT_00,
+      INIT_01 => INIT_01,
+      INIT_02 => INIT_02,
+      INIT_03 => INIT_03,
+      INIT_04 => INIT_04,
+      INIT_05 => INIT_05,
+      INIT_06 => INIT_06,
+      INIT_07 => INIT_07,
+      INIT_08 => INIT_08,
+      INIT_09 => INIT_09,
+      INIT_0A => INIT_0A,
+      INIT_0B => INIT_0B,
+      INIT_0C => INIT_0C,
+      INIT_0D => INIT_0D,
+      INIT_0E => INIT_0E,
+      INIT_0F => INIT_0F,
+      INIT_10 => INIT_10,
+      INIT_11 => INIT_11,
+      INIT_12 => INIT_12,
+      INIT_13 => INIT_13,
+      INIT_14 => INIT_14,
+      INIT_15 => INIT_15,
+      INIT_16 => INIT_16,
+      INIT_17 => INIT_17,
+      INIT_18 => INIT_18,
+      INIT_19 => INIT_19,
+      INIT_1A => INIT_1A,
+      INIT_1B => INIT_1B,
+      INIT_1C => INIT_1C,
+      INIT_1D => INIT_1D,
+      INIT_1E => INIT_1E,
+      INIT_1F => INIT_1F,
+      INIT_20 => INIT_20,
+      INIT_21 => INIT_21,
+      INIT_22 => INIT_22,
+      INIT_23 => INIT_23,
+      INIT_24 => INIT_24,
+      INIT_25 => INIT_25,
+      INIT_26 => INIT_26,
+      INIT_27 => INIT_27,
+      INIT_28 => INIT_28,
+      INIT_29 => INIT_29,
+      INIT_2A => INIT_2A,
+      INIT_2B => INIT_2B,
+      INIT_2C => INIT_2C,
+      INIT_2D => INIT_2D,
+      INIT_2E => INIT_2E,
+      INIT_2F => INIT_2F,
+      INIT_30 => INIT_30,
+      INIT_31 => INIT_31,
+      INIT_32 => INIT_32,
+      INIT_33 => INIT_33,
+      INIT_34 => INIT_34,
+      INIT_35 => INIT_35,
+      INIT_36 => INIT_36,
+      INIT_37 => INIT_37,
+      INIT_38 => INIT_38,
+      INIT_39 => INIT_39,
+      INIT_3A => INIT_3A,
+      INIT_3B => INIT_3B,
+      INIT_3C => INIT_3C,
+      INIT_3D => INIT_3D,
+      INIT_3E => INIT_3E,
+      INIT_3F => INIT_3F,
+      
+      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      
+      INITP_00 => INITP_00,
+      INITP_01 => INITP_01,
+      INITP_02 => INITP_02,
+      INITP_03 => INITP_03,
+      INITP_04 => INITP_04,
+      INITP_05 => INITP_05,
+      INITP_06 => INITP_06,
+      INITP_07 => INITP_07,
+      
+      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
+   )
+   port map (
+      DOA => DOUTA,     
+      DOB => DOUTB,     
+      ADDRA => ADDRA_10,  
+      ADDRB => ADDRB_10,  
+      CLKA => CLKA,     
+      CLKB => CLKB,     
+      DIA => DINA,      
+      DIB => DINB,      
+      ENA => ENA,       
+      ENB => ENB,       
+      REGCEA => '1',    
+      REGCEB => '1',    
+      RSTA => SSRA_t,   
+      RSTB => SSRB_t,   
+      WEA => WEA_t,     
+      WEB => WEB_t      
+   );
+   
+
+
+end RAMB16_S36_S36;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/ramb16_s9_s9.vhdl

@@ -0,0 +1,360 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm; 
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+entity RAMB16_S9_S9 is
+	generic (
+		INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+		INIT_A : bit_vector := X"000000000";
+		INIT_B : bit_vector := X"000000000";
+		SIM_COLLISION_CHECK : string := "ALL";   
+		SRVAL_A : bit_vector := X"000000000";
+		SRVAL_B : bit_vector := X"000000000";
+		WRITE_MODE_A : string := "WRITE_FIRST";  
+		WRITE_MODE_B : string := "WRITE_FIRST"   
+	);
+	port (
+		DOA : out std_logic_vector(7 downto 0);
+		DOB : out std_logic_vector(7 downto 0);
+		DOPA : out std_logic_vector(0 downto 0);
+		DOPB : out std_logic_vector(0 downto 0);
+		ADDRA : in std_logic_vector(10 downto 0);
+		ADDRB : in std_logic_vector(10 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(7 downto 0);
+		DIB : in std_logic_vector(7 downto 0);
+		DIPA : in std_logic_vector(0 downto 0);
+		DIPB : in std_logic_vector(0 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+end RAMB16_S9_S9;
+
+architecture RAMB16_S9_S9 of RAMB16_S9_S9 is
+
+signal DINA, DINB     : std_logic_vector(8 downto 0);
+signal DOUTA, DOUTB   : std_logic_vector(8 downto 0);
+signal SSRA_t, SSRB_t : std_logic;
+signal WEA_t, WEB_t   : std_logic_vector(0 downto 0);
+
+begin
+
+DINA   <= DIPA & DIA;
+DOPA(0) <= DOUTA(8);
+DOA    <= DOUTA(7 downto 0);
+
+DINB   <= DIPB & DIB;
+DOPB(0) <= DOUTB(8);
+DOB    <= DOUTB(7 downto 0);
+
+SSRA_t <= SSRA;
+SSRB_t <= SSRB;
+WEA_t(0)  <= WEA;
+WEB_t(0)  <= WEB;
+
+
+
+
+   
+   BRAM_0 : BRAM_TDP_MACRO
+   generic map (
+      BRAM_SIZE => "18Kb", 
+      DEVICE => "7SERIES", 
+      DOA_REG => 0, 
+      DOB_REG => 0, 
+      INIT_A => INIT_A, 
+      INIT_B => INIT_B, 
+      INIT_FILE => "NONE",
+      READ_WIDTH_A => 9,   
+      READ_WIDTH_B => 9,   
+      SIM_COLLISION_CHECK => "NONE",
+      SRVAL_A => SRVAL_A,   
+      SRVAL_B => SRVAL_A,   
+      WRITE_MODE_A => WRITE_MODE_A, 
+      WRITE_MODE_B => WRITE_MODE_B, 
+      WRITE_WIDTH_A => 9, 
+      WRITE_WIDTH_B => 9, 
+      INIT_00 => INIT_00,
+      INIT_01 => INIT_01,
+      INIT_02 => INIT_02,
+      INIT_03 => INIT_03,
+      INIT_04 => INIT_04,
+      INIT_05 => INIT_05,
+      INIT_06 => INIT_06,
+      INIT_07 => INIT_07,
+      INIT_08 => INIT_08,
+      INIT_09 => INIT_09,
+      INIT_0A => INIT_0A,
+      INIT_0B => INIT_0B,
+      INIT_0C => INIT_0C,
+      INIT_0D => INIT_0D,
+      INIT_0E => INIT_0E,
+      INIT_0F => INIT_0F,
+      INIT_10 => INIT_10,
+      INIT_11 => INIT_11,
+      INIT_12 => INIT_12,
+      INIT_13 => INIT_13,
+      INIT_14 => INIT_14,
+      INIT_15 => INIT_15,
+      INIT_16 => INIT_16,
+      INIT_17 => INIT_17,
+      INIT_18 => INIT_18,
+      INIT_19 => INIT_19,
+      INIT_1A => INIT_1A,
+      INIT_1B => INIT_1B,
+      INIT_1C => INIT_1C,
+      INIT_1D => INIT_1D,
+      INIT_1E => INIT_1E,
+      INIT_1F => INIT_1F,
+      INIT_20 => INIT_20,
+      INIT_21 => INIT_21,
+      INIT_22 => INIT_22,
+      INIT_23 => INIT_23,
+      INIT_24 => INIT_24,
+      INIT_25 => INIT_25,
+      INIT_26 => INIT_26,
+      INIT_27 => INIT_27,
+      INIT_28 => INIT_28,
+      INIT_29 => INIT_29,
+      INIT_2A => INIT_2A,
+      INIT_2B => INIT_2B,
+      INIT_2C => INIT_2C,
+      INIT_2D => INIT_2D,
+      INIT_2E => INIT_2E,
+      INIT_2F => INIT_2F,
+      INIT_30 => INIT_30,
+      INIT_31 => INIT_31,
+      INIT_32 => INIT_32,
+      INIT_33 => INIT_33,
+      INIT_34 => INIT_34,
+      INIT_35 => INIT_35,
+      INIT_36 => INIT_36,
+      INIT_37 => INIT_37,
+      INIT_38 => INIT_38,
+      INIT_39 => INIT_39,
+      INIT_3A => INIT_3A,
+      INIT_3B => INIT_3B,
+      INIT_3C => INIT_3C,
+      INIT_3D => INIT_3D,
+      INIT_3E => INIT_3E,
+      INIT_3F => INIT_3F,
+      
+      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      
+      INITP_00 => INITP_00,
+      INITP_01 => INITP_01,
+      INITP_02 => INITP_02,
+      INITP_03 => INITP_03,
+      INITP_04 => INITP_04,
+      INITP_05 => INITP_05,
+      INITP_06 => INITP_06,
+      INITP_07 => INITP_07,
+      
+      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
+   )
+   port map (
+      DOA => DOUTA,     
+      DOB => DOUTB,     
+      ADDRA => ADDRA,   
+      ADDRB => ADDRB,   
+      CLKA => CLKA,     
+      CLKB => CLKB,     
+      DIA => DINA,      
+      DIB => DINB,      
+      ENA => ENA,       
+      ENB => ENB,       
+      REGCEA => '1',    
+      REGCEB => '1',    
+      RSTA => SSRA_t,   
+      RSTB => SSRB_t,   
+      WEA => WEA_t,     
+      WEB => WEB_t      
+   );
+   
+
+
+end RAMB16_S9_S9;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x168_1w_0.vhdl

@@ -0,0 +1,338 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; 
+             use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; 
+use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_128x168_1w_0 is
+  generic (addressable_ports : positive := 128; 
+           addressbus_width : positive := 7;    
+           port_bitwidth : positive := 168;     
+           ways : positive := 1;                
+           expand_type : integer := 1);         
+  port (
+    gnd                : inout power_logic;
+    vdd                : inout power_logic;
+    vcs                : inout power_logic;
+    
+    nclk              : in clk_logic;
+    act               : in std_ulogic;
+    ccflush_dc        : in std_ulogic;
+    scan_dis_dc_b     : in std_ulogic;
+    scan_diag_dc      : in std_ulogic;
+
+    abst_scan_in    : in std_ulogic;
+    repr_scan_in    : in std_ulogic;
+    time_scan_in    : in std_ulogic;
+    abst_scan_out   : out std_ulogic;
+    repr_scan_out   : out std_ulogic;
+    time_scan_out   : out std_ulogic;
+    
+    lcb_d_mode_dc              : in std_ulogic;
+    lcb_clkoff_dc_b            : in std_ulogic;
+    lcb_act_dis_dc             : in std_ulogic;
+    lcb_mpw1_dc_b              : in std_ulogic_vector(0 to 4);
+    lcb_mpw2_dc_b              : in std_ulogic;
+    lcb_delay_lclkr_dc         : in std_ulogic_vector(0 to 4);
+
+    lcb_sg_1              : in std_ulogic;
+    lcb_time_sg_0         : in std_ulogic;
+    lcb_repr_sg_0         : in std_ulogic;
+    
+    lcb_abst_sl_thold_0   : in std_ulogic;
+    lcb_repr_sl_thold_0   : in std_ulogic;
+    lcb_time_sl_thold_0   : in std_ulogic;
+    lcb_ary_nsl_thold_0   : in std_ulogic;
+    lcb_bolt_sl_thold_0   : in std_ulogic; 
+
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_en_1                  : in std_ulogic;
+    din_abist                   : in std_ulogic_vector(0 to 3);
+    abist_cmp_en                : in std_ulogic;
+    abist_raw_b_dc              : in std_ulogic;
+    data_cmp_abist              : in std_ulogic_vector(0 to 3);
+    addr_abist                  : in std_ulogic_vector(0 to 6);
+    r_wb_abist                  : in std_ulogic;
+
+    pc_bo_enable_2                 : in    std_ulogic; 
+    pc_bo_reset                    : in    std_ulogic; 
+    pc_bo_unload                   : in    std_ulogic;
+    pc_bo_repair                   : in    std_ulogic; 
+    pc_bo_shdata                   : in    std_ulogic; 
+    pc_bo_select                   : in    std_ulogic; 
+    bo_pc_failout                  : out   std_ulogic; 
+    bo_pc_diagloop                 : out   std_ulogic;
+    tri_lcb_mpw1_dc_b              : in    std_ulogic;
+    tri_lcb_mpw2_dc_b              : in    std_ulogic;
+    tri_lcb_delay_lclkr_dc         : in    std_ulogic;
+    tri_lcb_clkoff_dc_b            : in    std_ulogic;
+    tri_lcb_act_dis_dc             : in    std_ulogic;
+
+    write_enable      : in std_ulogic;
+    addr              : in std_ulogic_vector (0 to addressbus_width-1);
+    data_in           : in std_ulogic_vector (0 to port_bitwidth-1);
+    data_out          : out std_ulogic_vector(0 to port_bitwidth-1)
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_128x168_1w_0;
+
+architecture tri_128x168_1w_0 of tri_128x168_1w_0 is
+
+constant wga_base_width : integer := 168;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+constant way : std_ulogic_vector(0 to 0) := "0";
+
+
+type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal write_enable_d     : std_ulogic;
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      addr_latch: tri_rlmreg_p
+        generic map (width => addr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr,
+                  dout        => addr_l2 );
+
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= act and write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+  abst_scan_out <= abst_scan_in;
+  repr_scan_out <= repr_scan_in;
+  time_scan_out <= time_scan_in;
+
+  bo_pc_failout  <= '0';
+  bo_pc_diagloop <= '0';
+
+  end generate um;
+  -- synopsys translate_on
+
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+      -- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+      -- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal ramb_data_in       : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+      signal ramb_data_out      : RAMB_DATA_ARRAY(way'range);
+      signal ramb_addr          : std_logic_vector(0 to ramb_base_addr - 1);
+
+      signal write              : std_ulogic_vector(way'range);
+      signal tidn               : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      add0: if (addressbus_width < ramb_base_addr) generate
+      begin
+        ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr );
+      end generate;
+      add1: if (addressbus_width >= ramb_base_addr) generate
+      begin
+        ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+      end generate;
+
+      din: for i in ramb_data_in'range generate
+      begin
+        R0: if(i <  port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate;
+        R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate;
+      end generate;
+
+      aw: for w in way'range generate begin
+        write(w) <= write_enable;
+
+        ax: for x in 0 to (ramb_width_mult - 1) generate begin
+          ram: RAMB16_S36_S36
+            -- pragma translate_off
+            generic map(
+                        sim_collision_check => "none")
+            -- pragma translate_on
+            port map(
+		DOA   => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DOB   => open,
+		DOPA  => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DOPB  => open,
+		ADDRA => ramb_addr,
+		ADDRB => ramb_addr,
+		CLKA  => nclk.clk,
+		CLKB  => tidn,
+		DIA   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIB   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIPA  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DIPB  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		ENA   => act,
+		ENB   => tidn,
+		SSRA  => nclk.sreset,
+		SSRB  => tidn,
+		WEA   => write(w),
+		WEB   => tidn
+	  );
+
+        end generate ax;
+
+        data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
+
+      end generate aw;
+      
+  abst_scan_out <= abst_scan_in;
+  repr_scan_out <= repr_scan_in;
+  time_scan_out <= time_scan_in;
+
+  bo_pc_failout  <= '0';
+  bo_pc_diagloop <= '0';
+
+  unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & ccflush_dc & scan_dis_dc_b & scan_diag_dc & lcb_d_mode_dc
+                       & lcb_clkoff_dc_b & lcb_act_dis_dc & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                       & lcb_delay_lclkr_dc & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0
+                       & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 & lcb_time_sl_thold_0
+                       & lcb_ary_nsl_thold_0 & lcb_bolt_sl_thold_0 & tc_lbist_ary_wrt_thru_dc
+                       & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist
+                       & addr_abist & r_wb_abist & pc_bo_enable_2 & pc_bo_reset
+                       & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+  end generate a;
+
+end tri_128x168_1w_0;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_128x16_1r1w_1.vhdl

@@ -0,0 +1,466 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;  use ieee.std_logic_1164.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library ibm; 
+             use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_128x16_1r1w_1 is
+  generic (addressable_ports : positive := 128; 
+           addressbus_width : positive := 7;    
+           port_bitwidth : positive := 16;      
+           ways : positive := 1;                
+           expand_type : integer := 1);         
+port (
+    vdd                          : INOUT power_logic; 
+    vcs                          : INOUT power_logic; 
+    gnd                          : INOUT power_logic; 
+  
+    nclk                         : IN clk_logic;
+
+    rd_act                             : IN std_ulogic;
+    wr_act            		       : IN std_ulogic;
+
+    lcb_d_mode_dc                : IN std_ulogic;
+    lcb_clkoff_dc_b              : IN std_ulogic;
+    lcb_mpw1_dc_b                : IN std_ulogic_vector(0 TO 4);
+    lcb_mpw2_dc_b                : IN std_ulogic;		
+    lcb_delay_lclkr_dc           : IN std_ulogic_vector(0 TO 4);		
+
+    ccflush_dc                   : IN  std_ulogic;
+    scan_dis_dc_b                : IN  std_ulogic;		
+    scan_diag_dc                 : IN  std_ulogic;
+    func_scan_in         : IN std_ulogic;
+    func_scan_out        : OUT std_ulogic;
+
+    lcb_sg_0              : IN std_ulogic;
+    lcb_sl_thold_0_b      : IN std_ulogic;
+    lcb_time_sl_thold_0        : IN std_ulogic;
+    lcb_abst_sl_thold_0        : IN std_ulogic;
+    lcb_ary_nsl_thold_0        : IN std_ulogic;
+    lcb_repr_sl_thold_0        : IN std_ulogic;
+    time_scan_in         : IN std_ulogic;
+    time_scan_out        : OUT std_ulogic;
+    abst_scan_in         : IN std_ulogic;
+    abst_scan_out        : OUT std_ulogic;
+    repr_scan_in         : IN std_ulogic;
+    repr_scan_out        : OUT std_ulogic;
+
+    abist_di                     : IN std_ulogic_vector(0 TO 3);
+    abist_bw_odd                 : IN std_ulogic;
+    abist_bw_even                : IN std_ulogic;
+    abist_wr_adr                 : IN std_ulogic_vector(0 TO 6);
+    wr_abst_act                  : IN std_ulogic;
+    abist_rd0_adr                : IN std_ulogic_vector(0 TO 6);
+    rd0_abst_act                 : IN std_ulogic;
+    tc_lbist_ary_wrt_thru_dc     : IN std_ulogic;
+    abist_ena_1                  : IN std_ulogic;
+    abist_g8t_rd0_comp_ena       : IN std_ulogic;
+    abist_raw_dc_b               : IN std_ulogic;
+    obs0_abist_cmp               : IN std_ulogic_vector(0 TO 3);
+
+    lcb_bolt_sl_thold_0         : in    std_ulogic;
+    pc_bo_enable_2              : in    std_ulogic; 
+    pc_bo_reset                 : in    std_ulogic; 
+    pc_bo_unload                : in    std_ulogic; 
+    pc_bo_repair                : in    std_ulogic; 
+    pc_bo_shdata                : in    std_ulogic; 
+    pc_bo_select                : in    std_ulogic; 
+    bo_pc_failout               : out   std_ulogic; 
+    bo_pc_diagloop              : out   std_ulogic;
+    tri_lcb_mpw1_dc_b           : in    std_ulogic;
+    tri_lcb_mpw2_dc_b           : in    std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in    std_ulogic;
+    tri_lcb_clkoff_dc_b         : in    std_ulogic;
+    tri_lcb_act_dis_dc          : in    std_ulogic;
+
+    bw                           : IN std_ulogic_vector( 0 TO 15 );  
+    wr_adr                       : IN std_ulogic_vector( 0 TO 6 );
+    rd_adr                       : IN std_ulogic_vector( 0 TO 6 );  
+    di                		 : IN std_ulogic_vector( 0 TO 15 );
+    do                        : OUT std_ulogic_vector( 0 TO 15 )
+		
+   );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity tri_128x16_1r1w_1;
+
+architecture tri_128x16_1r1w_1 of tri_128x16_1r1w_1 is
+
+begin
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+
+     constant rd_addr_offset       :  natural := 0;
+     constant wr_addr_offset       :  natural := rd_addr_offset + addressbus_width;
+     constant write_enable_offset  :  natural := wr_addr_offset + addressbus_width;
+     constant data_in_offset       :  natural := write_enable_offset + port_bitwidth;
+     constant data_out_offset      :  natural := data_in_offset + port_bitwidth;
+     constant array_offset         :  natural := data_out_offset + port_bitwidth;
+     constant scan_right           :  natural := array_offset + addressable_ports*port_bitwidth*ways - 1;
+
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal rd_addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal wr_addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal write_enable_d     : std_ulogic_vector(0 to port_bitwidth-1);
+      signal write_enable_l2    : std_ulogic_vector(0 to port_bitwidth-1);
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal data_out_d          : std_ulogic_vector(0 to port_bitwidth-1);
+      signal data_out_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal siv                      : std_ulogic_vector(0 to scan_right);
+      signal sov                      : std_ulogic_vector(0 to scan_right);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      rd_addr_latch: tri_rlmreg_p
+        generic map (width => rd_adr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => rd_act,
+                  scin        => siv(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1),
+                  scout       => sov(rd_addr_offset to rd_addr_offset+rd_addr_l2'length-1),
+                  din         => rd_adr,
+                  dout        => rd_addr_l2 );
+
+      wr_addr_latch: tri_rlmreg_p
+        generic map (width => wr_adr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1),
+                  scout       => sov(wr_addr_offset to wr_addr_offset+wr_addr_l2'length-1),
+                  din         => wr_adr,
+                  dout        => wr_addr_l2 );
+
+
+
+      write_enable_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(write_enable_offset to write_enable_offset+write_enable_l2'length-1),
+                  scout       => sov(write_enable_offset to write_enable_offset+write_enable_l2'length-1),
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(data_in_offset to data_in_offset+data_in_l2'length-1),
+                  scout       => sov(data_in_offset to data_in_offset+data_in_l2'length-1),
+                  din         => di,
+                  dout        => data_in_l2 );
+
+      data_out_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => siv(data_out_offset to data_out_offset+data_out_l2'length-1),
+                  scout       => sov(data_out_offset to data_out_offset+data_out_l2'length-1),
+                  din         => data_out_d,
+                  dout        => data_out_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => siv(array_offset to array_offset+array_l2'length-1),
+                  scout       => sov(array_offset to array_offset+array_l2'length-1),
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= bw when wr_act='1' else (others => '0');
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when ( write_enable_l2(x)='1' and wr_addr_l2 = tconv(y, addressbus_width)) 
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out_d(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth);
+      data_out_d(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1);
+      data_out_d(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2);
+      data_out_d(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3);
+      data_out_d(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4);
+      data_out_d(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5);
+      data_out_d(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6);
+      data_out_d(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7);
+      data_out_d(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8);
+      data_out_d(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9);
+      data_out_d(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10);
+      data_out_d(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11);
+      data_out_d(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12);
+      data_out_d(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13);
+      data_out_d(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14);
+      data_out_d(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15);
+
+      do(0) <= array_l2( tconv(rd_addr_l2)*port_bitwidth);
+      do(1) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+1);
+      do(2) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+2);
+      do(3) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+3);
+      do(4) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+4);
+      do(5) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+5);
+      do(6) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+6);
+      do(7) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+7);
+      do(8) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+8);
+      do(9) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+9);
+      do(10) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+10);
+      do(11) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+11);
+      do(12) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+12);
+      do(13) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+13);
+      do(14) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+14);
+      do(15) <= array_l2( tconv(rd_addr_l2)*port_bitwidth+15);
+
+  siv(0 to scan_right) <= sov(1 to scan_right) & func_scan_in;
+  func_scan_out <= sov(0);
+  
+  time_scan_out <= time_scan_in;
+  abst_scan_out <= abst_scan_in;
+  repr_scan_out <= repr_scan_in;
+
+  bo_pc_failout  <= '0';
+  bo_pc_diagloop <= '0';
+
+  end generate um;
+  -- synopsys translate_on
+
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+
+
+-- pragma translate_off
+-- pragma translate_on
+
+
+
+signal clk,clk2x                          : std_ulogic;
+signal b0addra,         b0addrb           : std_ulogic_vector(0 to 8);
+signal wea,             web               : std_ulogic;
+signal wren_a              : std_ulogic;
+signal reset_q                            : std_ulogic;
+signal gate_fq,         gate_d            : std_ulogic;
+signal r_data_out_1_d,  r_data_out_1_fq   : std_ulogic_vector(0 to 35);
+signal w_data_in_0                        : std_ulogic_vector(0 to 35);
+
+signal r_data_out_0_bram                  : std_logic_vector(0 to 35);
+signal r_data_out_1_bram                  : std_logic_vector(0 to 35);
+
+signal toggle_d     : std_ulogic;
+signal toggle_q     : std_ulogic;
+signal toggle2x_d   : std_ulogic;
+signal toggle2x_q   : std_ulogic;
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+clk   <= nclk.clk;
+clk2x <= nclk.clk2x;
+
+rlatch: process (clk) begin
+    if(rising_edge(clk)) then
+      reset_q              <= nclk.sreset;
+    end if;
+end process;
+
+
+tlatch: process (nclk.clk,reset_q)
+begin
+   if(rising_edge(nclk.clk)) then
+      if (reset_q = '1') then
+         toggle_q  <= '1';
+      else
+         toggle_q  <= toggle_d;
+      end if;
+    end if;
+end process;
+
+flatch: process (nclk.clk2x)
+begin
+   if(rising_edge(nclk.clk2x)) then
+      toggle2x_q <= toggle2x_d;
+      gate_fq  <= gate_d;
+      r_data_out_1_fq   <= r_data_out_1_d;
+   end if;
+end process;
+
+toggle_d   <= not toggle_q;
+toggle2x_d <= toggle_q;
+
+gate_d <= not(toggle_q xor toggle2x_q);
+
+
+
+
+
+b0addra(2 to 8)   <= wr_adr;
+b0addrb(2 to 8)   <= rd_adr;
+
+b0addra(0 to 1) <= "00";
+b0addrb(0 to 1) <= "00";
+
+
+
+wren_a <= '1' when bw /= "0000000000000000" else '0';
+wea         <= wren_a and not(gate_fq); 
+web         <= '0';
+w_data_in_0(0) <= di(0) when bw(0)='1' else r_data_out_0_bram(0);
+w_data_in_0(1) <= di(1) when bw(1)='1' else r_data_out_0_bram(1);
+w_data_in_0(2) <= di(2) when bw(2)='1' else r_data_out_0_bram(2);
+w_data_in_0(3) <= di(3) when bw(3)='1' else r_data_out_0_bram(3);
+w_data_in_0(4) <= di(4) when bw(4)='1' else r_data_out_0_bram(4);
+w_data_in_0(5) <= di(5) when bw(5)='1' else r_data_out_0_bram(5);
+w_data_in_0(6) <= di(6) when bw(6)='1' else r_data_out_0_bram(6);
+w_data_in_0(7) <= di(7) when bw(7)='1' else r_data_out_0_bram(7);
+w_data_in_0(8) <= di(8) when bw(8)='1' else r_data_out_0_bram(8);
+w_data_in_0(9) <= di(9) when bw(9)='1' else r_data_out_0_bram(9);
+w_data_in_0(10) <= di(10) when bw(10)='1' else r_data_out_0_bram(10);
+w_data_in_0(11) <= di(11) when bw(11)='1' else r_data_out_0_bram(11);
+w_data_in_0(12) <= di(12) when bw(12)='1' else r_data_out_0_bram(12);
+w_data_in_0(13) <= di(13) when bw(13)='1' else r_data_out_0_bram(13);
+w_data_in_0(14) <= di(14) when bw(14)='1' else r_data_out_0_bram(14);
+w_data_in_0(15) <= di(15) when bw(15)='1' else r_data_out_0_bram(15);
+w_data_in_0(16 to 35) <= (others => '0');
+
+r_data_out_1_d <= std_ulogic_vector(r_data_out_1_bram);
+
+bram0a : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                       clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => reset_q,
+	               ssrb  => reset_q,
+	               addra => std_logic_vector(b0addra),
+	               addrb => std_logic_vector(b0addrb),
+	               dia   => std_logic_vector(w_data_in_0(0 to 31)),
+	               dib   => (others => '0'),
+                       doa   => r_data_out_0_bram(0 to 31),
+                       dob   => r_data_out_1_bram(0 to 31),
+                       dopa  => r_data_out_0_bram(32 to 35),
+                       dopb  => r_data_out_1_bram(32 to 35),
+	               dipa  => std_logic_vector(w_data_in_0(32 to 35)),
+	               dipb  => (others => '0'),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea,
+	               web   => web
+	               );
+
+
+do   <= r_data_out_1_fq(0 to 15);
+
+func_scan_out <= func_scan_in;
+time_scan_out <= time_scan_in;
+abst_scan_out <= abst_scan_in;
+repr_scan_out <= repr_scan_in;
+
+bo_pc_failout  <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( std_ulogic_vector(r_data_out_0_bram(16 to 35)) & rd_act & wr_act
+                       & lcb_d_mode_dc & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                       & lcb_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc
+                       & lcb_sg_0 & lcb_sl_thold_0_b & lcb_time_sl_thold_0 & lcb_abst_sl_thold_0
+                       & lcb_ary_nsl_thold_0 & lcb_repr_sl_thold_0 & abist_di & abist_bw_odd
+                       & abist_bw_even & abist_wr_adr & wr_abst_act & abist_rd0_adr & rd0_abst_act
+                       & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                       & abist_raw_dc_b & obs0_abist_cmp & lcb_bolt_sl_thold_0 & pc_bo_enable_2
+                       & pc_bo_reset & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate a;
+
+
+end architecture tri_128x16_1r1w_1;
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w.vhdl

@@ -0,0 +1,411 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use ibm.std_ulogic_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+
+entity tri_144x78_2r2w is
+generic(
+   expand_type                         :     integer :=  1);
+port (
+   vdd                            :inout power_logic;    
+   gnd                            :inout power_logic;    
+   nclk                           :in   clk_logic;                 
+   abist_en                       :in   std_ulogic;  
+   abist_raw_dc_b                 :in   std_ulogic;  
+   r0e_abist_comp_en              :in   std_ulogic;  
+   r1e_abist_comp_en              :in   std_ulogic;  
+   lbist_en                      :in   std_ulogic;  
+
+   lcb_act_dis_dc                 :in   std_ulogic; 
+   lcb_clkoff_dc_b                :in   std_ulogic_vector(0 to 1);
+   lcb_d_mode_dc                  :in   std_ulogic;
+   lcb_delay_lclkr_dc             :in   std_ulogic_vector(0 to 9); 
+   lcb_fce_0                      :in   std_ulogic; 
+   lcb_mpw1_dc_b                  :in   std_ulogic_vector(1 to 9); 
+   lcb_mpw2_dc_b                  :in   std_ulogic; 
+   lcb_scan_diag_dc               :in   std_ulogic; 
+   lcb_scan_dis_dc_b              :in   std_ulogic; 
+   lcb_sg_0                       :in   std_ulogic; 
+   lcb_time_sg_0                  :in   std_ulogic;
+   lcb_obs0_sg_0                  :in   std_ulogic; 
+   lcb_obs1_sg_0                  :in   std_ulogic; 
+   lcb_obs0_sl_thold_0            :in   std_ulogic; 
+   lcb_obs1_sl_thold_0            :in   std_ulogic; 
+
+   lcb_abst_sl_thold_0            :in   std_ulogic;  
+   lcb_time_sl_thold_0            :in   std_ulogic; 
+   lcb_ary_nsl_thold_0            :in   std_ulogic;  
+
+   r_scan_in                      :in   std_ulogic;                 
+   r_scan_out                     :out  std_ulogic;   
+   w_scan_in                      :in   std_ulogic;                 
+   w_scan_out                     :out  std_ulogic;   
+   time_scan_in                   :in   std_ulogic; 
+   time_scan_out                  :out  std_ulogic; 
+   obs0_scan_in                   :in   std_ulogic; 
+   obs0_scan_out                  :out  std_ulogic; 
+   obs1_scan_in                   :in   std_ulogic; 
+   obs1_scan_out                  :out  std_ulogic; 
+
+   lcb_bolt_sl_thold_0            :in   std_ulogic;
+   pc_bo_enable_2                 :in   std_ulogic; 
+   pc_bo_reset                    :in   std_ulogic; 
+   pc_bo_unload                   :in   std_ulogic;
+   pc_bo_load                     :in   std_ulogic;
+   pc_bo_shdata                   :in   std_ulogic; 
+   pc_bo_select                   :in   std_ulogic; 
+   bo_pc_failout                  :out  std_ulogic; 
+   bo_pc_diagloop                 :out  std_ulogic;
+   tri_lcb_mpw1_dc_b              :in    std_ulogic;
+   tri_lcb_mpw2_dc_b              :in    std_ulogic;
+   tri_lcb_delay_lclkr_dc         :in    std_ulogic;
+   tri_lcb_clkoff_dc_b            :in    std_ulogic;
+   tri_lcb_act_dis_dc             :in    std_ulogic;
+
+   r0e_act                        :in   std_ulogic;                 
+   r0e_en_func                    :in   std_ulogic;                 
+   r0e_en_abist                   :in   std_ulogic;                 
+   r0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r0e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r0e_data_out                   :out  std_ulogic_vector(0 to 77); 
+   r0e_byp_e                      :in   std_ulogic; 
+   r0e_byp_l                      :in   std_ulogic; 
+   r0e_byp_r                      :in   std_ulogic;
+   r0e_sel_lbist                  :in   std_ulogic; 
+
+   r1e_act                        :in   std_ulogic;                 
+   r1e_en_func                    :in   std_ulogic;                 
+   r1e_en_abist                   :in   std_ulogic;                 
+   r1e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r1e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r1e_data_out                   :out  std_ulogic_vector(0 to 77);
+   r1e_byp_e                      :in   std_ulogic; 
+   r1e_byp_l                      :in   std_ulogic; 
+   r1e_byp_r                      :in   std_ulogic;
+   r1e_sel_lbist                  :in   std_ulogic; 
+
+   w0e_act                        :in   std_ulogic;                 
+   w0e_en_func                    :in   std_ulogic;                 
+   w0e_en_abist                   :in   std_ulogic;                 
+   w0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0e_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0e_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0e_data_abist                 :in   std_ulogic_vector(0 to 3);
+
+   w0l_act                        :in   std_ulogic;                 
+   w0l_en_func                    :in   std_ulogic;                 
+   w0l_en_abist                   :in   std_ulogic;                 
+   w0l_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0l_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0l_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0l_data_abist                 :in   std_ulogic_vector(0 to 3) );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity   tri_144x78_2r2w;
+architecture tri_144x78_2r2w of tri_144x78_2r2w is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal  tilo                           : std_ulogic;
+signal  tihi                           : std_ulogic;
+signal  zeross                         : std_logic_vector(0 to 3); 
+
+signal  correct_clk                    : std_ulogic;
+signal  clk2x                          : std_ulogic;
+signal  reset                          : std_ulogic;
+signal  reset_hi                       : std_ulogic;
+signal  reset_lo                       : std_ulogic;
+signal  reset_q                        : std_ulogic;
+signal  sinit0_q        : std_logic;
+signal  sinit1_q        : std_logic;
+signal  flipper_d                      : std_ulogic;
+signal  flipper_q                      : std_ulogic;
+
+signal  doutb0                         : std_logic_vector(0 to 77);
+signal  doutb0_q                       : std_ulogic_vector(0 to 77);
+signal dinfa0_par                      : std_logic_vector(64 to 95);
+signal doutb0_par                      : std_logic_vector(64 to 95);
+signal  weaf                           : std_logic;
+signal  addra                          : std_logic_vector(0 to 8); 
+signal  addrb0                         : std_logic_vector(0 to 8); 
+signal  dinfa                          : std_logic_vector(0 to 77); 
+signal  dinfb                          : std_logic_vector(0 to 31); 
+
+signal  w0e_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_en_q                       : std_ulogic;
+signal  w0l_addr_q                     : std_ulogic_vector(0 to 7);
+signal  r1e_addr_q                     : std_ulogic_vector(0 to 7);
+
+signal   r0e_byp_e_q                   :   std_ulogic; 
+signal   r0e_byp_l_q                   :   std_ulogic; 
+signal   r1e_byp_e_q                   :   std_ulogic; 
+signal   r1e_byp_l_q                   :   std_ulogic; 
+signal   r0_byp_sel                    :   std_ulogic_vector(0 to 1);
+signal   r1_byp_sel                    :   std_ulogic_vector(0 to 1);
+
+signal unused           : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+   tilo      <= '0';
+   tihi      <= '1';
+   zeross    <= (0 to 3  => '0');
+
+       reset       <= nclk.sreset;
+       correct_clk <= nclk.clk;
+       clk2x       <= nclk.clk2x;
+
+       reset_hi    <=     reset;
+       reset_lo    <= not reset_q after 1 ns ;
+
+
+   flipper_d <= not flipper_q;
+
+   slatch: process (correct_clk,reset) begin
+   if rising_edge(correct_clk) then
+    if (reset = '1') then
+      w0l_en_q    <= '0';
+      r1e_addr_q  <= (others => '0');
+      r0e_byp_e_q  <= '0';
+      r0e_byp_l_q  <= '0';
+      r1e_byp_e_q  <= '0';
+      r1e_byp_l_q  <= '0';
+
+    else
+      w0e_data_q   <= w0e_data_func;
+      w0l_data_q   <= w0l_data_func;
+      w0l_en_q     <= w0l_en_func;
+      w0l_addr_q   <= w0l_addr_func;
+      r1e_addr_q   <= r1e_addr_func;
+      r0e_byp_e_q  <= r0e_byp_e;
+      r0e_byp_l_q  <= r0e_byp_l;
+      r1e_byp_e_q  <= r1e_byp_e;
+      r1e_byp_l_q  <= r1e_byp_l;
+
+    end if;
+   end if;
+   end process;
+
+   flatch: process (clk2x,reset_lo) begin
+  if clk2x'event and clk2x = '1' then
+    if (reset_lo = '0') then
+      flipper_q  <= '0';
+
+    else
+      flipper_q    <= flipper_d;
+      doutb0_q     <= tconv(doutb0);
+
+    end if;
+   end if;
+   end process;
+
+   rlatch: process (correct_clk) begin
+    if(rising_edge(correct_clk)) then
+      reset_q   <= reset_hi;
+      sinit0_q  <= reset_hi;
+      sinit1_q  <= reset_hi;
+    end if;
+   end process;
+
+
+   addra(0)       <= '0';
+   addra(1 to 8)  <= (tconv((w0e_addr_func and (0 to  7 => flipper_q)) or (w0l_addr_q and (0 to  7 => not flipper_q))))  after 1 ns ; 
+   weaf           <= ((      w0e_en_func   and             flipper_q)  or (  w0l_en_q and             not  flipper_q))   after 1 ns;
+   dinfa          <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q))))  after 1 ns;
+ 
+   dinfb          <= (others => '0');
+   addrb0(0)      <= '0';
+   addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q  and (0 to 7 => not flipper_q)))) after 1 ns ;  
+
+   r0_byp_sel <= r0e_byp_e & r0e_byp_l;
+   with r0_byp_sel select 
+   r0e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     doutb0_q   when others;
+
+   r1_byp_sel <= r1e_byp_e & r1e_byp_l;
+   with r1_byp_sel select 
+   r1e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     tconv(doutb0) when others;
+
+
+U0 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(0 to 31),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(0 to 31),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit0_q,
+		SSRB  => sinit0_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+U1 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(32 to 63),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(32 to 63),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+doutb0(64 to 77)     <= doutb0_par(64 to 77);
+dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0');
+
+U2 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0_par(64 to 95),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa0_par(64 to 95),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+r_scan_out <= '0';
+w_scan_out <= '0';
+time_scan_out <= '0';
+obs0_scan_out <= '0';
+obs1_scan_out <= '0';
+
+bo_pc_failout <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95))
+                     & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en
+                     & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc
+                     & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                     & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0
+                     & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0
+                     & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0
+                     & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in
+                     & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist
+                     & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist
+                     & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist
+                     & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate;
+
+end architecture tri_144x78_2r2w;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_144x78_2r2w_eco.vhdl

@@ -0,0 +1,412 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use ibm.std_ulogic_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+
+entity tri_144x78_2r2w_eco is
+generic(
+   expand_type                         :     integer :=  1);
+port (
+   vdd                            :inout power_logic;    
+   gnd                            :inout power_logic;    
+   nclk                           :in   clk_logic;                 
+   abist_en                       :in   std_ulogic;  
+   abist_raw_dc_b                 :in   std_ulogic;  
+   r0e_abist_comp_en              :in   std_ulogic;  
+   r1e_abist_comp_en              :in   std_ulogic;  
+   lbist_en                      :in   std_ulogic;  
+
+   lcb_act_dis_dc                 :in   std_ulogic; 
+   lcb_clkoff_dc_b                :in   std_ulogic_vector(0 to 1);
+   lcb_d_mode_dc                  :in   std_ulogic;
+   lcb_delay_lclkr_dc             :in   std_ulogic_vector(0 to 9); 
+   lcb_fce_0                      :in   std_ulogic; 
+   lcb_mpw1_dc_b                  :in   std_ulogic_vector(1 to 9); 
+   lcb_mpw2_dc_b                  :in   std_ulogic; 
+   lcb_scan_diag_dc               :in   std_ulogic; 
+   lcb_scan_dis_dc_b              :in   std_ulogic; 
+   lcb_sg_0                       :in   std_ulogic; 
+   lcb_time_sg_0                  :in   std_ulogic;
+
+   lcb_obs0_sg_0                  :in   std_ulogic; 
+   lcb_obs1_sg_0                  :in   std_ulogic; 
+   lcb_obs0_sl_thold_0            :in   std_ulogic; 
+   lcb_obs1_sl_thold_0            :in   std_ulogic; 
+
+   lcb_abst_sl_thold_0            :in   std_ulogic;  
+   lcb_time_sl_thold_0            :in   std_ulogic; 
+   lcb_ary_nsl_thold_0            :in   std_ulogic;  
+
+   r_scan_in                      :in   std_ulogic;                 
+   r_scan_out                     :out  std_ulogic;   
+   w_scan_in                      :in   std_ulogic;                 
+   w_scan_out                     :out  std_ulogic;   
+   time_scan_in                   :in   std_ulogic; 
+   time_scan_out                  :out  std_ulogic; 
+   obs0_scan_in                   :in   std_ulogic; 
+   obs0_scan_out                  :out  std_ulogic; 
+   obs1_scan_in                   :in   std_ulogic; 
+   obs1_scan_out                  :out  std_ulogic; 
+
+   lcb_bolt_sl_thold_0            :in   std_ulogic;
+   pc_bo_enable_2                 :in   std_ulogic; 
+   pc_bo_reset                    :in   std_ulogic; 
+   pc_bo_unload                   :in   std_ulogic;
+   pc_bo_load                     :in   std_ulogic;
+   pc_bo_shdata                   :in   std_ulogic; 
+   pc_bo_select                   :in   std_ulogic; 
+   bo_pc_failout                  :out  std_ulogic; 
+   bo_pc_diagloop                 :out  std_ulogic;
+   tri_lcb_mpw1_dc_b              :in    std_ulogic;
+   tri_lcb_mpw2_dc_b              :in    std_ulogic;
+   tri_lcb_delay_lclkr_dc         :in    std_ulogic;
+   tri_lcb_clkoff_dc_b            :in    std_ulogic;
+   tri_lcb_act_dis_dc             :in    std_ulogic;
+
+   r0e_act                        :in   std_ulogic;                 
+   r0e_en_func                    :in   std_ulogic;                 
+   r0e_en_abist                   :in   std_ulogic;                 
+   r0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r0e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r0e_data_out                   :out  std_ulogic_vector(0 to 77); 
+   r0e_byp_e                      :in   std_ulogic; 
+   r0e_byp_l                      :in   std_ulogic; 
+   r0e_byp_r                      :in   std_ulogic;
+   r0e_sel_lbist                  :in   std_ulogic; 
+
+   r1e_act                        :in   std_ulogic;                 
+   r1e_en_func                    :in   std_ulogic;                 
+   r1e_en_abist                   :in   std_ulogic;                 
+   r1e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   r1e_addr_abist                 :in   std_ulogic_vector(0 to 7);   
+   r1e_data_out                   :out  std_ulogic_vector(0 to 77);
+   r1e_byp_e                      :in   std_ulogic; 
+   r1e_byp_l                      :in   std_ulogic; 
+   r1e_byp_r                      :in   std_ulogic;
+   r1e_sel_lbist                  :in   std_ulogic; 
+
+   w0e_act                        :in   std_ulogic;                 
+   w0e_en_func                    :in   std_ulogic;                 
+   w0e_en_abist                   :in   std_ulogic;                 
+   w0e_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0e_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0e_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0e_data_abist                 :in   std_ulogic_vector(0 to 3);
+
+   w0l_act                        :in   std_ulogic;                 
+   w0l_en_func                    :in   std_ulogic;                 
+   w0l_en_abist                   :in   std_ulogic;                 
+   w0l_addr_func                  :in   std_ulogic_vector(0 to 7);  
+   w0l_addr_abist                 :in   std_ulogic_vector(0 to 7);  
+   w0l_data_func                  :in   std_ulogic_vector(0 to 77); 
+   w0l_data_abist                 :in   std_ulogic_vector(0 to 3) );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity   tri_144x78_2r2w_eco;
+architecture tri_144x78_2r2w_eco of tri_144x78_2r2w_eco is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal  tilo                           : std_ulogic;
+signal  tihi                           : std_ulogic;
+signal  zeross                         : std_logic_vector(0 to 3); 
+
+signal  correct_clk                    : std_ulogic;
+signal  clk2x                          : std_ulogic;
+signal  reset                          : std_ulogic;
+signal  reset_hi                       : std_ulogic;
+signal  reset_lo                       : std_ulogic;
+signal  reset_q                        : std_ulogic;
+signal  sinit0_q        : std_logic;
+signal  sinit1_q        : std_logic;
+signal  flipper_d                      : std_ulogic;
+signal  flipper_q                      : std_ulogic;
+
+signal  doutb0                         : std_logic_vector(0 to 77);
+signal  doutb0_q                       : std_ulogic_vector(0 to 77);
+signal dinfa0_par                      : std_logic_vector(64 to 95);
+signal doutb0_par                      : std_logic_vector(64 to 95);
+signal  weaf                           : std_logic;
+signal  addra                          : std_logic_vector(0 to 8); 
+signal  addrb0                         : std_logic_vector(0 to 8); 
+signal  dinfa                          : std_logic_vector(0 to 77); 
+signal  dinfb                          : std_logic_vector(0 to 31); 
+
+signal  w0e_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_data_q                     : std_ulogic_vector(0 to 77);
+signal  w0l_en_q                       : std_ulogic;
+signal  w0l_addr_q                     : std_ulogic_vector(0 to 7);
+signal  r1e_addr_q                     : std_ulogic_vector(0 to 7);
+
+signal   r0e_byp_e_q                   :   std_ulogic; 
+signal   r0e_byp_l_q                   :   std_ulogic; 
+signal   r1e_byp_e_q                   :   std_ulogic; 
+signal   r1e_byp_l_q                   :   std_ulogic; 
+signal   r0_byp_sel                    :   std_ulogic_vector(0 to 1);
+signal   r1_byp_sel                    :   std_ulogic_vector(0 to 1);
+
+signal unused           : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+   tilo      <= '0';
+   tihi      <= '1';
+   zeross    <= (0 to 3  => '0');
+
+       reset       <= nclk.sreset;
+       correct_clk <= nclk.clk;
+       clk2x       <= nclk.clk2x;
+
+       reset_hi    <=     reset;
+       reset_lo    <= not reset_q after 1 ns ;
+
+
+   flipper_d <= not flipper_q;
+
+   slatch: process (correct_clk,reset) begin
+   if rising_edge(correct_clk) then
+    if (reset = '1') then
+      w0l_en_q    <= '0';
+      r1e_addr_q  <= (others => '0');
+      r0e_byp_e_q  <= '0';
+      r0e_byp_l_q  <= '0';
+      r1e_byp_e_q  <= '0';
+      r1e_byp_l_q  <= '0';
+
+    else
+      w0e_data_q   <= w0e_data_func;
+      w0l_data_q   <= w0l_data_func;
+      w0l_en_q     <= w0l_en_func;
+      w0l_addr_q   <= w0l_addr_func;
+      r1e_addr_q   <= r1e_addr_func;
+      r0e_byp_e_q  <= r0e_byp_e;
+      r0e_byp_l_q  <= r0e_byp_l;
+      r1e_byp_e_q  <= r1e_byp_e;
+      r1e_byp_l_q  <= r1e_byp_l;
+
+    end if;
+   end if;
+   end process;
+
+   flatch: process (clk2x,reset_lo) begin
+  if clk2x'event and clk2x = '1' then
+    if (reset_lo = '0') then
+      flipper_q  <= '0';
+
+    else
+      flipper_q    <= flipper_d;
+      doutb0_q     <= tconv(doutb0);
+
+    end if;
+   end if;
+   end process;
+
+   rlatch: process (correct_clk) begin
+    if(rising_edge(correct_clk)) then
+      reset_q   <= reset_hi;
+      sinit0_q  <= reset_hi;
+      sinit1_q  <= reset_hi;
+    end if;
+   end process;
+
+
+   addra(0)       <= '0';
+   addra(1 to 8)  <= (tconv((w0e_addr_func and (0 to  7 => flipper_q)) or (w0l_addr_q and (0 to  7 => not flipper_q))))  after 1 ns ; 
+   weaf           <= ((      w0e_en_func   and             flipper_q)  or (  w0l_en_q and             not  flipper_q))   after 1 ns;
+   dinfa          <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q))))  after 1 ns;
+ 
+   dinfb          <= (others => '0');
+   addrb0(0)      <= '0';
+   addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q  and (0 to 7 => not flipper_q)))) after 1 ns ;  
+
+   r0_byp_sel <= r0e_byp_e & r0e_byp_l;
+   with r0_byp_sel select 
+   r0e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     doutb0_q   when others;
+
+   r1_byp_sel <= r1e_byp_e & r1e_byp_l;
+   with r1_byp_sel select 
+   r1e_data_out   <= w0e_data_q when "10",
+                     w0l_data_q when "01",
+                     tconv(doutb0) when others;
+
+
+U0 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(0 to 31),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(0 to 31),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit0_q,
+		SSRB  => sinit0_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+U1 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0(32 to 63),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa(32 to 63),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+doutb0(64 to 77)     <= doutb0_par(64 to 77);
+dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0');
+
+U2 : RAMB16_S36_S36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+	port map 
+	(
+		DOA   => open,
+		DOB   => doutb0_par(64 to 95),
+		DOPA  => open,
+		DOPB  => open,
+		ADDRA => addra,
+		ADDRB => addrb0,
+		CLKA  => clk2x,
+		CLKB  => clk2x,
+		DIA   => dinfa0_par(64 to 95),
+		DIB   => dinfb,
+		DIPA  => zeross,
+		DIPB  => zeross,
+		ENA   => tihi,
+		ENB   => tihi,
+		SSRA  => sinit1_q,
+		SSRB  => sinit1_q,
+		WEA   => weaf,
+		WEB   => tilo
+	);
+
+r_scan_out <= '0';
+w_scan_out <= '0';
+time_scan_out <= '0';
+obs0_scan_out <= '0';
+obs1_scan_out <= '0';
+
+bo_pc_failout <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95))
+                     & abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en
+                     & lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc
+                     & lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b
+                     & lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0
+                     & lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0
+                     & lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0
+                     & r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in
+                     & r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist
+                     & r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist
+                     & w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist
+                     & w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate;
+
+end architecture tri_144x78_2r2w_eco;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_256x162_4w_0.vhdl

@@ -0,0 +1,359 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support;
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_256x162_4w_0 is
+  generic (addressable_ports : positive := 256; 
+           addressbus_width : positive := 8;    
+           port_bitwidth : positive := 162;     
+           ways : positive := 4;                
+           expand_type : integer := 1);         
+  port (
+    gnd               : inout power_logic;
+    vdd               : inout power_logic;
+    vcs               : inout power_logic;
+    nclk                        : in  clk_logic;
+    ccflush_dc                  : in  std_ulogic;
+    lcb_clkoff_dc_b             : in  std_ulogic;
+    lcb_d_mode_dc               : in  std_ulogic;
+    lcb_act_dis_dc              : in  std_ulogic;
+    lcb_ary_nsl_thold_0         : in  std_ulogic;
+    lcb_sg_1                    : in  std_ulogic;
+    lcb_abst_sl_thold_0         : in  std_ulogic;
+    scan_diag_dc                : in  std_ulogic;
+    scan_dis_dc_b               : in  std_ulogic;
+    abst_scan_in                : in  std_ulogic_vector(0 to 1);
+    abst_scan_out               : out std_ulogic_vector(0 to 1);
+    lcb_delay_lclkr_np_dc       : in  std_ulogic;
+    ctrl_lcb_delay_lclkr_np_dc  : in  std_ulogic;
+    dibw_lcb_delay_lclkr_np_dc  : in  std_ulogic;
+    ctrl_lcb_mpw1_np_dc_b       : in  std_ulogic;
+    dibw_lcb_mpw1_np_dc_b       : in  std_ulogic;
+    lcb_mpw1_pp_dc_b            : in  std_ulogic;
+    lcb_mpw1_2_pp_dc_b          : in  std_ulogic;
+    aodo_lcb_delay_lclkr_dc     : in  std_ulogic;
+    aodo_lcb_mpw1_dc_b          : in  std_ulogic;
+    aodo_lcb_mpw2_dc_b          : in  std_ulogic;
+    lcb_time_sg_0               : in    std_ulogic;
+    lcb_time_sl_thold_0         : in    std_ulogic;
+    time_scan_in                : in    std_ulogic;
+    time_scan_out               : out   std_ulogic;
+    bitw_abist                  : in    std_ulogic_vector(0 to 1);
+    lcb_repr_sl_thold_0         : in    std_ulogic;
+    lcb_repr_sg_0               : in    std_ulogic;
+    repr_scan_in                : in    std_ulogic;
+    repr_scan_out               : out   std_ulogic;
+    tc_lbist_ary_wrt_thru_dc    : in    std_ulogic;
+    abist_en_1                  : in    std_ulogic;
+    din_abist                   : in    std_ulogic_vector(0 to 3);
+    abist_cmp_en                : in    std_ulogic;
+    abist_raw_b_dc              : in    std_ulogic;
+    data_cmp_abist              : in    std_ulogic_vector(0 to 3);
+    addr_abist                  : in    std_ulogic_vector(0 to (addressbus_width-1));
+    r_wb_abist                  : in    std_ulogic;
+    write_thru_en_dc            : in    std_ulogic;
+    lcb_bolt_sl_thold_0         : in    std_ulogic; 
+    pc_bo_enable_2              : in    std_ulogic; 
+    pc_bo_reset                 : in    std_ulogic; 
+    pc_bo_unload                : in    std_ulogic;
+    pc_bo_repair                : in    std_ulogic; 
+    pc_bo_shdata                : in    std_ulogic; 
+    pc_bo_select                : in    std_ulogic_vector(0 to 1); 
+    bo_pc_failout               : out   std_ulogic_vector(0 to 1); 
+    bo_pc_diagloop              : out   std_ulogic_vector(0 to 1);
+    tri_lcb_mpw1_dc_b           : in    std_ulogic;
+    tri_lcb_mpw2_dc_b           : in    std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in    std_ulogic;
+    tri_lcb_clkoff_dc_b         : in    std_ulogic;
+    tri_lcb_act_dis_dc          : in    std_ulogic;
+    read_act          : in std_ulogic;
+    write_enable      : in std_ulogic;
+    write_way         : in std_ulogic_vector (0 to (ways-1));
+    addr              : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in           : in std_ulogic_vector (0 to (port_bitwidth-1));
+    data_out          : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_256x162_4w_0;
+
+architecture tri_256x162_4w_0 of tri_256x162_4w_0 is
+
+constant wga_base_width : integer := 324;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+
+
+type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal act                : std_ulogic;
+      signal addr_l2            : std_ulogic_vector (0 TO addressbus_width-1);
+      signal write_way_l2       : std_ulogic_vector (0 TO write_way'right);
+      signal write_enable_d     : std_ulogic;
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      act <= read_act or or_reduce(write_way);
+
+      addr_latch: tri_rlmreg_p
+        generic map (width => addr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr,
+                  dout        => addr_l2 );
+
+      write_way_latch: tri_rlmreg_p
+        generic map (width => write_way'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => write_way,
+                  dout        => write_way_l2 );
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= act and write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and 
+                                          write_way_l2(w)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out     <= "00";
+      time_scan_out     <= '0';
+      repr_scan_out     <= '0';
+
+      bo_pc_failout     <= "00";
+      bo_pc_diagloop    <= "00";
+
+  end generate um;
+  -- synopsys translate_on
+
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+        -- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+        -- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal ramb_data_in       : std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+      signal ramb_data_out      : RAMB_DATA_ARRAY(0 to ways-1);
+      signal ramb_addr          : std_logic_vector(0 to ramb_base_addr - 1);
+
+      signal act                : std_ulogic_vector(0 to ways-1);
+      signal write              : std_ulogic_vector(0 to ways-1);
+      signal tidn               : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      add0: if (addressbus_width < ramb_base_addr) generate
+      begin
+        ramb_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( addr );
+      end generate;
+      add1: if (addressbus_width >= ramb_base_addr) generate
+      begin
+        ramb_addr <= tconv( addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+      end generate;
+
+      din: for i in ramb_data_in'range generate
+      begin
+        R0: if(i <  port_bitwidth) generate begin ramb_data_in(i) <= data_in(i); end generate;
+        R1: if(i >= port_bitwidth) generate begin ramb_data_in(i) <= '0'; end generate;
+      end generate;
+
+      aw: for w in 0 to ways-1 generate begin
+        act(w) <= read_act or write_way(w);
+        write(w) <= write_enable and write_way(w);
+
+        ax: for x in 0 to (ramb_width_mult - 1) generate begin
+          arr: RAMB16_S36_S36
+            -- pragma translate_off
+            generic map(
+                        sim_collision_check => "none")
+            -- pragma translate_on
+            port map(
+		DOA   => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DOB   => open,
+		DOPA  => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DOPB  => open,
+		ADDRA => ramb_addr,
+		ADDRB => ramb_addr,
+		CLKA  => nclk.clk,
+		CLKB  => tidn,
+		DIA   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIB   => ramb_data_in(x*ramb_base_width to x*ramb_base_width+31),
+		DIPA  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DIPB  => ramb_data_in(x*ramb_base_width+32 to x*ramb_base_width+35),
+		ENA   => act(w),
+		ENB   => tidn,
+		SSRA  => nclk.sreset,
+		SSRB  => tidn,
+		WEA   => write(w),
+		WEB   => tidn
+	  );
+
+        end generate ax;
+
+        data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
+
+      end generate aw;
+
+      abst_scan_out     <= "00";
+      time_scan_out     <= '0';
+      repr_scan_out     <= '0';
+
+      bo_pc_failout     <= "00";
+      bo_pc_diagloop    <= "00";
+
+      unused <= or_reduce( std_ulogic_vector(ramb_data_out(0)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & std_ulogic_vector(ramb_data_out(1)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & std_ulogic_vector(ramb_data_out(2)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & std_ulogic_vector(ramb_data_out(3)(port_bitwidth to ramb_base_width*ramb_width_mult - 1))
+                       & ccflush_dc & lcb_clkoff_dc_b & lcb_d_mode_dc & lcb_act_dis_dc
+                       & scan_dis_dc_b & scan_diag_dc & bitw_abist
+                       & lcb_sg_1 & lcb_time_sg_0 & lcb_repr_sg_0
+                       & lcb_abst_sl_thold_0 & lcb_repr_sl_thold_0 
+                       & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc 
+                       & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist 
+                       & addr_abist & r_wb_abist & write_thru_en_dc & abst_scan_in & time_scan_in & repr_scan_in
+                       & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc
+                       & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b
+                       & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b
+                       & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                       & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+  end generate a;
+
+end tri_256x162_4w_0;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_32x35_8w_1r1w.vhdl

@@ -0,0 +1,578 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm;  use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_32x35_8w_1r1w is
+  generic (addressable_ports : positive := 32; 
+           addressbus_width : positive := 5;   
+           port_bitwidth : positive := 35;     
+           ways : positive := 8;                
+           expand_type : integer := 1);         
+  port (
+    gnd               : inout power_logic;
+    vdd               : inout power_logic;
+    vcs               : inout power_logic;
+    nclk              : in clk_logic;
+    rd0_act           : in std_ulogic;
+    sg_0              : in std_ulogic;
+    abst_slp_sl_thold_0 : in std_ulogic;
+    ary_slp_nsl_thold_0 : in std_ulogic;
+    time_sl_thold_0   : in std_ulogic;
+    repr_sl_thold_0   : in std_ulogic;
+    clkoff_dc_b       : in std_ulogic;
+    ccflush_dc        : in std_ulogic;
+    scan_dis_dc_b     : in std_ulogic;
+    scan_diag_dc      : in std_ulogic;
+    d_mode_dc         : in std_ulogic;
+    mpw1_dc_b         : in std_ulogic_vector(0 to 4);
+    mpw2_dc_b         : in std_ulogic;
+    delay_lclkr_dc    : in std_ulogic_vector(0 to 4);
+    wr_abst_act       : in std_ulogic;
+    rd0_abst_act      : in std_ulogic;
+    abist_di          : in std_ulogic_vector(0 to 3);
+    abist_bw_odd      : in std_ulogic;
+    abist_bw_even     : in std_ulogic;
+    abist_wr_adr      : in std_ulogic_vector(0 to 4);
+    abist_rd0_adr     : in std_ulogic_vector(0 to 4);
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_ena_1                 : in std_ulogic;
+    abist_g8t_rd0_comp_ena      : in std_ulogic;
+    abist_raw_dc_b              : in std_ulogic;
+    obs0_abist_cmp              : in std_ulogic_vector(0 to 3);
+    abst_scan_in      : in std_ulogic;
+    time_scan_in      : in std_ulogic;
+    repr_scan_in      : in std_ulogic;
+    abst_scan_out     : out std_ulogic;
+    time_scan_out     : out std_ulogic;
+    repr_scan_out     : out std_ulogic;
+    lcb_bolt_sl_thold_0         : in std_ulogic;
+    pc_bo_enable_2              : in std_ulogic; 
+    pc_bo_reset                 : in std_ulogic; 
+    pc_bo_unload                : in std_ulogic; 
+    pc_bo_repair                : in std_ulogic; 
+    pc_bo_shdata                : in std_ulogic; 
+    pc_bo_select                : in std_ulogic_vector(0 to 3); 
+    bo_pc_failout               : out std_ulogic_vector(0 to 3); 
+    bo_pc_diagloop              : out std_ulogic_vector(0 to 3);
+    tri_lcb_mpw1_dc_b           : in  std_ulogic;
+    tri_lcb_mpw2_dc_b           : in  std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in  std_ulogic;
+    tri_lcb_clkoff_dc_b         : in  std_ulogic;
+    tri_lcb_act_dis_dc          : in  std_ulogic;
+    write_enable      : in std_ulogic_vector (0 to ((port_bitwidth*ways-1)/(port_bitwidth*2)));
+    way               : in std_ulogic_vector (0 to (ways-1));
+    addr_wr           : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in           : in std_ulogic_vector (0 to (port_bitwidth-1));
+    addr_rd_01        : in std_ulogic_vector (0 to (addressbus_width-1));
+    addr_rd_23        : in std_ulogic_vector (0 to (addressbus_width-1));
+    addr_rd_45        : in std_ulogic_vector (0 to (addressbus_width-1));
+    addr_rd_67        : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_out          : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_32x35_8w_1r1w;
+
+architecture tri_32x35_8w_1r1w of tri_32x35_8w_1r1w is
+
+constant wga_base_width : integer := 70;
+constant wga_base_addr  : integer := 5;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+
+
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal addr_rd_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal addr_wr_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal way_l2             : std_ulogic_vector (0 TO way'right);
+      signal write_enable_d     : std_ulogic_vector(0 to wga_width_mult-1);
+      signal write_enable_l2    : std_ulogic_vector(0 to wga_width_mult-1);
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal act                : std_ulogic;
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      act <= or_reduce(write_enable) or rd0_act;
+
+      addr_rd_latch: tri_rlmreg_p
+        generic map (width => addr_rd_01'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr_rd_01,
+                  dout        => addr_rd_l2 );
+
+      addr_wr_latch: tri_rlmreg_p
+        generic map (width => addr_wr'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr_wr,
+                  dout        => addr_wr_l2 );
+
+      way_latch: tri_rlmreg_p
+        generic map (width => way'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => way,
+                  dout        => way_l2 );
+
+      write_enable_latch: tri_rlmreg_p
+        generic map (width => wga_width_mult, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( or_reduce(write_enable_l2) and addr_wr_l2 = tconv(y, addressbus_width) and 
+                                          way_l2(w)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_rd_l2)*port_bitwidth*ways to tconv(addr_rd_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out <= tidn;
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= "0000";
+      bo_pc_diagloop <= "0000";
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+        -- pragma translate_off
+	generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+        -- pragma translate_on
+	port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal array_wr_data      : std_logic_vector(0 to port_bitwidth - 1);
+      signal ramb_data_in       : std_logic_vector(0 to 35);
+      signal ramb_data_outA     : std_logic_vector(0 to 35);
+      signal ramb_data_outB     : std_logic_vector(0 to 35);
+      signal ramb_data_outC     : std_logic_vector(0 to 35);
+      signal ramb_data_outD     : std_logic_vector(0 to 35);
+      signal ramb_data_outE     : std_logic_vector(0 to 35);
+      signal ramb_data_outF     : std_logic_vector(0 to 35);
+      signal ramb_data_outG     : std_logic_vector(0 to 35);
+      signal ramb_data_outH     : std_logic_vector(0 to 35);
+      signal ramb_addr_wr       : std_logic_vector(0 to ramb_base_addr - 1);
+      signal ramb_addr_rd       : std_logic_vector(0 to ramb_base_addr - 1);
+      signal data_outA          : std_ulogic_vector(0 to 35);
+      signal data_outB          : std_ulogic_vector(0 to 35);
+      signal data_outC          : std_ulogic_vector(0 to 35);
+      signal data_outD          : std_ulogic_vector(0 to 35);
+      signal data_outE          : std_ulogic_vector(0 to 35);
+      signal data_outF          : std_ulogic_vector(0 to 35);
+      signal data_outG          : std_ulogic_vector(0 to 35);
+      signal data_outH          : std_ulogic_vector(0 to 35);
+
+      signal rd_addr            : std_ulogic_vector(0 to ramb_base_addr - 1);
+      signal wr_addr            : std_ulogic_vector(0 to ramb_base_addr - 1);
+      signal write_enable_wA    : std_ulogic;
+      signal write_enable_wB    : std_ulogic;
+      signal write_enable_wC    : std_ulogic;
+      signal write_enable_wD    : std_ulogic;
+      signal write_enable_wE    : std_ulogic;
+      signal write_enable_wF    : std_ulogic;
+      signal write_enable_wG    : std_ulogic;
+      signal write_enable_wH    : std_ulogic;
+      signal tidn               : std_logic_vector(0 to 35);
+      signal act                : std_ulogic;
+      signal wen                : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= (others=>'0');
+
+      wen <= or_reduce(write_enable);
+      act <= rd0_act or wen;
+
+      array_wr_data <= tconv(data_in);
+      addr_calc : for t in 0 to 35 generate begin
+            R0 : if(t < 35 - (port_bitwidth-1))  generate begin ramb_data_in(t) <= '0';                                       end generate;
+            R1 : if(t >= 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= array_wr_data(t-(35-(port_bitwidth-1)));   end generate;
+      end generate addr_calc;
+
+      write_enable_wA <= wen and way(0);
+      write_enable_wB <= wen and way(1);
+      write_enable_wC <= wen and way(2);
+      write_enable_wD <= wen and way(3);
+      write_enable_wE <= wen and way(4);
+      write_enable_wF <= wen and way(5);
+      write_enable_wG <= wen and way(6);
+      write_enable_wH <= wen and way(7);      
+
+      rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin
+            R0 : if(t < ramb_base_addr-addressbus_width) generate begin
+                  rd_addr(t) <= '0';
+                  wr_addr(t) <= '0';
+                 end generate;
+            R1 : if(t >= ramb_base_addr-addressbus_width) generate begin
+                  rd_addr(t) <= addr_rd_01(t-(ramb_base_addr-addressbus_width));
+                  wr_addr(t) <= addr_wr(t-(ramb_base_addr-addressbus_width));
+                 end generate;
+      end generate rambAddrCalc;
+
+      ramb_addr_wr <= tconv(wr_addr);
+      ramb_addr_rd <= tconv(rd_addr);
+
+      data_outA <= tconv(ramb_data_outA);
+      data_outB <= tconv(ramb_data_outB);
+      data_outC <= tconv(ramb_data_outC);
+      data_outD <= tconv(ramb_data_outD);
+      data_outE <= tconv(ramb_data_outE);
+      data_outF <= tconv(ramb_data_outF);
+      data_outG <= tconv(ramb_data_outG);
+      data_outH <= tconv(ramb_data_outH);
+
+      data_out <= data_outA((35-(port_bitwidth-1)) to 35) & data_outB((35-(port_bitwidth-1)) to 35) &
+                  data_outC((35-(port_bitwidth-1)) to 35) & data_outD((35-(port_bitwidth-1)) to 35) &
+                  data_outE((35-(port_bitwidth-1)) to 35) & data_outF((35-(port_bitwidth-1)) to 35) &
+                  data_outG((35-(port_bitwidth-1)) to 35) & data_outH((35-(port_bitwidth-1)) to 35);
+
+      arr0_A: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outA(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outA(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wA
+	  );
+
+      arr1_B: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outB(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outB(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wB
+	  );
+
+      arr2_C: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outC(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outC(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wC
+	  );
+
+      arr3_D: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outD(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outD(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wD
+	  );
+
+      arr4_E: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outE(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outE(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wE
+	  );
+
+      arr5_F: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outF(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outF(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wF
+	  );
+
+      arr6_G: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outG(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outG(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wG
+	  );
+
+      arr7_H: RAMB16_S36_S36
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+             DOA   => ramb_data_outH(0 to 31),
+             DOB   => open,
+             DOPA  => ramb_data_outH(32 to 35),
+             DOPB  => open,
+             ADDRA => ramb_addr_rd,
+             ADDRB => ramb_addr_wr,
+             CLKA  => nclk.clk,
+             CLKB  => nclk.clk,
+             DIA   => tidn(0 to 31),
+             DIB   => ramb_data_in(0 to 31),
+             DIPA  => tidn(32 to 35),
+             DIPB  => ramb_data_in(32 to 35),
+             ENA   => act,
+             ENB   => act,
+             SSRA  => nclk.sreset,
+             SSRB  => nclk.sreset,
+             WEA   => tidn(0),
+             WEB   => write_enable_wH
+	  );
+
+      abst_scan_out <= tidn(0);
+      time_scan_out <= tidn(0);
+      repr_scan_out <= tidn(0);
+
+      bo_pc_failout <= "0000";
+      bo_pc_diagloop <= "0000";
+
+      unused <= or_reduce( data_outA(0) & data_outB(0) & data_outC(0) & data_outD(0)
+                           & data_outE(0) & data_outF(0) & data_outG(0) & data_outH(0)
+                           & sg_0 & abst_slp_sl_thold_0 & ary_slp_nsl_thold_0
+                           & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc
+                           & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b
+                           & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di
+                           & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                           & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                           & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in
+                           & repr_scan_in & addr_rd_23 & addr_rd_45 & addr_rd_67
+                           & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                           & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                           & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                           & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+  end generate a;
+
+end tri_32x35_8w_1r1w;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_512x288_9.vhdl

@@ -0,0 +1,762 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_512x288_9 is
+  generic (addressable_ports : positive := 512; 
+           addressbus_width : positive := 6;    
+           port_bitwidth : positive := 288;     
+           bit_write_type : positive := 9;  
+           ways : positive := 1;        
+           expand_type : integer := 1);         
+  port (
+    gnd               : inout power_logic;
+    vdd               : inout power_logic;
+    vcs               : inout power_logic;
+    nclk              : in clk_logic;
+    act               : in std_ulogic;
+    sg_0              : in std_ulogic;
+    sg_1              : in std_ulogic;
+    ary_nsl_thold_0   : in std_ulogic;
+    abst_sl_thold_0   : in std_ulogic;
+    time_sl_thold_0   : in std_ulogic;
+    repr_sl_thold_0   : in std_ulogic;
+    clkoff_dc_b       : in std_ulogic;
+    ccflush_dc        : in std_ulogic;
+    scan_dis_dc_b     : in std_ulogic;
+    scan_diag_dc      : in std_ulogic;
+    d_mode_dc         : in std_ulogic;
+    act_dis_dc        : in std_ulogic;
+    lcb_delay_lclkr_np_dc       : in std_ulogic;
+    ctrl_lcb_delay_lclkr_np_dc  : in std_ulogic;
+    dibw_lcb_delay_lclkr_np_dc  : in std_ulogic;
+    ctrl_lcb_mpw1_np_dc_b       : in std_ulogic;
+    dibw_lcb_mpw1_np_dc_b       : in std_ulogic;
+    lcb_mpw1_pp_dc_b            : in std_ulogic;
+    lcb_mpw1_2_pp_dc_b          : in std_ulogic;
+    aodo_lcb_delay_lclkr_dc     : in std_ulogic;
+    aodo_lcb_mpw1_dc_b          : in std_ulogic;
+    aodo_lcb_mpw2_dc_b          : in std_ulogic;
+    bitw_abist                  : in std_ulogic_vector(0 to 1);
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_en_1                  : in std_ulogic;
+    din_abist                   : in std_ulogic_vector(0 to 3);
+    abist_cmp_en                : in std_ulogic;
+    abist_raw_b_dc              : in std_ulogic;
+    data_cmp_abist              : in std_ulogic_vector(0 to 3);
+    addr_abist                  : in std_ulogic_vector(0 to 8);
+    r_wb_abist                  : in std_ulogic;
+    abst_scan_in      : in std_ulogic_vector(0 to 1);
+    time_scan_in      : in std_ulogic;
+    repr_scan_in      : in std_ulogic;
+    abst_scan_out     : out std_ulogic_vector(0 to 1);
+    time_scan_out     : out std_ulogic;
+    repr_scan_out     : out std_ulogic;
+    lcb_bolt_sl_thold_0         : in std_ulogic; 
+    pc_bo_enable_2              : in std_ulogic; 
+    pc_bo_reset                 : in std_ulogic; 
+    pc_bo_unload                : in std_ulogic;
+    pc_bo_repair                : in std_ulogic; 
+    pc_bo_shdata                : in std_ulogic; 
+    pc_bo_select                : in std_ulogic_vector(0 to 1); 
+    bo_pc_failout               : out std_ulogic_vector(0 to 1); 
+    bo_pc_diagloop              : out std_ulogic_vector(0 to 1);
+    tri_lcb_mpw1_dc_b           : in  std_ulogic;
+    tri_lcb_mpw2_dc_b           : in  std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in  std_ulogic;
+    tri_lcb_clkoff_dc_b         : in  std_ulogic;
+    tri_lcb_act_dis_dc          : in  std_ulogic;
+    write_enable      : in std_ulogic;
+    bw                : in std_ulogic_vector (0 to (port_bitwidth-1));
+    arr_up_addr       : in std_ulogic_vector (0 to 2);
+    addr              : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in           : in std_ulogic_vector (0 to (port_bitwidth-1));
+    data_out          : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_512x288_9;
+
+architecture tri_512x288_9 of tri_512x288_9 is
+
+
+
+
+constant ramb_base_addr  : integer := 11;
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal addr_l2            : std_ulogic_vector(0 TO addressbus_width-1);
+      signal bw_l2              : std_ulogic_vector(0 TO bw'right);
+      signal write_enable_d     : std_ulogic;
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      addr_latch: tri_rlmreg_p
+        generic map (width => addr'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => addr,
+                  dout        => addr_l2 );
+
+      bw_latch: tri_rlmreg_p
+        generic map (width => bw'length, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => bw,
+                  dout        => bw_l2 );
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => write_enable_d,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      write_enable_d <= act and write_enable;
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(x)  when (( write_enable_l2 and addr_l2 = tconv(y, addressbus_width) and bw_l2(x/bit_write_type) ) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(addr_l2)*port_bitwidth*ways to tconv(addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out <= (others=>'0');
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= (others=>'0');
+      bo_pc_diagloop <= (others=>'0');
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+      component RAMB16_S9_S9
+      -- pragma translate_off
+	generic
+	(
+		SIM_COLLISION_CHECK : string := "none"); 
+      -- pragma translate_on
+	port
+	(
+		DOA : out std_logic_vector(7 downto 0);
+		DOB : out std_logic_vector(7 downto 0);
+		DOPA : out std_logic_vector(0 downto 0);
+		DOPB : out std_logic_vector(0 downto 0);
+		ADDRA : in std_logic_vector(10 downto 0);
+		ADDRB : in std_logic_vector(10 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(7 downto 0);
+		DIB : in std_logic_vector(7 downto 0);
+		DIPA : in std_logic_vector(0 downto 0);
+		DIPB : in std_logic_vector(0 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      constant addresswidth     : integer := addressbus_width+3+1;
+      signal arr_data_in        : std_logic_vector(0 to 287);
+      signal ramb_data_in       : std_logic_vector(0 to 255);
+      signal ramb_parity_in     : std_logic_vector(0 to 31);
+      signal ramb_uh_addr       : std_ulogic_vector(0 to 10);
+      signal ramb_lh_addr       : std_ulogic_vector(0 to 10);
+      signal uh_addr            : std_ulogic_vector(0 to addresswidth-1);
+      signal lh_addr            : std_ulogic_vector(0 to addresswidth-1);
+      signal ramb_data_out      : std_logic_vector(0 to 255);
+      signal ramb_parity_out    : std_logic_vector(0 to 31);
+
+      signal tidn               : std_ulogic;
+      signal wrt_en_wAH         : std_ulogic_vector(0 to 31);
+      signal bitWrt             : std_ulogic_vector(0 to 31);
+      signal rdDataOut          : std_ulogic_vector(0 to 255);
+      signal rdParityOut        : std_ulogic_vector(0 to 31);
+
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      arr_data_in   <= tconv(data_in);
+
+      dWFixUp : for t in 0 to 31 generate begin
+            ramb_data_in((8*t) to (8*t)+7) <= arr_data_in(t+0)   & arr_data_in(t+32)  & arr_data_in(t+64)  & arr_data_in(t+96) &
+                                              arr_data_in(t+144) & arr_data_in(t+176) & arr_data_in(t+208) & arr_data_in(t+240);
+            ramb_parity_in(t)              <= arr_data_in(t+128+(128*(t/16)));
+            bitWrt(t)                      <= bw(t);
+      end generate dWFixUp;
+
+      wrtEn_gen : for t in 0 to 31 generate begin
+            wrt_en_wAH(t) <= write_enable and bitWrt(t);
+      end generate wrtEn_gen;
+
+      uh_addr <= arr_up_addr & addr & '0';
+      lh_addr <= arr_up_addr & addr & '1';
+
+      rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin
+            R0 : if(t < ramb_base_addr-addresswidth) generate begin
+                  ramb_uh_addr(t) <= '0';
+                  ramb_lh_addr(t) <= '0';
+                 end generate;
+            R1 : if(t >= ramb_base_addr-addresswidth) generate begin
+                  ramb_uh_addr(t) <= uh_addr(t-(ramb_base_addr-addresswidth));
+                  ramb_lh_addr(t) <= lh_addr(t-(ramb_base_addr-addresswidth));
+                 end generate;
+      end generate rambAddrCalc;     
+
+      dRFixUp : for t in 0 to 31 generate begin
+            data_out(t+0)                <= rdDataOut((t*8)+0);
+            data_out(t+32)               <= rdDataOut((t*8)+1);
+            data_out(t+64)               <= rdDataOut((t*8)+2);
+            data_out(t+96)               <= rdDataOut((t*8)+3);
+            data_out(t+144)              <= rdDataOut((t*8)+4);
+            data_out(t+176)              <= rdDataOut((t*8)+5);
+            data_out(t+208)              <= rdDataOut((t*8)+6);
+            data_out(t+240)              <= rdDataOut((t*8)+7);
+            data_out(t+128+(128*(t/16))) <= rdParityOut(t);
+      end generate dRFixUp;
+
+      rdDataOut   <= tconv(ramb_data_out);
+      rdParityOut <= tconv(ramb_parity_out);
+
+      arr0: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(0 to 7),
+              DOB   => ramb_data_out(128 to 135),
+              DOPA  => ramb_parity_out(0 to 0),
+              DOPB  => ramb_parity_out(16 to 16),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(0 to 7),
+              DIB   => ramb_data_in(128 to 135),
+              DIPA  => ramb_parity_in(0 to 0),
+              DIPB  => ramb_parity_in(16 to 16),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(0),
+              WEB   => wrt_en_wAH(16)
+	    );
+
+      arr1: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(8 to 15),
+              DOB   => ramb_data_out(136 to 143),
+              DOPA  => ramb_parity_out(1 to 1),
+              DOPB  => ramb_parity_out(17 to 17),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(8 to 15),
+              DIB   => ramb_data_in(136 to 143),
+              DIPA  => ramb_parity_in(1 to 1),
+              DIPB  => ramb_parity_in(17 to 17),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(1),
+              WEB   => wrt_en_wAH(17)
+	    );
+
+      arr2: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(16 to 23),
+              DOB   => ramb_data_out(144 to 151),
+              DOPA  => ramb_parity_out(2 to 2),
+              DOPB  => ramb_parity_out(18 to 18),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(16 to 23),
+              DIB   => ramb_data_in(144 to 151),
+              DIPA  => ramb_parity_in(2 to 2),
+              DIPB  => ramb_parity_in(18 to 18),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(2),
+              WEB   => wrt_en_wAH(18)
+	    );
+
+      arr3: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(24 to 31),
+              DOB   => ramb_data_out(152 to 159),
+              DOPA  => ramb_parity_out(3 to 3),
+              DOPB  => ramb_parity_out(19 to 19),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(24 to 31),
+              DIB   => ramb_data_in(152 to 159),
+              DIPA  => ramb_parity_in(3 to 3),
+              DIPB  => ramb_parity_in(19 to 19),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(3),
+              WEB   => wrt_en_wAH(19)
+	    );
+
+      arr4: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(32 to 39),
+              DOB   => ramb_data_out(160 to 167),
+              DOPA  => ramb_parity_out(4 to 4),
+              DOPB  => ramb_parity_out(20 to 20),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(32 to 39),
+              DIB   => ramb_data_in(160 to 167),
+              DIPA  => ramb_parity_in(4 to 4),
+              DIPB  => ramb_parity_in(20 to 20),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(4),
+              WEB   => wrt_en_wAH(20)
+	    );
+
+      arr5: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(40 to 47),
+              DOB   => ramb_data_out(168 to 175),
+              DOPA  => ramb_parity_out(5 to 5),
+              DOPB  => ramb_parity_out(21 to 21),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(40 to 47),
+              DIB   => ramb_data_in(168 to 175),
+              DIPA  => ramb_parity_in(5 to 5),
+              DIPB  => ramb_parity_in(21 to 21),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(5),
+              WEB   => wrt_en_wAH(21)
+	    );
+
+      arr6: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(48 to 55),
+              DOB   => ramb_data_out(176 to 183),
+              DOPA  => ramb_parity_out(6 to 6),
+              DOPB  => ramb_parity_out(22 to 22),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(48 to 55),
+              DIB   => ramb_data_in(176 to 183),
+              DIPA  => ramb_parity_in(6 to 6),
+              DIPB  => ramb_parity_in(22 to 22),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(6),
+              WEB   => wrt_en_wAH(22)
+	    );
+
+      arr7: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(56 to 63),
+              DOB   => ramb_data_out(184 to 191),
+              DOPA  => ramb_parity_out(7 to 7),
+              DOPB  => ramb_parity_out(23 to 23),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(56 to 63),
+              DIB   => ramb_data_in(184 to 191),
+              DIPA  => ramb_parity_in(7 to 7),
+              DIPB  => ramb_parity_in(23 to 23),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(7),
+              WEB   => wrt_en_wAH(23)
+	    );
+
+      arr8: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(64 to 71),
+              DOB   => ramb_data_out(192 to 199),
+              DOPA  => ramb_parity_out(8 to 8),
+              DOPB  => ramb_parity_out(24 to 24),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(64 to 71),
+              DIB   => ramb_data_in(192 to 199),
+              DIPA  => ramb_parity_in(8 to 8),
+              DIPB  => ramb_parity_in(24 to 24),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(8),
+              WEB   => wrt_en_wAH(24)
+	    );
+
+      arr9: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(72 to 79),
+              DOB   => ramb_data_out(200 to 207),
+              DOPA  => ramb_parity_out(9 to 9),
+              DOPB  => ramb_parity_out(25 to 25),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(72 to 79),
+              DIB   => ramb_data_in(200 to 207),
+              DIPA  => ramb_parity_in(9 to 9),
+              DIPB  => ramb_parity_in(25 to 25),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(9),
+              WEB   => wrt_en_wAH(25)
+	    );
+
+      arrA: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(80 to 87),
+              DOB   => ramb_data_out(208 to 215),
+              DOPA  => ramb_parity_out(10 to 10),
+              DOPB  => ramb_parity_out(26 to 26),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(80 to 87),
+              DIB   => ramb_data_in(208 to 215),
+              DIPA  => ramb_parity_in(10 to 10),
+              DIPB  => ramb_parity_in(26 to 26),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(10),
+              WEB   => wrt_en_wAH(26)
+	    );
+
+      arrB: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(88 to 95),
+              DOB   => ramb_data_out(216 to 223),
+              DOPA  => ramb_parity_out(11 to 11),
+              DOPB  => ramb_parity_out(27 to 27),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(88 to 95),
+              DIB   => ramb_data_in(216 to 223),
+              DIPA  => ramb_parity_in(11 to 11),
+              DIPB  => ramb_parity_in(27 to 27),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(11),
+              WEB   => wrt_en_wAH(27)
+	    );
+
+      arrC: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(96 to 103),
+              DOB   => ramb_data_out(224 to 231),
+              DOPA  => ramb_parity_out(12 to 12),
+              DOPB  => ramb_parity_out(28 to 28),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(96 to 103),
+              DIB   => ramb_data_in(224 to 231),
+              DIPA  => ramb_parity_in(12 to 12),
+              DIPB  => ramb_parity_in(28 to 28),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(12),
+              WEB   => wrt_en_wAH(28)
+	    );
+
+      arrD: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(104 to 111),
+              DOB   => ramb_data_out(232 to 239),
+              DOPA  => ramb_parity_out(13 to 13),
+              DOPB  => ramb_parity_out(29 to 29),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(104 to 111),
+              DIB   => ramb_data_in(232 to 239),
+              DIPA  => ramb_parity_in(13 to 13),
+              DIPB  => ramb_parity_in(29 to 29),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(13),
+              WEB   => wrt_en_wAH(29)
+	    );
+
+      arrE: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(112 to 119),
+              DOB   => ramb_data_out(240 to 247),
+              DOPA  => ramb_parity_out(14 to 14),
+              DOPB  => ramb_parity_out(30 to 30),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(112 to 119),
+              DIB   => ramb_data_in(240 to 247),
+              DIPA  => ramb_parity_in(14 to 14),
+              DIPB  => ramb_parity_in(30 to 30),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(14),
+              WEB   => wrt_en_wAH(30)
+	    );
+
+      arrF: RAMB16_S9_S9
+          -- pragma translate_off
+          generic map(
+                      sim_collision_check => "none")
+          -- pragma translate_on
+          port map(
+              DOA   => ramb_data_out(120 to 127),
+              DOB   => ramb_data_out(248 to 255),
+              DOPA  => ramb_parity_out(15 to 15),
+              DOPB  => ramb_parity_out(31 to 31),
+              ADDRA => tconv(ramb_uh_addr),
+              ADDRB => tconv(ramb_lh_addr),
+              CLKA  => nclk.clk,
+              CLKB  => nclk.clk,
+              DIA   => ramb_data_in(120 to 127),
+              DIB   => ramb_data_in(248 to 255),
+              DIPA  => ramb_parity_in(15 to 15),
+              DIPB  => ramb_parity_in(31 to 31),
+              ENA   => act,
+              ENB   => act,
+              SSRA  => nclk.sreset,
+              SSRB  => nclk.sreset,
+              WEA   => wrt_en_wAH(15),
+              WEB   => wrt_en_wAH(31)
+	    );
+
+      abst_scan_out <= (others=>'0');
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= (others=>'0');
+      bo_pc_diagloop <= (others=>'0');
+
+      unused <= or_reduce( bw(32 to port_bitwidth-1)
+                       & clkoff_dc_b & ccflush_dc & scan_dis_dc_b & scan_diag_dc & d_mode_dc & act_dis_dc
+                       & bitw_abist & sg_0 & sg_1
+                       & abst_sl_thold_0 & repr_sl_thold_0 
+                       & time_sl_thold_0 & ary_nsl_thold_0 & tc_lbist_ary_wrt_thru_dc 
+                       & abist_en_1 & din_abist & abist_cmp_en & abist_raw_b_dc & data_cmp_abist 
+                       & addr_abist & r_wb_abist & abst_scan_in & time_scan_in & repr_scan_in
+                       & lcb_delay_lclkr_np_dc & ctrl_lcb_delay_lclkr_np_dc & dibw_lcb_delay_lclkr_np_dc
+                       & ctrl_lcb_mpw1_np_dc_b & dibw_lcb_mpw1_np_dc_b & lcb_mpw1_pp_dc_b & lcb_mpw1_2_pp_dc_b
+                       & aodo_lcb_delay_lclkr_dc & aodo_lcb_mpw1_dc_b & aodo_lcb_mpw2_dc_b
+                       & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                       & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                       & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                       & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+  end generate a;
+
+
+end tri_512x288_9;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x36_4w_1r1w.vhdl

@@ -0,0 +1,357 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ;
+library ibm; use ibm.std_ulogic_support.all ;
+             use ibm.std_ulogic_function_support.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_64x36_4w_1r1w is
+  generic (addressable_ports : positive := 64;  
+           addressbus_width : positive := 6;    
+           port_bitwidth : positive := 36;      
+           ways : positive := 4;                
+           expand_type : integer := 1);         
+  port (
+    gnd                         : inout power_logic;
+    vdd                         : inout power_logic;
+    vcs                         : inout power_logic;
+    nclk                        : in clk_logic;
+    rd_act                      : in std_ulogic;
+    wr_act                      : in std_ulogic;
+    sg_0                        : in std_ulogic;
+    abst_sl_thold_0             : in std_ulogic;
+    ary_nsl_thold_0             : in std_ulogic;
+    time_sl_thold_0             : in std_ulogic;
+    repr_sl_thold_0             : in std_ulogic;
+    clkoff_dc_b                 : in std_ulogic;
+    ccflush_dc                  : in std_ulogic;
+    scan_dis_dc_b               : in std_ulogic;
+    scan_diag_dc                : in std_ulogic;
+    d_mode_dc                   : in std_ulogic;
+    mpw1_dc_b                   : in std_ulogic_vector(0 to 4);
+    mpw2_dc_b                   : in std_ulogic;
+    delay_lclkr_dc              : in std_ulogic_vector(0 to 4);
+    wr_abst_act                 : in std_ulogic;
+    rd0_abst_act                : in std_ulogic;
+    abist_di                    : in std_ulogic_vector(0 to 3);
+    abist_bw_odd                : in std_ulogic;
+    abist_bw_even               : in std_ulogic;
+    abist_wr_adr                : in std_ulogic_vector(0 to 5);
+    abist_rd0_adr               : in std_ulogic_vector(0 to 5);
+    tc_lbist_ary_wrt_thru_dc    : in std_ulogic;
+    abist_ena_1                 : in std_ulogic;
+    abist_g8t_rd0_comp_ena      : in std_ulogic;
+    abist_raw_dc_b              : in std_ulogic;
+    obs0_abist_cmp              : in std_ulogic_vector(0 to 3);
+    abst_scan_in                : in std_ulogic_vector(0 to 1);
+    time_scan_in                : in std_ulogic;
+    repr_scan_in                : in std_ulogic;
+    abst_scan_out               : out std_ulogic_vector(0 to 1);
+    time_scan_out               : out std_ulogic;
+    repr_scan_out               : out std_ulogic;
+    lcb_bolt_sl_thold_0         : in std_ulogic;
+    pc_bo_enable_2              : in std_ulogic; 
+    pc_bo_reset                 : in std_ulogic; 
+    pc_bo_unload                : in std_ulogic; 
+    pc_bo_repair                : in std_ulogic; 
+    pc_bo_shdata                : in std_ulogic; 
+    pc_bo_select                : in std_ulogic_vector(0 to 1); 
+    bo_pc_failout               : out std_ulogic_vector(0 to 1); 
+    bo_pc_diagloop              : out std_ulogic_vector(0 to 1);
+    tri_lcb_mpw1_dc_b           : in  std_ulogic;
+    tri_lcb_mpw2_dc_b           : in  std_ulogic;
+    tri_lcb_delay_lclkr_dc      : in  std_ulogic;
+    tri_lcb_clkoff_dc_b         : in  std_ulogic;
+    tri_lcb_act_dis_dc          : in  std_ulogic;
+    wr_way                      : in std_ulogic_vector (0 to (ways-1));
+    wr_addr                     : in std_ulogic_vector (0 to (addressbus_width-1));
+    data_in                     : in std_ulogic_vector (0 to (port_bitwidth*ways-1));
+    rd_addr                     : in std_ulogic_vector(0 to (addressbus_width-1));
+    data_out                    : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
+);
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_64x36_4w_1r1w;
+
+architecture tri_64x36_4w_1r1w of tri_64x36_4w_1r1w is
+
+constant wga_base_width : integer := 72;
+constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
+constant ramb_base_width : integer := 36;
+constant ramb_base_addr  : integer := 9;
+constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;  
+
+
+type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
+
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+      signal tiup               : std_ulogic;
+      signal tidn               : std_ulogic;
+
+      signal wr_addr_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal rd_addr_l2         : std_ulogic_vector (0 TO addressbus_width-1);
+      signal way_l2             : std_ulogic_vector (0 TO wr_way'right);
+      signal write_enable_l2    : std_ulogic;
+      signal data_in_l2         : std_ulogic_vector(0 to port_bitwidth*ways-1);
+      signal array_d            : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+      signal array_l2           : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
+  begin
+      tiup <= '1';
+      tidn <= '0';
+
+      wr_addr_latch: tri_rlmreg_p
+        generic map (width => wr_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => wr_addr,
+                  dout        => wr_addr_l2 );
+
+      rd_addr_latch: tri_rlmreg_p
+        generic map (width => rd_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => rd_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => rd_addr,
+                  dout        => rd_addr_l2 );
+
+      way_latch: tri_rlmreg_p
+        generic map (width => wr_way'length, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => wr_way,
+                  dout        => way_l2 );
+
+      write_enable_latch: tri_rlmlatch_p
+        generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => tidn,
+                  scout       => open,
+                  din         => wr_act,
+                  dout        => write_enable_l2 );
+
+      data_in_latch: tri_rlmreg_p
+        generic map (width => port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => wr_act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => data_in,
+                  dout        => data_in_l2 );
+
+      array_latch: tri_rlmreg_p
+        generic map (width => addressable_ports*port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type)
+        port map (vd          => vdd,
+                  gd          => gnd,
+                  nclk        => nclk,
+                  act         => tiup,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => array_d,
+                  dout        => array_l2 );
+
+      ww: for w in 0 to ways-1 generate
+      begin
+        wy: for y in 0 to addressable_ports-1 generate
+        begin
+          wx: for x in 0 to port_bitwidth-1 generate
+          begin
+            array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
+                   data_in_l2(w*port_bitwidth+x)  when (( write_enable_l2 and wr_addr_l2 = tconv(y, addressbus_width) and 
+                                          way_l2(w)) = '1')
+              else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
+
+          end generate wx;
+        end generate wy;
+      end generate ww;
+
+      data_out <= array_l2( tconv(rd_addr_l2)*port_bitwidth*ways to tconv(rd_addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
+
+      abst_scan_out <= tidn & tidn;
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= tidn & tidn;
+      bo_pc_diagloop <= tidn & tidn;
+  end generate um;
+  -- synopsys translate_on
+
+
+  a: if expand_type = 1 generate
+      component RAMB16_S36_S36
+      -- pragma translate_off
+	generic
+	(
+		SIM_COLLISION_CHECK : string := "none"); 
+      -- pragma translate_on
+	port
+	(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic
+	);
+      end component;
+
+      -- pragma translate_off
+      -- pragma translate_on
+
+      signal ramb_data_in       : RAMB_DATA_ARRAY(wr_way'range);
+      signal ramb_data_out      : RAMB_DATA_ARRAY(wr_way'range);
+      signal ramb_rd_addr       : std_logic_vector(0 to ramb_base_addr - 1);
+      signal ramb_wr_addr       : std_logic_vector(0 to ramb_base_addr - 1);
+
+      signal tidn               : std_ulogic;
+      signal unused             : std_ulogic;
+      -- synopsys translate_off
+      -- synopsys translate_on
+  begin
+
+      tidn <= '0';
+
+      add0: if (addressbus_width < ramb_base_addr) generate
+      begin
+        ramb_rd_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_rd_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( rd_addr );
+
+        ramb_wr_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
+        ramb_wr_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( wr_addr );
+      end generate;
+      add1: if (addressbus_width >= ramb_base_addr) generate
+      begin
+        ramb_rd_addr <= tconv( rd_addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+        ramb_wr_addr <= tconv( wr_addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
+      end generate;
+
+      dw: for w in wr_way'range generate begin
+        din: for i in 0 to (ramb_base_width*ramb_width_mult - 1) generate
+        begin
+          R0: if(i <  port_bitwidth) generate begin ramb_data_in(w)(i) <= data_in(w*port_bitwidth+i); end generate;
+          R1: if(i >= port_bitwidth) generate begin ramb_data_in(w)(i) <= '0'; end generate;
+        end generate din;
+      end generate dw;
+
+      aw: for w in wr_way'range generate begin
+        ax: for x in 0 to (ramb_width_mult - 1) generate begin
+          arr: RAMB16_S36_S36
+            -- pragma translate_off
+            generic map(
+                        sim_collision_check => "none")
+            -- pragma translate_on
+            port map(
+		DOA   => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DOB   => open,
+		DOPA  => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DOPB  => open,
+		ADDRA => ramb_rd_addr,
+		ADDRB => ramb_wr_addr,
+		CLKA  => nclk.clk,
+		CLKB  => nclk.clk,
+		DIA   => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DIB   => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31),
+		DIPA  => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		DIPB  => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
+		ENA   => rd_act,
+		ENB   => wr_act,
+		SSRA  => nclk.sreset,
+		SSRB  => nclk.sreset,
+		WEA   => tidn,
+		WEB   => wr_way(w)
+	  );
+
+        end generate ax;
+
+        data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
+
+      end generate aw;
+
+      abst_scan_out <= tidn & tidn;
+      time_scan_out <= tidn;
+      repr_scan_out <= tidn;
+
+      bo_pc_failout <= tidn & tidn;
+      bo_pc_diagloop <= tidn & tidn;
+
+      unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0
+                           & time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc
+                           & scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b
+                           & delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di
+                           & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                           & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                           & abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in
+                           & repr_scan_in & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                           & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                           & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                           & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+  end generate a;
+
+
+end tri_64x36_4w_1r1w;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x42_4w_1r1w.vhdl

@@ -0,0 +1,381 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_64x42_4w_1r1w is
+generic(
+   expand_type                         : integer :=  1);
+port (
+   vdd                                 : INOUT power_logic; 
+   vcs                                 : INOUT power_logic; 
+   gnd                                 : INOUT power_logic; 
+
+   nclk                                : in clk_logic;
+   sg_0                                : in  std_ulogic;
+   abst_sl_thold_0                     : in  std_ulogic;
+   ary_nsl_thold_0                     : in  std_ulogic;
+   time_sl_thold_0                     : in  std_ulogic;
+   repr_sl_thold_0                     : in  std_ulogic;
+
+   rd0_act                             : in std_ulogic;
+   rd0_adr                             : in std_ulogic_vector(0 to 5);  
+   do0                                 : out std_ulogic_vector(0 to 167);
+   
+   wr_way                              : in std_ulogic_vector (0 to 3);
+   wr_act            		       : in std_ulogic;
+   wr_adr            		       : in std_ulogic_vector(0 to 5);    		
+   di                		       : in std_ulogic_vector(0 to 167);
+     
+   abst_scan_in                        : in  std_ulogic;
+   abst_scan_out                       : out std_ulogic;
+   time_scan_in                        : in  std_ulogic;
+   time_scan_out                       : out std_ulogic;
+   repr_scan_in                        : in  std_ulogic;
+   repr_scan_out                       : out std_ulogic;
+   
+   scan_dis_dc_b                       : in  std_ulogic;
+   scan_diag_dc                        : in  std_ulogic;
+   ccflush_dc                          : in  std_ulogic;
+   ary0_clkoff_dc_b                    : in  std_ulogic;
+   ary0_d_mode_dc                      : in  std_ulogic;
+   ary0_mpw1_dc_b                      : in  std_ulogic_vector(0 to 4);
+   ary0_mpw2_dc_b                      : in  std_ulogic;
+   ary0_delay_lclkr_dc                 : in  std_ulogic_vector(0 to 4);
+   ary1_clkoff_dc_b                    : in  std_ulogic;
+   ary1_d_mode_dc                      : in  std_ulogic;
+   ary1_mpw1_dc_b                      : in  std_ulogic_vector(0 to 4);
+   ary1_mpw2_dc_b                      : in  std_ulogic;
+   ary1_delay_lclkr_dc                 : in  std_ulogic_vector(0 to 4);
+
+   lcb_bolt_sl_thold_0                 : in  std_ulogic;
+   pc_bo_enable_2                      : in  std_ulogic; 
+   pc_bo_reset                         : in  std_ulogic; 
+   pc_bo_unload                        : in  std_ulogic; 
+   pc_bo_repair                        : in  std_ulogic; 
+   pc_bo_shdata                        : in  std_ulogic; 
+   pc_bo_select                        : in  std_ulogic_vector(0 to 1); 
+   bo_pc_failout                       : out std_ulogic_vector(0 to 1); 
+   bo_pc_diagloop                      : out std_ulogic_vector(0 to 1);
+   tri_lcb_mpw1_dc_b                   : in  std_ulogic;
+   tri_lcb_mpw2_dc_b                   : in  std_ulogic;
+   tri_lcb_delay_lclkr_dc              : in  std_ulogic;
+   tri_lcb_clkoff_dc_b                 : in  std_ulogic;
+   tri_lcb_act_dis_dc                  : in  std_ulogic;
+
+   abist_di                            : in  std_ulogic_vector(0 to 3);
+   abist_bw_odd                        : in  std_ulogic;
+   abist_bw_even                       : in  std_ulogic;
+   abist_wr_adr                        : in  std_ulogic_vector(0 to 5);
+   wr_abst_act                         : in  std_ulogic;
+   abist_rd0_adr                       : in  std_ulogic_vector(0 to 5);
+   rd0_abst_act                        : in  std_ulogic;
+   tc_lbist_ary_wrt_thru_dc            : in  std_ulogic;
+   abist_ena_1                         : in  std_ulogic;
+   abist_g8t_rd0_comp_ena              : in  std_ulogic;
+   abist_raw_dc_b                      : in  std_ulogic;
+   obs0_abist_cmp                      : in  std_ulogic_vector(0 to 3)
+   );
+
+-- synopsys translate_off
+-- synopsys translate_on
+
+
+end entity tri_64x42_4w_1r1w;
+architecture tri_64x42_4w_1r1w of tri_64x42_4w_1r1w is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal clk,             clk2x             : std_ulogic;
+signal addra,           addrb             : std_ulogic_vector(0 to 8);
+signal wea0, wea1, wea2, wea3             : std_ulogic;
+signal web0, web1, web2, web3             : std_ulogic;
+signal bdo0, bdo1, bdo2, bdo3             : std_logic_vector(0 to 71);
+signal bdi0, bdi1, bdi2, bdi3             : std_ulogic_vector(0 to 71);
+signal sreset                             : std_ulogic;
+signal tidn                               : std_ulogic_vector(36 to 65);
+signal reset_q                            : std_ulogic;
+signal gate_fq,         gate_d            : std_ulogic;
+signal bdo_d,           bdo_fq            : std_ulogic_vector(0 to 167);
+
+signal toggle_d     : std_ulogic;
+signal toggle_q     : std_ulogic;
+signal toggle2x_d   : std_ulogic;
+signal toggle2x_q   : std_ulogic;
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+tidn  <= (others=>'0');
+clk   <= nclk.clk;
+clk2x <= nclk.clk2x;
+sreset<= nclk.sreset;
+
+rlatch: process (clk) begin
+    if(rising_edge(clk)) then
+      reset_q              <= sreset after 10 ps;
+    end if;
+end process;
+
+
+tlatch: process (nclk.clk,reset_q)
+begin
+   if(rising_edge(nclk.clk)) then
+      if (reset_q = '1') then
+         toggle_q  <= '1';
+      else
+         toggle_q  <= toggle_d;
+      end if;
+    end if;
+end process;
+
+flatch: process (nclk.clk2x)
+begin
+   if(rising_edge(nclk.clk2x)) then
+      toggle2x_q <= toggle2x_d;
+      gate_fq  <= gate_d;
+      bdo_fq   <= bdo_d;
+   end if;
+end process;
+
+toggle_d   <= not toggle_q;
+toggle2x_d <= toggle_q;
+
+gate_d <= not(toggle_q xor toggle2x_q);
+
+
+
+
+
+
+
+   bdi0        <= di(0   to  35) & tidn(36 to 65) & di(36  to  41);
+   bdi1        <= di(42  to  77) & tidn(36 to 65) & di(78  to  83);
+   bdi2        <= di(84  to 119) & tidn(36 to 65) & di(120 to 125);
+   bdi3        <= di(126 to 161) & tidn(36 to 65) & di(162 to 167);
+
+bdo_d(0   to  41) <= std_ulogic_vector(bdo0(0 to 35) & bdo0(66 to 71));
+bdo_d(42  to  83) <= std_ulogic_vector(bdo1(0 to 35) & bdo1(66 to 71));
+bdo_d(84  to 125) <= std_ulogic_vector(bdo2(0 to 35) & bdo2(66 to 71));
+bdo_d(126 to 167) <= std_ulogic_vector(bdo3(0 to 35) & bdo3(66 to 71));
+
+do0         <= bdo_fq;
+
+wea0        <= (wr_act and gate_fq and wr_way(0)) after 10 ps;
+web0        <= (wr_act and gate_fq and wr_way(0)) after 10 ps;
+wea1        <= (wr_act and gate_fq and wr_way(1)) after 10 ps;
+web1        <= (wr_act and gate_fq and wr_way(1)) after 10 ps;
+wea2        <= (wr_act and gate_fq and wr_way(2)) after 10 ps;
+web2        <= (wr_act and gate_fq and wr_way(2)) after 10 ps;
+wea3        <= (wr_act and gate_fq and wr_way(3)) after 10 ps;
+web3        <= (wr_act and gate_fq and wr_way(3)) after 10 ps;
+
+with gate_fq select
+   addra    <= ("00" & wr_adr  & '0') after 10 ps  when '1',
+               ("00" & rd0_adr & '0') after 10 ps when others;
+
+with gate_fq select
+   addrb    <= ("00" & wr_adr  & '1') after 10 ps when '1',
+               ("00" & rd0_adr & '1') after 10 ps when others;
+
+bram0a : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi0(00 to 31)),
+	               dipa  => std_logic_vector(bdi0(32 to 35)),
+	               dib   => std_logic_vector(bdi0(36 to 67)),
+	               dipb  => std_logic_vector(bdi0(68 to 71)),
+                  doa   => bdo0(00 to 31),
+                  dopa  => bdo0(32 to 35),
+                  dob   => bdo0(36 to 67),
+                  dopb  => bdo0(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea0,
+	               web   => web0
+	               );
+
+bram0b : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi1(00 to 31)),
+	               dipa  => std_logic_vector(bdi1(32 to 35)),
+	               dib   => std_logic_vector(bdi1(36 to 67)),
+	               dipb  => std_logic_vector(bdi1(68 to 71)),
+                  doa   => bdo1(00 to 31),
+                  dopa  => bdo1(32 to 35),
+                  dob   => bdo1(36 to 67),
+                  dopb  => bdo1(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea1,
+	               web   => web1
+	               );
+
+bram0c : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi2(00 to 31)),
+	               dipa  => std_logic_vector(bdi2(32 to 35)),
+	               dib   => std_logic_vector(bdi2(36 to 67)),
+	               dipb  => std_logic_vector(bdi2(68 to 71)),
+                  doa   => bdo2(00 to 31),
+                  dopa  => bdo2(32 to 35),
+                  dob   => bdo2(36 to 67),
+                  dopb  => bdo2(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea2,
+	               web   => web2
+	               );
+
+
+bram0d : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi3(00 to 31)),
+	               dipa  => std_logic_vector(bdi3(32 to 35)),
+	               dib   => std_logic_vector(bdi3(36 to 67)),
+	               dipb  => std_logic_vector(bdi3(68 to 71)),
+                  doa   => bdo3(00 to 31),
+                  dopa  => bdo3(32 to 35),
+                  dob   => bdo3(36 to 67),
+                  dopb  => bdo3(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea3,
+	               web   => web3
+	               );
+
+
+abst_scan_out  <= abst_scan_in;
+time_scan_out  <= time_scan_in;
+repr_scan_out  <= repr_scan_in;
+
+bo_pc_failout <= "00";
+bo_pc_diagloop <= "00";
+
+unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0
+                     & ary0_clkoff_dc_b & ary0_d_mode_dc & ary0_mpw1_dc_b & ary0_mpw2_dc_b
+                     & ary0_delay_lclkr_dc & ccflush_dc & scan_dis_dc_b & scan_diag_dc
+                     & ary1_clkoff_dc_b & ary1_d_mode_dc & ary1_mpw1_dc_b & ary1_mpw2_dc_b
+                     & ary1_delay_lclkr_dc & abist_di
+                     & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                     & wr_abst_act & rd0_abst_act
+                     & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                     & abist_raw_dc_b & obs0_abist_cmp & rd0_act
+                     & std_ulogic_vector( bdo0(36 to 65) ) & std_ulogic_vector( bdo1(36 to 65) )
+                     & std_ulogic_vector( bdo2(36 to 65) ) & std_ulogic_vector( bdo3(36 to 65) )
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+end generate;
+
+end architecture tri_64x42_4w_1r1w;
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_64x72_1r1w.vhdl

@@ -0,0 +1,285 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_function_support.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_64x72_1r1w is
+generic(
+   expand_type                         : integer :=  1;
+   regsize                             : integer := 64);
+port (
+   vdd                                 : INOUT power_logic; 
+   vcs                                 : INOUT power_logic; 
+   gnd                                 : INOUT power_logic; 
+
+   nclk                                : in clk_logic;
+   sg_0                                : in  std_ulogic;
+   abst_sl_thold_0                     : in  std_ulogic;
+   ary_nsl_thold_0                     : in  std_ulogic;
+   time_sl_thold_0                     : in  std_ulogic;
+   repr_sl_thold_0                     : in  std_ulogic;
+
+   rd0_act                             : in std_ulogic;
+   rd0_adr                             : in std_ulogic_vector(0 to 5);  
+   do0                                 : out std_ulogic_vector(64-regsize to 72-(64/regsize));
+
+   wr_act                              : in std_ulogic;
+   wr_adr                              : in std_ulogic_vector(0 to 5);
+   di                                  : in std_ulogic_vector(64-regsize to 72-(64/regsize));
+
+   abst_scan_in                        : in  std_ulogic;
+   abst_scan_out                       : out std_ulogic;
+   time_scan_in                        : in  std_ulogic;
+   time_scan_out                       : out std_ulogic;
+   repr_scan_in                        : in  std_ulogic;
+   repr_scan_out                       : out std_ulogic;
+   
+   scan_dis_dc_b                       : in  std_ulogic;
+   scan_diag_dc                        : in  std_ulogic;
+   ccflush_dc                          : in  std_ulogic;
+   clkoff_dc_b                         : in  std_ulogic;
+   d_mode_dc                           : in  std_ulogic;
+   mpw1_dc_b                           : in  std_ulogic_vector(0 to 4);
+   mpw2_dc_b                           : in  std_ulogic;
+   delay_lclkr_dc                      : in  std_ulogic_vector(0 to 4);
+
+   lcb_bolt_sl_thold_0                 : in  std_ulogic;
+   pc_bo_enable_2                      : in  std_ulogic; 
+   pc_bo_reset                         : in  std_ulogic; 
+   pc_bo_unload                        : in  std_ulogic; 
+   pc_bo_repair                        : in  std_ulogic; 
+   pc_bo_shdata                        : in  std_ulogic; 
+   pc_bo_select                        : in  std_ulogic; 
+   bo_pc_failout                       : out std_ulogic; 
+   bo_pc_diagloop                      : out std_ulogic;
+   tri_lcb_mpw1_dc_b                   : in  std_ulogic;
+   tri_lcb_mpw2_dc_b                   : in  std_ulogic;
+   tri_lcb_delay_lclkr_dc              : in  std_ulogic;
+   tri_lcb_clkoff_dc_b                 : in  std_ulogic;
+   tri_lcb_act_dis_dc                  : in  std_ulogic;
+
+   abist_di                            : in  std_ulogic_vector(0 to 3);
+   abist_bw_odd                        : in  std_ulogic;
+   abist_bw_even                       : in  std_ulogic;
+   abist_wr_adr                        : in  std_ulogic_vector(0 to 5);
+   wr_abst_act                         : in  std_ulogic;
+   abist_rd0_adr                       : in  std_ulogic_vector(0 to 5);
+   rd0_abst_act                        : in  std_ulogic;
+   tc_lbist_ary_wrt_thru_dc            : in  std_ulogic;
+   abist_ena_1                         : in  std_ulogic;
+   abist_g8t_rd0_comp_ena              : in  std_ulogic;
+   abist_raw_dc_b                      : in  std_ulogic;
+   obs0_abist_cmp                      : in  std_ulogic_vector(0 to 3)
+   );
+
+-- synopsys translate_off
+-- synopsys translate_on
+
+
+end entity tri_64x72_1r1w;
+architecture tri_64x72_1r1w of tri_64x72_1r1w is
+
+begin
+
+a : if expand_type = 1 generate
+
+component RAMB16_S36_S36
+-- pragma translate_off
+generic(
+		SIM_COLLISION_CHECK : string := "none"); 
+-- pragma translate_on
+port(
+		DOA : out std_logic_vector(31 downto 0);
+		DOB : out std_logic_vector(31 downto 0);
+		DOPA : out std_logic_vector(3 downto 0);
+		DOPB : out std_logic_vector(3 downto 0);
+		ADDRA : in std_logic_vector(8 downto 0);
+		ADDRB : in std_logic_vector(8 downto 0);
+		CLKA : in std_ulogic;
+		CLKB : in std_ulogic;
+		DIA : in std_logic_vector(31 downto 0);
+		DIB : in std_logic_vector(31 downto 0);
+		DIPA : in std_logic_vector(3 downto 0);
+		DIPB : in std_logic_vector(3 downto 0);
+		ENA : in std_ulogic;
+		ENB : in std_ulogic;
+		SSRA : in std_ulogic;
+		SSRB : in std_ulogic;
+		WEA : in std_ulogic;
+		WEB : in std_ulogic);
+end component;
+
+-- pragma translate_off
+-- pragma translate_on
+
+signal clk,             clk2x             : std_ulogic;
+signal addra,           addrb             : std_ulogic_vector(0 to 8);
+signal wea,             web               : std_ulogic;
+signal bdo                                : std_logic_vector(0 to 71);
+signal bdi                                : std_ulogic_vector(0 to 71);
+signal sreset                             : std_ulogic;
+signal tidn                               : std_ulogic_vector(0 to 71);
+signal reset_q                            : std_ulogic;
+signal gate_fq,         gate_d            : std_ulogic;
+signal bdo_d,           bdo_fq            : std_ulogic_vector(64-regsize to 72-(64/regsize));
+
+signal toggle_d     : std_ulogic;
+signal toggle_q     : std_ulogic;
+signal toggle2x_d   : std_ulogic;
+signal toggle2x_q   : std_ulogic;
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+tidn  <= (others=>'0');
+clk   <= nclk.clk;
+clk2x <= nclk.clk2x;
+sreset<= nclk.sreset;
+
+rlatch: process (clk) begin
+    if(rising_edge(clk)) then
+      reset_q              <= sreset after 10 ps;
+    end if;
+end process;
+
+
+tlatch: process (nclk.clk,reset_q)
+begin
+   if(rising_edge(nclk.clk)) then
+      if (reset_q = '1') then
+         toggle_q  <= '1';
+      else
+         toggle_q  <= toggle_d;
+      end if;
+    end if;
+end process;
+
+flatch: process (nclk.clk2x)
+begin
+   if(rising_edge(nclk.clk2x)) then
+      toggle2x_q <= toggle2x_d;
+      gate_fq  <= gate_d;
+      bdo_fq   <= bdo_d;
+   end if;
+end process;
+
+toggle_d   <= not toggle_q;
+toggle2x_d <= toggle_q;
+
+gate_d <= not(toggle_q xor toggle2x_q);
+
+
+
+
+
+
+in32 : if regsize = 32 generate
+   bdi         <= tidn(0 to 31) & di(32 to 63) & di(64 to 70) & tidn(71);
+end generate;
+in64 : if regsize = 64 generate
+   bdi         <= di(0 to 71);
+end generate;
+
+bdo_d       <= std_ulogic_vector(bdo(64-regsize to 72-(64/regsize)));
+do0         <= bdo_fq;
+
+wea         <= (wr_act and gate_fq) after 10 ps;
+web         <= (wr_act and gate_fq) after 10 ps;
+
+with gate_fq select
+   addra    <= ("00" & wr_adr  & '0') after 10 ps  when '1',
+               ("00" & rd0_adr & '0') after 10 ps when others;
+
+with gate_fq select
+   addrb    <= ("00" & wr_adr  & '1') after 10 ps when '1',
+               ("00" & rd0_adr & '1') after 10 ps when others;
+
+bram0a : ramb16_s36_s36
+-- pragma translate_off
+generic map(
+   sim_collision_check => "none")
+-- pragma translate_on
+port map(
+                  clka  => clk2x,
+	               clkb  => clk2x,
+	               ssra  => sreset,
+	               ssrb  => sreset,
+	               addra => std_logic_vector(addra),
+	               addrb => std_logic_vector(addrb),
+	               dia   => std_logic_vector(bdi(00 to 31)),
+	               dib   => std_logic_vector(bdi(32 to 63)),
+	               dipa  => std_logic_vector(bdi(64 to 67)),
+	               dipb  => std_logic_vector(bdi(68 to 71)),
+                  doa   => bdo(00 to 31),
+                  dob   => bdo(32 to 63),
+                  dopa  => bdo(64 to 67),
+                  dopb  => bdo(68 to 71),
+	               ena   => '1',
+	               enb   => '1',
+	               wea   => wea,
+	               web   => web
+	               );
+                  
+
+abst_scan_out  <= abst_scan_in;
+time_scan_out  <= time_scan_in;
+repr_scan_out  <= repr_scan_in;
+
+bo_pc_failout <= '0';
+bo_pc_diagloop <= '0';
+
+unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0
+                     & scan_dis_dc_b & scan_diag_dc & ccflush_dc
+                     & clkoff_dc_b & d_mode_dc & mpw1_dc_b & mpw2_dc_b
+                     & delay_lclkr_dc & abist_di
+                     & abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
+                     & wr_abst_act & rd0_abst_act
+                     & tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
+                     & abist_raw_dc_b & obs0_abist_cmp & rd0_act & tidn
+                     & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
+                     & pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
+                     & tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
+                     & tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
+
+
+end generate;
+
+end architecture tri_64x72_1r1w;
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats.vhdl

@@ -0,0 +1,122 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;    use ieee.std_logic_1164.all;
+                 use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri;     use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_aoi22_nlats is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ; 
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "NLL0001_X2_A12TH" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        LCLK     : in    clk_logic; 
+        D1CLK    : in    std_ulogic; 
+        D2CLK    : in    std_ulogic; 
+        SCANIN   : in    std_ulogic_vector(offset to offset+width-1);
+        SCANOUT  : out   std_ulogic_vector(offset to offset+width-1);
+        A1       : in    std_ulogic_vector(offset to offset+width-1); 
+        A2       : in    std_ulogic_vector(offset to offset+width-1); 
+        B1       : in    std_ulogic_vector(offset to offset+width-1); 
+        B2       : in    std_ulogic_vector(offset to offset+width-1); 
+        QB       : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_aoi22_nlats;
+
+architecture tri_aoi22_nlats of tri_aoi22_nlats is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal din : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= LCLK.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    din   <= (A1 and A2) or (B1 and B2) ;       
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact   <= (0 to width-1 =>     D1CLK);
+    vact_b <= (0 to width-1 => not D1CLK);
+
+    vthold_b <= (0 to width-1 => D2CLK);
+    vthold   <= (0 to width-1 => not D2CLK);
+
+    l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(LCLK.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    QB <= not int_dout;
+    SCANOUT <= zeros;
+
+    unused <= SCANIN;
+  end generate a;
+
+end tri_aoi22_nlats;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_aoi22_nlats_wlcb.vhdl

@@ -0,0 +1,133 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_aoi22_nlats_wlcb is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 ; 
+    synthclonedlatch   : string                    := "" ;
+    btr                : string                    := "NLL0001_X2_A12TH" );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    A1       : in    std_ulogic_vector(offset to offset+width-1); 
+    A2       : in    std_ulogic_vector(offset to offset+width-1); 
+    B1       : in    std_ulogic_vector(offset to offset+width-1); 
+    B2       : in    std_ulogic_vector(offset to offset+width-1); 
+    QB       : out   std_ulogic_vector(offset to offset+width-1));
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_aoi22_nlats_wlcb;
+
+architecture tri_aoi22_nlats_wlcb of tri_aoi22_nlats_wlcb is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din, din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    din   <= (A1 and A2) or (B1 and B2) ;       
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v);
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    QB <= not int_dout;
+
+    scout <= zeros;
+
+    unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_aoi22_nlats_wlcb;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_bht.vhdl

@@ -0,0 +1,501 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+use ibm.std_ulogic_unsigned.all;
+
+library support;
+use support.power_logic_pkg.all;
+
+library tri;
+use tri.tri_latches_pkg.all;
+
+
+entity tri_bht is
+generic(expand_type : integer := 1 ); 
+port(
+     gnd                        : inout power_logic;
+     vdd                        : inout power_logic;
+     vcs                        : inout power_logic;
+
+     nclk                       : in  clk_logic; 
+     pc_iu_func_sl_thold_2      : in  std_ulogic;
+     pc_iu_sg_2                 : in  std_ulogic;
+     pc_iu_time_sl_thold_2      : in  std_ulogic;
+     pc_iu_abst_sl_thold_2      : in  std_ulogic;
+     pc_iu_ary_nsl_thold_2      : in  std_ulogic;
+     pc_iu_repr_sl_thold_2      : in  std_ulogic;
+     pc_iu_bolt_sl_thold_2      : in  std_ulogic;
+     tc_ac_ccflush_dc           : in  std_ulogic;
+     tc_ac_scan_dis_dc_b        : in  std_ulogic;
+     clkoff_b                   : in  std_ulogic;
+     scan_diag_dc               : in  std_ulogic;
+     act_dis                    : in  std_ulogic;
+     d_mode                     : in  std_ulogic;
+     delay_lclkr                : in  std_ulogic;
+     mpw1_b                     : in  std_ulogic;
+     mpw2_b                     : in  std_ulogic;
+     g8t_clkoff_b               : in  std_ulogic;
+     g8t_d_mode                 : in  std_ulogic;
+     g8t_delay_lclkr            : in  std_ulogic_vector(0 to 4);
+     g8t_mpw1_b                 : in  std_ulogic_vector(0 to 4);
+     g8t_mpw2_b                 : in  std_ulogic;
+     func_scan_in               : in  std_ulogic;
+     time_scan_in               : in  std_ulogic;
+     abst_scan_in               : in  std_ulogic;
+     repr_scan_in               : in  std_ulogic;
+     func_scan_out              : out std_ulogic;
+     time_scan_out              : out std_ulogic;
+     abst_scan_out              : out std_ulogic;
+     repr_scan_out              : out std_ulogic;
+
+     pc_iu_abist_di_0           : in  std_ulogic_vector(0 to 3);
+     pc_iu_abist_g8t_bw_1       : in  std_ulogic;
+     pc_iu_abist_g8t_bw_0       : in  std_ulogic;
+     pc_iu_abist_waddr_0        : in  std_ulogic_vector(3 to 9);
+     pc_iu_abist_g8t_wenb       : in  std_ulogic;
+     pc_iu_abist_raddr_0        : in  std_ulogic_vector(3 to 9);
+     pc_iu_abist_g8t1p_renb_0   : in  std_ulogic;
+     an_ac_lbist_ary_wrt_thru_dc: in  std_ulogic;
+     pc_iu_abist_ena_dc         : in  std_ulogic;
+     pc_iu_abist_wl128_comp_ena : in  std_ulogic;
+     pc_iu_abist_raw_dc_b       : in  std_ulogic;
+     pc_iu_abist_g8t_dcomp      : in  std_ulogic_vector(0 to 3);
+
+     pc_iu_bo_enable_2          : in  std_ulogic; 
+     pc_iu_bo_reset             : in  std_ulogic; 
+     pc_iu_bo_unload            : in  std_ulogic; 
+     pc_iu_bo_repair            : in  std_ulogic; 
+     pc_iu_bo_shdata            : in  std_ulogic; 
+     pc_iu_bo_select            : in  std_ulogic; 
+     iu_pc_bo_fail              : out std_ulogic; 
+     iu_pc_bo_diagout           : out std_ulogic;
+
+     r_act                      : in  std_ulogic;
+     w_act                      : in  std_ulogic_vector(0 to 3);
+     r_addr                     : in  std_ulogic_vector(0 to 7);
+     w_addr                     : in  std_ulogic_vector(0 to 7);
+     data_in                    : in  std_ulogic_vector(0 to 1);
+     data_out0                  : out std_ulogic_vector(0 to 1);
+     data_out1                  : out std_ulogic_vector(0 to 1);
+     data_out2                  : out std_ulogic_vector(0 to 1);
+     data_out3                  : out std_ulogic_vector(0 to 1)
+
+);
+
+-- pragma translate_off
+
+
+-- pragma translate_on
+
+end tri_bht;
+architecture tri_bht of tri_bht is
+
+
+constant data_in_offset                 : natural := 0;
+constant w_act_offset                   : natural := data_in_offset     + 2;
+constant r_act_offset                   : natural := w_act_offset       + 4;
+constant w_addr_offset                  : natural := r_act_offset       + 1;
+constant r_addr_offset                  : natural := w_addr_offset      + 8;
+constant data_out_offset                : natural := r_addr_offset      + 8;
+constant array_offset                   : natural := data_out_offset    + 8;
+constant scan_right                     : natural := array_offset       + 1 - 1;
+
+constant INIT_MASK                      : std_ulogic_vector(0 to 1) := "10";
+
+
+signal pc_iu_func_sl_thold_1    : std_ulogic;
+signal pc_iu_func_sl_thold_0    : std_ulogic;
+signal pc_iu_func_sl_thold_0_b  : std_ulogic;
+signal pc_iu_time_sl_thold_1    : std_ulogic;
+signal pc_iu_time_sl_thold_0    : std_ulogic;
+signal pc_iu_ary_nsl_thold_1    : std_ulogic;
+signal pc_iu_ary_nsl_thold_0    : std_ulogic;
+signal pc_iu_abst_sl_thold_1    : std_ulogic;
+signal pc_iu_abst_sl_thold_0    : std_ulogic;
+signal pc_iu_repr_sl_thold_1    : std_ulogic;
+signal pc_iu_repr_sl_thold_0    : std_ulogic;
+signal pc_iu_bolt_sl_thold_1    : std_ulogic;
+signal pc_iu_bolt_sl_thold_0    : std_ulogic;
+signal pc_iu_sg_1               : std_ulogic;
+signal pc_iu_sg_0               : std_ulogic;
+signal forcee                    : std_ulogic;
+
+signal siv              : std_ulogic_vector(0 to scan_right);
+signal sov              : std_ulogic_vector(0 to scan_right);
+
+signal tiup             : std_ulogic;
+
+signal data_out_d       : std_ulogic_vector(0 to 7);
+signal data_out_q       : std_ulogic_vector(0 to 7);
+
+signal ary_w_en         : std_ulogic;
+signal ary_w_addr       : std_ulogic_vector(0 to 6);
+signal ary_w_sel        : std_ulogic_vector(0 to 15);
+signal ary_w_data       : std_ulogic_vector(0 to 15);
+
+signal ary_r_en         : std_ulogic;
+signal ary_r_addr       : std_ulogic_vector(0 to 6);
+signal ary_r_data       : std_ulogic_vector(0 to 15);
+
+signal data_out         : std_ulogic_vector(0 to 7);
+signal write_thru       : std_ulogic_vector(0 to 3);
+
+signal data_in_d        : std_ulogic_vector(0 to 1);
+signal data_in_q        : std_ulogic_vector(0 to 1);
+signal w_act_d          : std_ulogic_vector(0 to 3);
+signal w_act_q          : std_ulogic_vector(0 to 3);
+signal r_act_d          : std_ulogic;
+signal r_act_q          : std_ulogic;
+signal w_addr_d         : std_ulogic_vector(0 to 7);
+signal w_addr_q         : std_ulogic_vector(0 to 7);
+signal r_addr_d         : std_ulogic_vector(0 to 7);
+signal r_addr_q         : std_ulogic_vector(0 to 7);
+
+
+begin
+
+
+tiup    <= '1';
+
+
+data_out0(0 to 1)       <= data_out_q(0 to 1);
+data_out1(0 to 1)       <= data_out_q(2 to 3);
+data_out2(0 to 1)       <= data_out_q(4 to 5);
+data_out3(0 to 1)       <= data_out_q(6 to 7);
+
+
+ary_w_en                <= or_reduce(w_act(0 to 3)) and not ((w_addr(1 to 7) = r_addr(1 to 7)) and r_act = '1');
+
+ary_w_addr(0 to 6)      <= w_addr(1 to 7);
+
+ary_w_sel(0)            <= w_act(0) and w_addr(0) = '0';
+ary_w_sel(1)            <= w_act(0) and w_addr(0) = '0';
+ary_w_sel(2)            <= w_act(1) and w_addr(0) = '0';
+ary_w_sel(3)            <= w_act(1) and w_addr(0) = '0';
+ary_w_sel(4)            <= w_act(2) and w_addr(0) = '0';
+ary_w_sel(5)            <= w_act(2) and w_addr(0) = '0';
+ary_w_sel(6)            <= w_act(3) and w_addr(0) = '0';
+ary_w_sel(7)            <= w_act(3) and w_addr(0) = '0';
+ary_w_sel(8)            <= w_act(0) and w_addr(0) = '1';
+ary_w_sel(9)            <= w_act(0) and w_addr(0) = '1';
+ary_w_sel(10)           <= w_act(1) and w_addr(0) = '1';
+ary_w_sel(11)           <= w_act(1) and w_addr(0) = '1';
+ary_w_sel(12)           <= w_act(2) and w_addr(0) = '1';
+ary_w_sel(13)           <= w_act(2) and w_addr(0) = '1';
+ary_w_sel(14)           <= w_act(3) and w_addr(0) = '1';
+ary_w_sel(15)           <= w_act(3) and w_addr(0) = '1';
+
+ary_w_data(0 to 15)     <= (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
+                           (data_in(0 to 1) xor INIT_MASK(0 to 1)) ;
+
+ary_r_en                <= r_act;
+
+ary_r_addr(0 to 6)      <= r_addr(1 to 7);
+
+data_out(0 to 7)        <= gate(ary_r_data(0 to 7)  xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '0') or
+                           gate(ary_r_data(8 to 15) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '1') ;
+
+
+data_in_d(0 to 1)       <= data_in(0 to 1);
+w_act_d(0 to 3)         <= w_act(0 to 3);
+r_act_d                 <= r_act;
+w_addr_d(0 to 7)        <= w_addr(0 to 7);
+r_addr_d(0 to 7)        <= r_addr(0 to 7);
+
+write_thru(0 to 3)      <= w_act_q(0 to 3) when (w_addr_q(0 to 7) = r_addr_q(0 to 7)) and r_act_q = '1' else "0000";
+
+data_out_d(0 to 1)      <= data_in_q(0 to 1) when write_thru(0) = '1' else
+                           data_out(0 to 1);
+data_out_d(2 to 3)      <= data_in_q(0 to 1) when write_thru(1) = '1' else
+                           data_out(2 to 3);
+data_out_d(4 to 5)      <= data_in_q(0 to 1) when write_thru(2) = '1' else
+                           data_out(4 to 5);
+data_out_d(6 to 7)      <= data_in_q(0 to 1) when write_thru(3) = '1' else
+                           data_out(6 to 7);
+
+
+bht0: entity tri.tri_128x16_1r1w_1
+  generic map ( expand_type => expand_type )
+  port map(
+           gnd                          => gnd,
+           vdd                          => vdd,
+           vcs                          => vcs,
+           nclk                         => nclk,
+
+           rd_act                       => ary_r_en,              
+           wr_act                       => ary_w_en,		    
+
+           lcb_d_mode_dc                => g8t_d_mode,           
+           lcb_clkoff_dc_b              => g8t_clkoff_b,      
+           lcb_mpw1_dc_b                => g8t_mpw1_b, 
+           lcb_mpw2_dc_b                => g8t_mpw2_b,                  
+           lcb_delay_lclkr_dc           => g8t_delay_lclkr,
+           ccflush_dc                   => tc_ac_ccflush_dc,
+           scan_dis_dc_b                => tc_ac_scan_dis_dc_b,
+           scan_diag_dc                 => scan_diag_dc,
+           func_scan_in                 => siv(array_offset),
+           func_scan_out                => sov(array_offset),
+
+           lcb_sg_0                     => pc_iu_sg_0,                      
+           lcb_sl_thold_0_b             => pc_iu_func_sl_thold_0_b,     
+           lcb_time_sl_thold_0          => pc_iu_time_sl_thold_0,
+           lcb_abst_sl_thold_0          => pc_iu_abst_sl_thold_0,
+           lcb_ary_nsl_thold_0          => pc_iu_ary_nsl_thold_0,
+           lcb_repr_sl_thold_0          => pc_iu_repr_sl_thold_0,
+           time_scan_in                 => time_scan_in,
+           time_scan_out                => time_scan_out,
+           abst_scan_in                 => abst_scan_in,
+           abst_scan_out                => abst_scan_out,
+           repr_scan_in                 => repr_scan_in,
+           repr_scan_out                => repr_scan_out,
+
+           abist_di                     => pc_iu_abist_di_0,
+           abist_bw_odd                 => pc_iu_abist_g8t_bw_1,
+           abist_bw_even                => pc_iu_abist_g8t_bw_0,
+           abist_wr_adr                 => pc_iu_abist_waddr_0,
+           wr_abst_act                  => pc_iu_abist_g8t_wenb,
+           abist_rd0_adr                => pc_iu_abist_raddr_0,
+           rd0_abst_act                 => pc_iu_abist_g8t1p_renb_0,
+           tc_lbist_ary_wrt_thru_dc     => an_ac_lbist_ary_wrt_thru_dc,
+           abist_ena_1                  => pc_iu_abist_ena_dc,        
+           abist_g8t_rd0_comp_ena       => pc_iu_abist_wl128_comp_ena,
+           abist_raw_dc_b               => pc_iu_abist_raw_dc_b,
+           obs0_abist_cmp               => pc_iu_abist_g8t_dcomp,
+
+           lcb_bolt_sl_thold_0          => pc_iu_bolt_sl_thold_0,
+           pc_bo_enable_2               => pc_iu_bo_enable_2,
+           pc_bo_reset                  => pc_iu_bo_reset,
+           pc_bo_unload                 => pc_iu_bo_unload,
+           pc_bo_repair                 => pc_iu_bo_repair,
+           pc_bo_shdata                 => pc_iu_bo_shdata,
+           pc_bo_select                 => pc_iu_bo_select,
+           bo_pc_failout                => iu_pc_bo_fail,
+           bo_pc_diagloop               => iu_pc_bo_diagout,
+
+           tri_lcb_mpw1_dc_b            => mpw1_b,
+           tri_lcb_mpw2_dc_b            => mpw2_b,
+           tri_lcb_delay_lclkr_dc       => delay_lclkr,
+           tri_lcb_clkoff_dc_b          => clkoff_b,
+           tri_lcb_act_dis_dc           => act_dis,
+
+           bw                           => ary_w_sel,     
+           wr_adr                       => ary_w_addr,     
+           rd_adr                       => ary_r_addr,     
+           di                           => ary_w_data,     
+           do                           => ary_r_data
+);
+
+
+
+
+data_in_reg: tri_rlmreg_p
+generic map (width => data_in_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(data_in_offset to data_in_offset + data_in_q'length-1),
+          scout       => sov(data_in_offset to data_in_offset + data_in_q'length-1),
+          din         => data_in_d,
+          dout        => data_in_q);
+
+w_act_reg: tri_rlmreg_p
+generic map (width => w_act_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(w_act_offset to w_act_offset + w_act_q'length-1),
+          scout       => sov(w_act_offset to w_act_offset + w_act_q'length-1),
+          din         => w_act_d,
+          dout        => w_act_q);
+
+r_act_reg: tri_rlmlatch_p
+generic map (init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(r_act_offset),
+          scout       => sov(r_act_offset),
+          din         => r_act_d,
+          dout        => r_act_q);
+
+w_addr_reg: tri_rlmreg_p
+generic map (width => w_addr_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(w_addr_offset to w_addr_offset + w_addr_q'length-1),
+          scout       => sov(w_addr_offset to w_addr_offset + w_addr_q'length-1),
+          din         => w_addr_d,
+          dout        => w_addr_q);
+
+r_addr_reg: tri_rlmreg_p
+generic map (width => r_addr_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(r_addr_offset to r_addr_offset + r_addr_q'length-1),
+          scout       => sov(r_addr_offset to r_addr_offset + r_addr_q'length-1),
+          din         => r_addr_d,
+          dout        => r_addr_q);
+
+
+data_out_reg: tri_rlmreg_p
+generic map (width => data_out_q'length, init => 0, expand_type => expand_type)
+port map (vd          => vdd,
+          gd          => gnd,
+          nclk        => nclk,
+          act         => tiup,
+          thold_b     => pc_iu_func_sl_thold_0_b,
+          sg          => pc_iu_sg_0,
+          forcee       => forcee,
+          delay_lclkr => delay_lclkr,
+          mpw1_b      => mpw1_b,
+          mpw2_b      => mpw2_b,
+          d_mode      => d_mode,
+          scin        => siv(data_out_offset to data_out_offset + data_out_q'length-1),
+          scout       => sov(data_out_offset to data_out_offset + data_out_q'length-1),
+          din         => data_out_d,
+          dout        => data_out_q);
+
+
+
+perv_2to1_reg: tri_plat
+  generic map (width => 7, expand_type => expand_type)
+  port map (vd          => vdd,
+            gd          => gnd,
+            nclk        => nclk,
+            flush       => tc_ac_ccflush_dc,
+            din(0)      => pc_iu_func_sl_thold_2,
+            din(1)      => pc_iu_sg_2,
+            din(2)      => pc_iu_time_sl_thold_2,
+            din(3)      => pc_iu_abst_sl_thold_2,
+            din(4)      => pc_iu_ary_nsl_thold_2,
+            din(5)      => pc_iu_repr_sl_thold_2,
+            din(6)      => pc_iu_bolt_sl_thold_2,
+            q(0)        => pc_iu_func_sl_thold_1,
+            q(1)        => pc_iu_sg_1,
+            q(2)        => pc_iu_time_sl_thold_1,
+            q(3)        => pc_iu_abst_sl_thold_1,
+            q(4)        => pc_iu_ary_nsl_thold_1,
+            q(5)        => pc_iu_repr_sl_thold_1,
+            q(6)        => pc_iu_bolt_sl_thold_1
+);
+
+perv_1to0_reg: tri_plat
+  generic map (width => 7, expand_type => expand_type)
+  port map (vd          => vdd,
+            gd          => gnd,
+            nclk        => nclk,
+            flush       => tc_ac_ccflush_dc,
+            din(0)      => pc_iu_func_sl_thold_1,
+            din(1)      => pc_iu_sg_1,
+            din(2)      => pc_iu_time_sl_thold_1,
+            din(3)      => pc_iu_abst_sl_thold_1,
+            din(4)      => pc_iu_ary_nsl_thold_1,
+            din(5)      => pc_iu_repr_sl_thold_1,
+            din(6)      => pc_iu_bolt_sl_thold_1,
+            q(0)        => pc_iu_func_sl_thold_0,
+            q(1)        => pc_iu_sg_0,
+            q(2)        => pc_iu_time_sl_thold_0,
+            q(3)        => pc_iu_abst_sl_thold_0,
+            q(4)        => pc_iu_ary_nsl_thold_0,
+            q(5)        => pc_iu_repr_sl_thold_0,
+            q(6)        => pc_iu_bolt_sl_thold_0
+);
+
+perv_lcbor: tri_lcbor
+  generic map (expand_type => expand_type)
+  port map (clkoff_b    => clkoff_b,
+            thold       => pc_iu_func_sl_thold_0,
+            sg          => pc_iu_sg_0,
+            act_dis     => act_dis,
+            forcee       => forcee,
+            thold_b     => pc_iu_func_sl_thold_0_b);
+
+
+
+siv(0 to scan_right)    <= func_scan_in & sov(0 to scan_right-1);
+func_scan_out           <= sov(scan_right);
+
+
+end tri_bht;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_boltreg_p.vhdl

@@ -0,0 +1,191 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+library ibm; 
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_boltreg_p is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    din     : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    dout    : out std_ulogic_vector(offset to offset+width-1) );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_boltreg_p;
+
+architecture tri_boltreg_p of tri_boltreg_p is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+    component c_rlmreg_p
+      generic ( width    : positive  := 4 ;          
+            init     : std_ulogic_vector := "0"; 
+            dualscan : string := ""              
+          );
+    port (
+         nclk        : in  std_ulogic;        
+         act         : in  std_ulogic;        
+         thold_b     : in  std_ulogic;        
+         sg          : in  std_ulogic;        
+         scin        : in  std_ulogic_vector(0 to width-1);  
+         din         : in  std_ulogic_vector(0 to width-1);  
+         dout        : out std_ulogic_vector(0 to width-1);  
+         scout       : out std_ulogic_vector(0 to width-1)   
+       );
+    end component;
+    signal scanin_inv : std_ulogic_vector(0 to width-1);
+    signal scanout_inv : std_ulogic_vector(0 to width-1);
+    signal act_or_force : std_ulogic;
+    signal din_buf : std_ulogic_vector(0 to width-1);
+    signal dout_buf : std_ulogic_vector(0 to width-1);
+  begin
+    act_or_force <= act or forcee;
+
+    cib: 
+    if ibuf = true generate
+      din_buf  <= not din;
+      dout     <= not dout_buf;
+    end generate cib;
+    cnib: 
+    if ibuf = false generate
+      din_buf  <= din;
+      dout     <= dout_buf;
+    end generate cnib;
+
+    l:c_rlmreg_p
+      generic map (width => width, init  => init_v, dualscan => dualscan)
+      port map (
+        nclk    => nclk.clk,
+        act     => act_or_force,
+        thold_b => thold_b,
+        sg      => sg,
+        scin    => scanin_inv,
+        din     => din_buf,
+        scout   => scanout_inv,
+        dout    => dout_buf);
+
+    scanin_inv <= scin xor init_v;
+    scout <= scanout_inv xor init_v;
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    cib: if ibuf = true generate
+      int_din <= (vsreset_b and not din) or
+                 (vsreset and init_v);
+    end generate cib;
+    cnib: if ibuf = false generate
+      int_din <= (vsreset_b and din) or
+                 (vsreset and init_v);
+    end generate cnib;
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    cob: if ibuf = true generate 
+	dout <= not int_dout;
+    end generate cob;
+
+    cnob: if ibuf = false generate 
+	dout <= int_dout;
+    end generate cnob;
+
+    scout <= zeros;
+
+    unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_boltreg_p;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_caa_prism_abist.vhdl

@@ -0,0 +1,145 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee, ibm;
+use ieee.std_logic_1164.all;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+library support;
+USE support.power_logic_pkg.all;
+library tri;
+use tri.tri_latches_pkg.all;
+
+
+entity tri_caa_prism_abist is
+generic(expand_type     : integer := 1 );    
+Port   (vdd                             : INOUT power_logic;
+        gnd                             : INOUT power_logic;
+        nclk                            : In    clk_logic;
+        scan_dis_dc_b                   : In    std_ulogic;
+        lcb_clkoff_dc_b                 : In    std_ulogic;
+        lcb_mpw1_dc_b                   : In    std_ulogic;
+        lcb_mpw2_dc_b                   : In    std_ulogic;
+        lcb_delay_lclkr_dc              : In    std_ulogic;
+        lcb_delay_lclkr_np_dc           : In    std_ulogic;
+        lcb_act_dis_dc                  : In    std_ulogic;
+        lcb_d_mode_dc                   : In    std_ulogic;
+        gptr_thold                      : In    std_ulogic;
+        gptr_scan_in                    : In    std_ulogic;
+        gptr_scan_out                   : Out   std_ulogic;
+        abist_thold                     : In    std_ulogic;
+        abist_sg                        : In    std_ulogic;
+        abist_scan_in                   : In    std_ulogic;
+        abist_scan_out                  : Out   std_ulogic;
+        abist_done_in_dc                : In    std_ulogic;
+        abist_done_out_dc               : Out   std_ulogic;
+        abist_mode_dc                   : In    std_ulogic;
+        abist_start_test                : In    std_ulogic;
+        lbist_mode_dc                   : In    std_ulogic;
+        lbist_ac_mode_dc                : In    std_ulogic;
+        abist_waddr_0                   : Out   std_ulogic_vector(0 to 9);
+        abist_waddr_1                   : Out   std_ulogic_vector(0 to 9);
+        abist_grf_wenb_0                : Out   std_ulogic;      
+        abist_grf_wenb_1                : Out   std_ulogic;      
+        abist_raddr_0                   : Out   std_ulogic_vector(0 to 9);
+        abist_raddr_1                   : Out   std_ulogic_vector(0 to 9);
+        abist_grf_renb_0                : Out   std_ulogic;
+        abist_grf_renb_1                : Out   std_ulogic;
+        abist_g8t_wenb                  : Out   std_ulogic;
+        abist_g8t1p_renb_0              : Out   std_ulogic;
+        abist_g6t_r_wb                  : Out   std_ulogic;
+        abist_di_g6t_2r                 : Out   std_ulogic_vector(0 to 3);
+        abist_di_0                      : Out   std_ulogic_vector(0 to 3);
+        abist_di_1                      : Out   std_ulogic_vector(0 to 3);
+        abist_dcomp                     : Out   std_ulogic_vector(0 to 3);
+        abist_dcomp_g6t_2r              : Out   std_ulogic_vector(0 to 3);
+        abist_bw_0                      : Out   std_ulogic;
+        abist_bw_1                      : Out   std_ulogic;
+        abist_wl32_g8t_comp_ena         : Out   std_ulogic;
+        abist_wl64_g8t_comp_ena         : Out   std_ulogic;
+        abist_wl128_g8t_comp_ena        : Out   std_ulogic;
+        abist_wl144_comp_ena            : Out   std_ulogic;
+        abist_wl256_comp_ena            : Out   std_ulogic;
+        abist_wl512_comp_ena            : Out   std_ulogic;
+        abist_ena_dc                    : Out   std_ulogic;
+        abist_raw_dc_b                  : Out   std_ulogic
+);
+
+-- synopsys translate_off
+
+
+
+
+-- synopsys translate_on
+end entity tri_caa_prism_abist;
+
+architecture tri_caa_prism_abist of tri_caa_prism_abist is
+
+signal unused             : std_ulogic;
+-- synopsys translate_off
+-- synopsys translate_on
+
+begin
+
+        gptr_scan_out                   <= '0';
+        abist_scan_out                  <= '0';
+        abist_done_out_dc               <= '0';
+        abist_waddr_0                   <= "0000000000";
+        abist_waddr_1                   <= "0000000000";
+        abist_grf_wenb_0                <= '0';      
+        abist_grf_wenb_1                <= '0';      
+        abist_raddr_0                   <= "0000000000";
+        abist_raddr_1                   <= "0000000000";
+        abist_grf_renb_0                <= '0';
+        abist_grf_renb_1                <= '0';
+        abist_g8t_wenb                  <= '0';
+        abist_g8t1p_renb_0              <= '0';
+        abist_g6t_r_wb                  <= '0';
+        abist_di_g6t_2r                 <= "0000";
+        abist_di_0                      <= "0000";
+        abist_di_1                      <= "0000";
+        abist_dcomp                     <= "0000";
+        abist_dcomp_g6t_2r              <= "0000";
+        abist_bw_0                      <= '0';
+        abist_bw_1                      <= '0';
+        abist_wl32_g8t_comp_ena         <= '0';
+        abist_wl64_g8t_comp_ena         <= '0';
+        abist_wl128_g8t_comp_ena        <= '0';
+        abist_wl144_comp_ena            <= '0';
+        abist_wl256_comp_ena            <= '0';
+        abist_wl512_comp_ena            <= '0';
+        abist_ena_dc                    <= '0';
+        abist_raw_dc_b                  <= '0';
+
+        unused <= or_reduce(scan_dis_dc_b & lcb_clkoff_dc_b & lcb_mpw1_dc_b & lcb_mpw2_dc_b &
+                            lcb_delay_lclkr_dc & lcb_delay_lclkr_np_dc & lcb_act_dis_dc & lcb_d_mode_dc &
+                            gptr_thold & gptr_scan_in & abist_thold & abist_sg & abist_scan_in &
+                            abist_done_in_dc & abist_mode_dc & abist_start_test &
+                            lbist_mode_dc & lbist_ac_mode_dc );
+
+end tri_caa_prism_abist;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_16x143_1r1w1c_matchline.vhdl

@@ -0,0 +1,396 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all ;
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+
+entity tri_cam_16x143_1r1w1c_matchline is
+  generic (have_xbit : integer := 1;
+             num_pgsizes : integer := 5;
+             have_cmpmask         : integer := 1;
+             cmpmask_width        : integer := 4);
+
+port( 
+    addr_in                          : in std_ulogic_vector(0 to 51);
+    addr_enable                      : in std_ulogic_vector(0 to 1);
+    comp_pgsize                      : in std_ulogic_vector(0 to 2);
+    pgsize_enable                    : in std_ulogic;
+    entry_size                       : in std_ulogic_vector(0 to 2);
+    entry_cmpmask                    : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_xbit                       : in std_ulogic;
+    entry_xbitmask                   : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_epn                        : in std_ulogic_vector(0 to 51);
+    comp_class                       : in std_ulogic_vector(0 to 1);
+    entry_class                      : in std_ulogic_vector(0 to 1);
+    class_enable                     : in std_ulogic_vector(0 to 2);
+    comp_extclass                    : in std_ulogic_vector(0 to 1);
+    entry_extclass                   : in std_ulogic_vector(0 to 1);
+    extclass_enable                  : in std_ulogic_vector(0 to 1);
+    comp_state                       : in std_ulogic_vector(0 to 1);
+    entry_hv                         : in std_ulogic;
+    entry_ds                         : in std_ulogic;
+    state_enable                     : in std_ulogic_vector(0 to 1);
+    entry_thdid                      : in std_ulogic_vector(0 to 3);
+    comp_thdid                       : in std_ulogic_vector(0 to 3);
+    thdid_enable                     : in std_ulogic_vector(0 to 1);
+    entry_pid                        : in std_ulogic_vector(0 to 7);
+    comp_pid                         : in std_ulogic_vector(0 to 7);
+    pid_enable                       : in std_ulogic;
+    entry_v                          : in std_ulogic;
+    comp_invalidate                  : in std_ulogic;
+
+    match                            : out std_ulogic
+);
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end tri_cam_16x143_1r1w1c_matchline;
+
+architecture tri_cam_16x143_1r1w1c_matchline of tri_cam_16x143_1r1w1c_matchline is
+
+
+
+  signal entry_epn_b             : std_ulogic_vector(34 to 51);
+  signal function_50_51     : std_ulogic;
+  signal function_48_51     : std_ulogic;
+  signal function_46_51     : std_ulogic;
+  signal function_44_51     : std_ulogic;
+  signal function_40_51     : std_ulogic;
+  signal function_36_51     : std_ulogic;
+  signal function_34_51     : std_ulogic;
+  signal pgsize_eq_16K  : std_ulogic;
+  signal pgsize_eq_64K  : std_ulogic;
+  signal pgsize_eq_256K : std_ulogic;
+  signal pgsize_eq_1M   : std_ulogic;
+  signal pgsize_eq_16M  : std_ulogic;
+  signal pgsize_eq_256M : std_ulogic;
+  signal pgsize_eq_1G   : std_ulogic;
+  signal pgsize_gte_16K  : std_ulogic;
+  signal pgsize_gte_64K  : std_ulogic;
+  signal pgsize_gte_256K : std_ulogic;
+  signal pgsize_gte_1M   : std_ulogic;
+  signal pgsize_gte_16M  : std_ulogic;
+  signal pgsize_gte_256M : std_ulogic;
+  signal pgsize_gte_1G   : std_ulogic;
+  signal comp_or_34_35      : std_ulogic;
+  signal comp_or_34_39      : std_ulogic;
+  signal comp_or_36_39      : std_ulogic;
+  signal comp_or_40_43      : std_ulogic;
+  signal comp_or_44_45      : std_ulogic;
+  signal comp_or_44_47      : std_ulogic;
+  signal comp_or_46_47      : std_ulogic;
+  signal comp_or_48_49      : std_ulogic;
+  signal comp_or_48_51      : std_ulogic;
+  signal comp_or_50_51      : std_ulogic;
+  signal match_line         : std_ulogic_vector(0 to 72);
+  signal pgsize_match       : std_ulogic;
+  signal addr_match         : std_ulogic;
+  signal class_match        : std_ulogic;
+  signal extclass_match     : std_ulogic;
+  signal state_match        : std_ulogic;
+  signal thdid_match        : std_ulogic;
+  signal pid_match          : std_ulogic;
+
+begin
+
+  match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor
+                             (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3))
+                            );
+
+numpgsz8 : if num_pgsizes = 8 generate
+
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask80 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) );
+  pgsize_eq_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2)));
+  pgsize_eq_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) );
+
+  pgsize_gte_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_gte_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_1G;
+  pgsize_gte_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_256M;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2))) or
+                      pgsize_gte_16M;
+  pgsize_gte_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_256K;
+  pgsize_gte_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_64K;
+
+end generate gen_nocmpmask80;
+
+gen_cmpmask80 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_256M <= not entry_cmpmask(1);
+  pgsize_gte_16M  <= not entry_cmpmask(2);
+  pgsize_gte_1M   <= not entry_cmpmask(3);
+  pgsize_gte_256K <= not entry_cmpmask(4);
+  pgsize_gte_64K  <= not entry_cmpmask(5);
+  pgsize_gte_16K  <= not entry_cmpmask(6);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_256M <= entry_xbitmask(1);
+  pgsize_eq_16M  <= entry_xbitmask(2);
+  pgsize_eq_1M   <= entry_xbitmask(3);
+  pgsize_eq_256K <= entry_xbitmask(4);
+  pgsize_eq_64K  <= entry_xbitmask(5);
+  pgsize_eq_16K  <= entry_xbitmask(6);
+end generate gen_cmpmask80;
+
+gen_noxbit80 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_36_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_46_51 <= '0';
+  function_48_51 <= '0';
+  function_50_51 <= '0';
+end generate gen_noxbit80;
+ 
+gen_xbit80 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_36_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256M) or
+                    or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_46_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256K) or
+                    or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+  function_50_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16K) or
+                    or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51));
+end generate gen_xbit80; 
+
+                    
+
+  comp_or_50_51 <=  and_reduce(match_line(50 to 51)) or pgsize_gte_16K;
+  comp_or_48_49 <=  and_reduce(match_line(48 to 49)) or pgsize_gte_64K;
+  comp_or_46_47 <=  and_reduce(match_line(46 to 47)) or pgsize_gte_256K;
+  comp_or_44_45 <=  and_reduce(match_line(44 to 45)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_36_39 <=  and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
+  comp_or_34_35 <=  and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
+
+gen_noxbit81 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit81;
+ 
+gen_xbit81 : if have_xbit /= 0 generate
+  addr_match <=    (function_50_51 and               
+                    function_48_51 and
+                    function_46_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_36_51 and
+                    function_34_51 and
+                    comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit81; 
+
+end generate numpgsz8; 
+
+
+numpgsz5 : if num_pgsizes = 5 generate
+
+  function_50_51 <= '0';
+  function_46_51 <= '0';
+  function_36_51 <= '0';
+  pgsize_eq_16K <= '0';
+  pgsize_eq_256K <= '0';
+  pgsize_eq_256M <= '0';
+  pgsize_gte_16K <= '0';
+  pgsize_gte_256K <= '0';
+  pgsize_gte_256M <= '0';
+  comp_or_34_35 <= '0';
+  comp_or_36_39 <= '0';
+  comp_or_44_45 <= '0';
+  comp_or_46_47 <= '0';
+  comp_or_48_49 <= '0';
+  comp_or_50_51 <= '0';
+  
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask50 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+  pgsize_eq_16M   <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) );
+  pgsize_eq_1M    <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2));
+  pgsize_eq_64K   <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2));
+  
+
+  pgsize_gte_1G  <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+
+  pgsize_gte_16M  <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1G;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2)) or
+                      pgsize_gte_16M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2)) or
+                      pgsize_gte_1M;
+end generate gen_nocmpmask50;
+
+gen_cmpmask50 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_16M  <= not entry_cmpmask(1);
+  pgsize_gte_1M   <= not entry_cmpmask(2);
+  pgsize_gte_64K  <= not entry_cmpmask(3);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_16M  <= entry_xbitmask(1);
+  pgsize_eq_1M   <= entry_xbitmask(2);
+  pgsize_eq_64K  <= entry_xbitmask(3);
+end generate gen_cmpmask50;
+
+gen_noxbit50 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_48_51 <= '0';
+end generate gen_noxbit50;
+ 
+gen_xbit50 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+end generate gen_xbit50;
+
+  comp_or_48_51 <=  and_reduce(match_line(48 to 51)) or pgsize_gte_64K;
+  comp_or_44_47 <=  and_reduce(match_line(44 to 47)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_34_39 <=  and_reduce(match_line(34 to 39)) or pgsize_gte_1G;
+
+gen_noxbit51 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit51;
+
+gen_xbit51 : if have_xbit /= 0 generate
+  addr_match <=    (function_48_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_34_51 and
+                    comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit51;
+
+end generate numpgsz5; 
+
+
+  pgsize_match <=   and_reduce(match_line(52 to 54)) or
+                    not(pgsize_enable);
+
+  class_match  <=  (match_line(55) or not(class_enable(0))) and 
+                    (match_line(56) or not(class_enable(1))) and 
+                    (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  extclass_match <= (match_line(57) or not(extclass_enable(0))) and  
+                     (match_line(58) or not(extclass_enable(1)));     
+
+  state_match <=    (match_line(59) or
+                     not(state_enable(0))) and
+                     (match_line(60) or
+                     not(state_enable(1)));
+
+  thdid_match <=   (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and 
+                    (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  pid_match <=      and_reduce(match_line(61 to 68)) or
+                    (not(entry_extclass(1)) and not comp_invalidate) or  
+                      not(pid_enable); 
+
+  match <=         addr_match and                       
+                    pgsize_match and                     
+                    class_match and                      
+                    extclass_match and                   
+                    state_match and                      
+                    thdid_match and                      
+                    pid_match and                        
+                    entry_v;                             
+
+end tri_cam_16x143_1r1w1c_matchline;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_32x143_1r1w1c_matchline.vhdl

@@ -0,0 +1,398 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;
+use ieee.std_logic_1164.all ;
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+
+
+entity tri_cam_32x143_1r1w1c_matchline is
+  generic (have_xbit : integer := 1;
+             num_pgsizes : integer := 5;
+             have_cmpmask         : integer := 1;
+             cmpmask_width        : integer := 4);
+
+port( 
+    addr_in                          : in std_ulogic_vector(0 to 51);
+    addr_enable                      : in std_ulogic_vector(0 to 1);
+    comp_pgsize                      : in std_ulogic_vector(0 to 2);
+    pgsize_enable                    : in std_ulogic;
+    entry_size                       : in std_ulogic_vector(0 to 2);
+    entry_cmpmask                    : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_xbit                       : in std_ulogic;
+    entry_xbitmask                   : in std_ulogic_vector(0 to cmpmask_width-1);
+    entry_epn                        : in std_ulogic_vector(0 to 51);
+    comp_class                       : in std_ulogic_vector(0 to 1);
+    entry_class                      : in std_ulogic_vector(0 to 1);
+    class_enable                     : in std_ulogic_vector(0 to 2);
+    comp_extclass                    : in std_ulogic_vector(0 to 1);
+    entry_extclass                   : in std_ulogic_vector(0 to 1);
+    extclass_enable                  : in std_ulogic_vector(0 to 1);
+    comp_state                       : in std_ulogic_vector(0 to 1);
+    entry_hv                         : in std_ulogic;
+    entry_ds                         : in std_ulogic;
+    state_enable                     : in std_ulogic_vector(0 to 1);
+    entry_thdid                      : in std_ulogic_vector(0 to 3);
+    comp_thdid                       : in std_ulogic_vector(0 to 3);
+    thdid_enable                     : in std_ulogic_vector(0 to 1);
+    entry_pid                        : in std_ulogic_vector(0 to 7);
+    comp_pid                         : in std_ulogic_vector(0 to 7);
+    pid_enable                       : in std_ulogic;
+    entry_v                          : in std_ulogic;
+    comp_invalidate                  : in std_ulogic;
+
+    match                            : out std_ulogic
+);
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end tri_cam_32x143_1r1w1c_matchline;
+
+architecture tri_cam_32x143_1r1w1c_matchline of tri_cam_32x143_1r1w1c_matchline is
+
+
+
+  signal entry_epn_b             : std_ulogic_vector(34 to 51);
+  signal function_50_51     : std_ulogic;
+  signal function_48_51     : std_ulogic;
+  signal function_46_51     : std_ulogic;
+  signal function_44_51     : std_ulogic;
+  signal function_40_51     : std_ulogic;
+  signal function_36_51     : std_ulogic;
+  signal function_34_51     : std_ulogic;
+  signal pgsize_eq_16K  : std_ulogic;
+  signal pgsize_eq_64K  : std_ulogic;
+  signal pgsize_eq_256K : std_ulogic;
+  signal pgsize_eq_1M   : std_ulogic;
+  signal pgsize_eq_16M  : std_ulogic;
+  signal pgsize_eq_256M : std_ulogic;
+  signal pgsize_eq_1G   : std_ulogic;
+  signal pgsize_gte_16K  : std_ulogic;
+  signal pgsize_gte_64K  : std_ulogic;
+  signal pgsize_gte_256K : std_ulogic;
+  signal pgsize_gte_1M   : std_ulogic;
+  signal pgsize_gte_16M  : std_ulogic;
+  signal pgsize_gte_256M : std_ulogic;
+  signal pgsize_gte_1G   : std_ulogic;
+  signal comp_or_34_35      : std_ulogic;
+  signal comp_or_34_39      : std_ulogic;
+  signal comp_or_36_39      : std_ulogic;
+  signal comp_or_40_43      : std_ulogic;
+  signal comp_or_44_45      : std_ulogic;
+  signal comp_or_44_47      : std_ulogic;
+  signal comp_or_46_47      : std_ulogic;
+  signal comp_or_48_49      : std_ulogic;
+  signal comp_or_48_51      : std_ulogic;
+  signal comp_or_50_51      : std_ulogic;
+  signal match_line         : std_ulogic_vector(0 to 72);
+  signal pgsize_match       : std_ulogic;
+  signal addr_match         : std_ulogic;
+  signal class_match        : std_ulogic;
+  signal extclass_match     : std_ulogic;
+  signal state_match        : std_ulogic;
+  signal thdid_match        : std_ulogic;
+  signal pid_match          : std_ulogic;
+
+begin
+
+  match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor
+                             (addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3))
+                            );
+
+numpgsz8 : if num_pgsizes = 8 generate
+
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask80 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) );
+  pgsize_eq_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2)));
+  pgsize_eq_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) );
+  pgsize_eq_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2)));
+  pgsize_eq_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) );
+
+  pgsize_gte_1G   <= (    entry_size(0)  and     entry_size(1)  and     entry_size(2) );
+  pgsize_gte_256M <= (    entry_size(0)  and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_1G;
+  pgsize_gte_16M  <= (    entry_size(0)  and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_256M;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and not(entry_size(2))) or
+                      pgsize_gte_16M;
+  pgsize_gte_256K <= (not(entry_size(0)) and     entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and not(entry_size(2))) or
+                      pgsize_gte_256K;
+  pgsize_gte_16K  <= (not(entry_size(0)) and not(entry_size(1)) and     entry_size(2) ) or
+                      pgsize_gte_64K;
+
+
+end generate gen_nocmpmask80;
+
+gen_cmpmask80 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_256M <= not entry_cmpmask(1);
+  pgsize_gte_16M  <= not entry_cmpmask(2);
+  pgsize_gte_1M   <= not entry_cmpmask(3);
+  pgsize_gte_256K <= not entry_cmpmask(4);
+  pgsize_gte_64K  <= not entry_cmpmask(5);
+  pgsize_gte_16K  <= not entry_cmpmask(6);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_256M <= entry_xbitmask(1);
+  pgsize_eq_16M  <= entry_xbitmask(2);
+  pgsize_eq_1M   <= entry_xbitmask(3);
+  pgsize_eq_256K <= entry_xbitmask(4);
+  pgsize_eq_64K  <= entry_xbitmask(5);
+  pgsize_eq_16K  <= entry_xbitmask(6);
+end generate gen_cmpmask80;
+
+gen_noxbit80 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_36_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_46_51 <= '0';
+  function_48_51 <= '0';
+  function_50_51 <= '0';
+end generate gen_noxbit80;
+ 
+gen_xbit80 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_36_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256M) or
+                    or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_46_51 <= not(entry_xbit) or
+                    not(pgsize_eq_256K) or
+                    or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+  function_50_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16K) or
+                    or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51));
+end generate gen_xbit80; 
+                    
+
+  comp_or_50_51 <=  and_reduce(match_line(50 to 51)) or pgsize_gte_16K;
+  comp_or_48_49 <=  and_reduce(match_line(48 to 49)) or pgsize_gte_64K;
+  comp_or_46_47 <=  and_reduce(match_line(46 to 47)) or pgsize_gte_256K;
+  comp_or_44_45 <=  and_reduce(match_line(44 to 45)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_36_39 <=  and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
+  comp_or_34_35 <=  and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
+
+gen_noxbit81 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit81;
+ 
+gen_xbit81 : if have_xbit /= 0 generate
+  addr_match <=    (function_50_51 and               
+                    function_48_51 and
+                    function_46_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_36_51 and
+                    function_34_51 and
+                    comp_or_34_35  and               
+                    comp_or_36_39  and
+                    comp_or_40_43  and
+                    comp_or_44_45  and
+                    comp_or_46_47  and
+                    comp_or_48_49  and
+                    comp_or_50_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit81; 
+
+end generate numpgsz8; 
+
+
+numpgsz5 : if num_pgsizes = 5 generate
+
+  function_50_51 <= '0';
+  function_46_51 <= '0';
+  function_36_51 <= '0';
+  pgsize_eq_16K <= '0';
+  pgsize_eq_256K <= '0';
+  pgsize_eq_256M <= '0';
+  pgsize_gte_16K <= '0';
+  pgsize_gte_256K <= '0';
+  pgsize_gte_256M <= '0';
+  comp_or_34_35 <= '0';
+  comp_or_36_39 <= '0';
+  comp_or_44_45 <= '0';
+  comp_or_46_47 <= '0';
+  comp_or_48_49 <= '0';
+  comp_or_50_51 <= '0';
+  
+  entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
+
+
+gen_nocmpmask50 : if have_cmpmask = 0 generate
+  pgsize_eq_1G   <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+  pgsize_eq_16M   <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) );
+  pgsize_eq_1M    <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2));
+  pgsize_eq_64K   <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2));
+  
+
+  pgsize_gte_1G  <= (    entry_size(0)  and     entry_size(1)  and  not(entry_size(2)) );
+
+  pgsize_gte_16M  <= (    entry_size(0)  and    entry_size(1)  and     entry_size(2) ) or
+                      pgsize_gte_1G;
+  pgsize_gte_1M   <= (    entry_size(0)  and not(entry_size(1)) and   entry_size(2)) or
+                      pgsize_gte_16M;
+  pgsize_gte_64K  <= (not(entry_size(0)) and     entry_size(1)  and   entry_size(2)) or
+                      pgsize_gte_1M;
+
+end generate gen_nocmpmask50;
+
+gen_cmpmask50 : if have_cmpmask = 1 generate
+  pgsize_gte_1G   <= not entry_cmpmask(0);
+  pgsize_gte_16M  <= not entry_cmpmask(1);
+  pgsize_gte_1M   <= not entry_cmpmask(2);
+  pgsize_gte_64K  <= not entry_cmpmask(3);
+
+  pgsize_eq_1G   <= entry_xbitmask(0);
+  pgsize_eq_16M  <= entry_xbitmask(1);
+  pgsize_eq_1M   <= entry_xbitmask(2);
+  pgsize_eq_64K  <= entry_xbitmask(3);
+end generate gen_cmpmask50;
+
+gen_noxbit50 : if have_xbit = 0 generate
+  function_34_51 <= '0';
+  function_40_51 <= '0';
+  function_44_51 <= '0';
+  function_48_51 <= '0';
+end generate gen_noxbit50;
+ 
+gen_xbit50 : if have_xbit /= 0 generate
+  function_34_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1G) or
+                    or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
+  function_40_51 <= not(entry_xbit) or
+                    not(pgsize_eq_16M) or
+                    or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
+  function_44_51 <= not(entry_xbit) or
+                    not(pgsize_eq_1M) or
+                    or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
+  function_48_51 <= not(entry_xbit) or
+                    not(pgsize_eq_64K) or
+                    or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
+end generate gen_xbit50;
+
+  comp_or_48_51 <=  and_reduce(match_line(48 to 51)) or pgsize_gte_64K;
+  comp_or_44_47 <=  and_reduce(match_line(44 to 47)) or pgsize_gte_1M;
+  comp_or_40_43 <=  and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
+  comp_or_34_39 <=  and_reduce(match_line(34 to 39)) or pgsize_gte_1G;
+
+gen_noxbit51 : if have_xbit = 0 generate
+  addr_match <=    (comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_noxbit51;
+
+gen_xbit51 : if have_xbit /= 0 generate
+  addr_match <=    (function_48_51 and
+                    function_44_51 and
+                    function_40_51 and
+                    function_34_51 and
+                    comp_or_34_39  and               
+                    comp_or_40_43  and
+                    comp_or_44_47  and
+                    comp_or_48_51  and
+                    and_reduce(match_line(31 to 33)) and     
+                    (and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or  
+                    not(addr_enable(0));                    
+end generate gen_xbit51;
+
+end generate numpgsz5; 
+
+
+  pgsize_match <=   and_reduce(match_line(52 to 54)) or
+                    not(pgsize_enable);
+
+  class_match  <=  (match_line(55) or not(class_enable(0))) and 
+                    (match_line(56) or not(class_enable(1))) and 
+                    (and_reduce(match_line(55 to 56)) or not(class_enable(2)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  extclass_match <= (match_line(57) or not(extclass_enable(0))) and  
+                     (match_line(58) or not(extclass_enable(1)));     
+
+  state_match <=    (match_line(59) or
+                     not(state_enable(0))) and
+                     (match_line(60) or
+                     not(state_enable(1)));
+
+  thdid_match <=   (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and 
+                    (and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or
+                      (not(entry_extclass(1)) and not comp_invalidate));   
+
+  pid_match <=      and_reduce(match_line(61 to 68)) or
+                    (not(entry_extclass(1)) and not comp_invalidate) or  
+                      not(pid_enable); 
+
+  match <=         addr_match and                       
+                    pgsize_match and                     
+                    class_match and                      
+                    extclass_match and                   
+                    state_match and                      
+                    thdid_match and                      
+                    pid_match and                        
+                    entry_v;                             
+
+
+end tri_cam_32x143_1r1w1c_matchline;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_cam_parerr_mac.vhdl

@@ -0,0 +1,178 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;
+use ieee.std_logic_1164.all;
+library ibm;
+use ibm.std_ulogic_unsigned.all;
+use ibm.std_ulogic_function_support.all;
+library support;
+use support.power_logic_pkg.all;
+library tri;
+use tri.tri_latches_pkg.all;
+
+entity tri_cam_parerr_mac  is
+  generic (expand_type : integer := 1);
+  port(
+
+   np1_cam_cmp_data             :in  std_ulogic_vector(0 to 83);
+   np1_array_cmp_data           :in  std_ulogic_vector(0 to 67);
+
+   np2_cam_cmp_data             :out std_ulogic_vector(0 to 83);
+   np2_array_cmp_data           :out std_ulogic_vector(0 to 67);
+   np2_cmp_data_parerr_epn      :out std_ulogic; 
+   np2_cmp_data_parerr_rpn      :out std_ulogic;
+
+   gnd                          :inout power_logic;
+   vdd                          :inout power_logic;
+   nclk                         :in  clk_logic;
+   act                          :in  std_ulogic;
+   lcb_act_dis_dc               :in  std_ulogic;
+   lcb_delay_lclkr_dc           :in  std_ulogic;
+   lcb_clkoff_dc_b_0            :in  std_ulogic;
+   lcb_mpw1_dc_b                :in  std_ulogic;
+   lcb_mpw2_dc_b                :in  std_ulogic;
+   lcb_sg_0                     :in  std_ulogic;
+   lcb_func_sl_thold_0          :in  std_ulogic; 
+   func_scan_in                 :in  std_ulogic;
+   func_scan_out                :out std_ulogic
+  );
+-- synopsys translate_off
+-- synopsys translate_on
+end entity tri_cam_parerr_mac;
+
+architecture tri_cam_parerr_mac of tri_cam_parerr_mac is
+
+begin
+
+  um: if expand_type = 0 generate
+      signal np2_cam_cmp_data_q         :std_ulogic_vector(0 to np1_cam_cmp_data'length-1);
+      signal np2_array_cmp_data_q       :std_ulogic_vector(0 to np1_array_cmp_data'length-1);
+      signal np2_cmp_data_calc_par      :std_ulogic_vector(50 to 67);
+
+  begin
+      np1_cam_cmp_data_latch: tri_rlmreg_p
+        generic map (width => np1_cam_cmp_data'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => np1_cam_cmp_data,
+                  dout        => np2_cam_cmp_data_q);
+
+      np1_array_cmp_data_latch: tri_rlmreg_p
+        generic map (width => np1_array_cmp_data'length, init => 0, expand_type => expand_type)
+        port map (nclk        => nclk,
+                  act         => act,
+                  scin        => (others => '0'),
+                  scout       => open,
+                  din         => np1_array_cmp_data,
+                  dout        => np2_array_cmp_data_q);
+
+      np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82));
+      np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7));
+      np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15));
+      np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23));
+      np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31));
+      np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39));
+      np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47));
+      np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55));
+      np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62));
+      np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66));
+      np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74));
+      np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5));
+      np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13));
+      np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21));
+      np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29));
+      np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37));
+      np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44));
+      np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50));
+
+      np2_cmp_data_parerr_epn   <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60)));
+      np2_cmp_data_parerr_rpn   <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67));
+      np2_cam_cmp_data          <= np2_cam_cmp_data_q;
+      np2_array_cmp_data        <= np2_array_cmp_data_q;
+  end generate um;
+
+  a: if expand_type = 1 generate
+      signal np2_cam_cmp_data_q         :std_ulogic_vector(0 to np1_cam_cmp_data'length-1);
+      signal np2_array_cmp_data_q       :std_ulogic_vector(0 to np1_array_cmp_data'length-1);
+      signal np2_cmp_data_calc_par      :std_ulogic_vector(50 to 67);
+      signal clk                        :std_ulogic;
+      signal sreset_q                   :std_ulogic;
+  begin
+     clk   <= not nclk.clk;
+     rlatch: process (clk)
+     begin
+       if(rising_edge(clk)) then
+         sreset_q             <= nclk.sreset;
+       end if;
+     end process;
+
+     slatch: process (nclk,sreset_q)
+     begin
+       if(rising_edge(nclk.clk)) then
+         if (sreset_q = '1') then
+           np2_cam_cmp_data_q   <= (others=>'0');
+           np2_array_cmp_data_q <= (others=>'0');
+         else
+           np2_cam_cmp_data_q   <= np1_cam_cmp_data;
+           np2_array_cmp_data_q <= np1_array_cmp_data;
+         end if;
+       end if;
+     end process;
+
+     np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82));
+     np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7));
+     np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15));
+     np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23));
+     np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31));
+     np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39));
+     np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47));
+     np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55));
+     np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62));
+     np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66));
+     np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74));
+     np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5));
+     np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13));
+     np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21));
+     np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29));
+     np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37));
+     np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44));
+     np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50));
+
+     np2_cmp_data_parerr_epn   <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60)));
+     np2_cmp_data_parerr_rpn   <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67));
+     np2_cam_cmp_data          <= np2_cam_cmp_data_q;
+     np2_array_cmp_data        <= np2_array_cmp_data_q;
+
+     func_scan_out <= func_scan_in;
+  end generate a;
+
+end tri_cam_parerr_mac;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_direct_err_rpt.vhdl

@@ -0,0 +1,66 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support;                  use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_direct_err_rpt is
+
+  generic (
+      width         : positive := 1 ;      
+      expand_type   : integer  := 1 );     
+  port (
+      vd            : inout power_logic;
+      gd            : inout power_logic;
+
+      err_in        : in  std_ulogic_vector(0 to width-1);
+      err_out       : out std_ulogic_vector(0 to width-1)
+  );
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end tri_direct_err_rpt;
+
+architecture tri_direct_err_rpt of tri_direct_err_rpt is
+
+begin  
+
+  a: if expand_type /= 2 generate
+  begin
+    err_out <= err_in;
+  end generate a;
+
+end tri_direct_err_rpt;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_err_rpt.vhdl

@@ -0,0 +1,132 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_err_rpt is
+
+  generic (
+      width        : positive := 1;               
+      mask_reset_value : std_ulogic_vector := "0";
+      inline       : boolean := false;            
+      share_mask   : boolean := false;            
+      use_nlats    : boolean := false;            
+      needs_sreset : integer := 1 ;        
+      expand_type  : integer := 1 );       
+
+  port (
+      vd            : inout power_logic;
+      gd            : inout power_logic;
+      err_d1clk     : in  std_ulogic;           
+      err_d2clk     : in  std_ulogic;
+      err_lclk      : in  clk_logic;
+      err_scan_in   : in  std_ulogic_vector(0 to width-1);
+      err_scan_out  : out std_ulogic_vector(0 to width-1);
+      mode_dclk     : in  std_ulogic;
+      mode_lclk     : in  clk_logic;
+      mode_scan_in  : in  std_ulogic_vector(0 to width-1);
+      mode_scan_out : out std_ulogic_vector(0 to width-1);
+
+      err_in        : in  std_ulogic_vector(0 to width-1);
+      err_out       : out std_ulogic_vector(0 to width-1);
+
+      hold_out      : out std_ulogic_vector(0 to width-1); 
+      mask_out      : out std_ulogic_vector(0 to width-1)
+  );
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end tri_err_rpt;
+
+architecture tri_err_rpt of tri_err_rpt is
+
+begin  
+
+  a: if expand_type /= 2 generate
+    constant mask_initv : std_ulogic_vector(0 to (mask_reset_value'length + width-1)):=mask_reset_value & (0 to width-1=>'0');
+    signal hold_in      : std_ulogic_vector(0 to width-1);
+    signal hold_lt      : std_ulogic_vector(0 to width-1);
+    signal mask_lt      : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    hold_in  <= err_in or hold_lt;
+
+    hold: entity tri.tri_nlat_scan
+    generic map( width => width,
+                 needs_sreset => needs_sreset,
+                 expand_type => expand_type )
+    port map
+     ( vd        => vd,
+       gd        => gd,
+       d1clk     => err_d1clk,
+       d2clk     => err_d2clk,
+       lclk      => err_lclk,
+       scan_in   => err_scan_in(0 to width-1),
+       scan_out  => err_scan_out(0 to width-1),
+       din       => hold_in,
+       q         => hold_lt,
+       q_b       => open
+     );
+
+    m: if (share_mask = false) generate
+        mask_lt <= mask_initv(0 to width-1);
+    end generate m;
+    sm: if (share_mask = true) generate
+        mask_lt <= (others => mask_initv(0));
+    end generate sm;
+
+    mode_scan_out <= (others => '0');
+
+    hold_out <= hold_lt;
+    mask_out <= mask_lt;
+
+    inline_hold: if (inline = true) generate
+        err_out <= hold_lt and not mask_lt;
+    end generate inline_hold;
+
+    side_hold: if (inline = false) generate
+        err_out <= err_in and not mask_lt;
+    end generate side_hold;
+
+    unused(0) <= mode_dclk;
+    unused(1 to width) <= mode_scan_in;
+  end generate a;
+
+end tri_err_rpt;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats.vhdl

@@ -0,0 +1,119 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;    use ieee.std_logic_1164.all;
+                 use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri;     use tri.tri_latches_pkg.all;
+
+entity tri_inv_nlats is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ; 
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "NLI0001_X1_A12TH" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        LCLK     : in    clk_logic; 
+        D1CLK    : in    std_ulogic; 
+        D2CLK    : in    std_ulogic; 
+        SCANIN   : in    std_ulogic_vector(offset to offset+width-1);
+        SCANOUT  : out   std_ulogic_vector(offset to offset+width-1);
+        D        : in    std_ulogic_vector(offset to offset+width-1); 
+        QB       : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_inv_nlats;
+
+architecture tri_inv_nlats of tri_inv_nlats is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal din : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= LCLK.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    din   <= D ;       
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact   <= (0 to width-1 =>     D1CLK);
+    vact_b <= (0 to width-1 => not D1CLK);
+
+    vthold_b <= (0 to width-1 => D2CLK);
+    vthold   <= (0 to width-1 => not D2CLK);
+
+    l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(LCLK.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    QB <= not int_dout;
+    SCANOUT <= zeros;
+
+    unused <= SCANIN;
+  end generate a;
+
+
+
+end tri_inv_nlats;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_inv_nlats_wlcb.vhdl

@@ -0,0 +1,128 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_inv_nlats_wlcb is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 ; 
+    synthclonedlatch   : string                    := "" ;
+    btr                : string                    := "NLI0001_X2_A12TH" );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    D        : in    std_ulogic_vector(offset to offset+width-1); 
+    QB       : out   std_ulogic_vector(offset to offset+width-1));
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_inv_nlats_wlcb;
+
+architecture tri_inv_nlats_wlcb of tri_inv_nlats_wlcb is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din, din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    din   <= D;       
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v);
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    QB <= not int_dout;
+
+    scout <= zeros;
+
+    unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_inv_nlats_wlcb;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_latches_pkg.vhdl

@@ -0,0 +1,511 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+LIBRARY ieee; USE ieee.std_logic_1164.all;
+LIBRARY support; USE support.power_logic_pkg.all;
+
+PACKAGE tri_latches_pkg IS
+
+  type clk_logic is record
+    clk         : std_ulogic;
+    sreset      : std_ulogic;
+    clk2x       : std_ulogic;
+    clk4x       : std_ulogic;
+  end record;
+
+  type clk_logic_vector is array ( NATURAL range <> ) of clk_logic;
+
+
+  component tri_cw_nlat
+    generic (
+            bhc:string:="";
+            ub:string:="";
+            offset : natural  range 0 to 65535 := 0;
+            width  : positive range 1 to 65536 := 1 ;
+            init   : std_ulogic_vector := "0";
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+    port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        d_b      : in    std_ulogic_vector(0 to width-1);
+        scan_in  : in    std_ulogic_vector(0 to width-1);
+        d1clk    : in    std_ulogic;
+        d2clk    : in    std_ulogic;
+        lclk     : in    clk_logic;
+        q_b      : out   std_ulogic_vector(0 to width-1);
+        scan_out : out   std_ulogic_vector(0 to width-1)
+       );
+  end component;
+
+  component tri_direct_err_rpt
+    generic (
+      width         : positive := 1 ;      
+      expand_type   : integer  := 1 );     
+    port (
+      vd            : inout power_logic;
+      gd            : inout power_logic;
+
+      err_in        : in  std_ulogic_vector(0 to width-1);
+      err_out       : out std_ulogic_vector(0 to width-1)
+    );
+  end component;
+
+  component tri_err_rpt
+    generic (
+      width        : positive := 1;               
+      mask_reset_value : std_ulogic_vector := "0";
+      inline       : boolean := false;            
+      reset_hold   : boolean := false;            
+      needs_sreset : integer := 1 ;        
+      expand_type  : integer := 1 );       
+    port (
+      vd            : inout power_logic;
+      gd            : inout power_logic;
+      err_d1clk     : in  std_ulogic;           
+      err_d2clk     : in  std_ulogic;
+      err_lclk      : in  clk_logic;
+      err_scan_in   : in  std_ulogic_vector(0 to width-1);
+      err_scan_out  : out std_ulogic_vector(0 to width-1);
+      mode_dclk     : in  std_ulogic;
+      mode_lclk     : in  clk_logic;
+      mode_scan_in  : in  std_ulogic_vector(0 to width-1);
+      mode_scan_out : out std_ulogic_vector(0 to width-1);
+
+      err_in        : in  std_ulogic_vector(0 to width-1);
+      err_out       : out std_ulogic_vector(0 to width-1);
+
+      hold_out      : out std_ulogic_vector(0 to width-1); 
+      mask_out      : out std_ulogic_vector(0 to width-1)
+    );
+  end component;
+
+  component tri_klat
+    generic (
+            width              : positive range 1 to 65536 := 1 ;
+            offset             : natural  range 0 to 65535 := 0;
+            init               : std_ulogic_vector         := "0" ;
+            synthclonedlatch   : string                    := "" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+    port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        dclk     : in    std_ulogic;
+        lclk     : in    clk_logic;
+        din      : in    std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1)
+       );
+  end component;
+
+  component tri_lcbcntl_array_mac
+    generic ( expand_type : integer := 1 ); 
+    port (
+        vdd            : inout power_logic;
+        gnd            : inout power_logic;
+        sg             : in    std_ulogic;
+        nclk           : in    clk_logic;
+        scan_in        : in    std_ulogic;
+        scan_diag_dc   : in    std_ulogic;
+        thold          : in    std_ulogic;
+        clkoff_dc_b    : out   std_ulogic;
+        delay_lclkr_dc : out   std_ulogic_vector(0 to 4);
+        act_dis_dc     : out   std_ulogic;
+        d_mode_dc      : out   std_ulogic;
+        mpw1_dc_b      : out   std_ulogic_vector(0 to 4);
+        mpw2_dc_b      : out   std_ulogic;
+        scan_out       : out   std_ulogic
+       );
+  end component;
+
+  component tri_lcbcntl_mac
+    generic ( expand_type : integer := 1 ); 
+    port (
+        vdd            : inout power_logic;
+        gnd            : inout power_logic;
+        sg             : in    std_ulogic;
+        nclk           : in    clk_logic;
+        scan_in        : in    std_ulogic;
+        scan_diag_dc   : in    std_ulogic;
+        thold          : in    std_ulogic;
+        clkoff_dc_b    : out   std_ulogic;
+        delay_lclkr_dc : out   std_ulogic_vector(0 to 4);
+        act_dis_dc     : out   std_ulogic;
+        d_mode_dc      : out   std_ulogic;
+        mpw1_dc_b      : out   std_ulogic_vector(0 to 4);
+        mpw2_dc_b      : out   std_ulogic;
+        scan_out       : out   std_ulogic
+       );
+  end component;
+
+  component tri_lcbkd
+    generic ( expand_type : integer := 1 ); 
+    port (
+        vd          : inout power_logic;
+        gd          : inout power_logic;
+        act         : in    std_ulogic;
+        delay_lclkr : in    std_ulogic;
+        mpw1_b      : in    std_ulogic;
+        mpw2_b      : in    std_ulogic;
+        nclk        : in    clk_logic;
+        forcee       : in    std_ulogic;
+        thold_b     : in    std_ulogic;
+        dclk        : out   std_ulogic;
+        lclk        : out   clk_logic
+       );
+  end component;
+
+  component tri_lcbnd
+    generic ( expand_type : integer := 1 ); 
+    port (
+        vd          : inout power_logic;
+        gd          : inout power_logic;
+        act         : in    std_ulogic;
+        delay_lclkr : in    std_ulogic;
+        mpw1_b      : in    std_ulogic;
+        mpw2_b      : in    std_ulogic;
+        nclk        : in    clk_logic;
+        forcee       : in    std_ulogic;
+        sg          : in    std_ulogic;
+        thold_b     : in    std_ulogic;
+        d1clk       : out   std_ulogic;
+        d2clk       : out   std_ulogic;
+        lclk        : out   clk_logic
+       );
+  end component;
+
+  component tri_lcbor
+    generic ( expand_type : integer := 1 ); 
+    port (
+        clkoff_b : in    std_ulogic;
+        thold    : in    std_ulogic;
+        sg       : in    std_ulogic;
+        act_dis  : in    std_ulogic;
+        forcee    : out   std_ulogic;
+        thold_b  : out   std_ulogic
+       );
+  end component;
+
+  component tri_lcbs
+    generic ( expand_type : integer := 1 ); 
+    port (
+        vd          : inout power_logic;
+        gd          : inout power_logic;
+        delay_lclkr : in    std_ulogic;
+        nclk        : in    clk_logic;
+        forcee       : in    std_ulogic;
+        thold_b     : in    std_ulogic;
+        dclk        : out   std_ulogic;
+        lclk        : out   clk_logic
+       );
+  end component;
+
+  component tri_nlat
+    generic (
+            offset             : natural  range 0 to 65535 := 0;
+            reset_inverts_scan : boolean                   := true;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ;
+            synthclonedlatch   : string                    := "" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+    port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        d1clk    : in    std_ulogic;
+        d2clk    : in    std_ulogic;
+        lclk     : in    clk_logic;
+        scan_in  : in    std_ulogic;
+        din      : in    std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1);
+        scan_out : out   std_ulogic
+       );
+  end component;
+
+  component tri_nlat_scan
+    generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ;
+            reset_inverts_scan : boolean                   := true;
+            synthclonedlatch   : string                    := "" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+    port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        d1clk    : in    std_ulogic;
+        d2clk    : in    std_ulogic;
+        lclk     : in    clk_logic;
+        din      : in    std_ulogic_vector(offset to offset+width-1);
+        scan_in  : in    std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1);
+        scan_out : out   std_ulogic_vector(offset to offset+width-1)
+       );
+  end component;
+
+  component tri_plat
+    generic (
+      width       : positive range 1 to 65536 := 1 ;
+      offset      : natural range 0 to 65535  := 0 ;
+      init        : integer := 0;  
+      synthclonedlatch : string                    := "" ;
+      flushlat         : boolean                   := true ;
+      expand_type : integer := 1 ); 
+    port (
+      vd      : inout power_logic;
+      gd      : inout power_logic;
+      nclk    : in    clk_logic;
+      flush   : in    std_ulogic;
+      din     : in    std_ulogic_vector(offset to offset+width-1);
+      q       : out   std_ulogic_vector(offset to offset+width-1) );
+  end component;
+
+  component tri_regk
+    generic (
+      width       : integer := 4;
+      offset      : integer range 0 to 65535 := 0 ; 
+      init        : integer := 0;  
+      synthclonedlatch    : string  := "";
+      needs_sreset        : integer := 1 ;                  
+      expand_type : integer := 1 );
+    port (
+      vd      : inout power_logic;
+      gd      : inout power_logic;
+      nclk    : in  clk_logic;
+      act     : in  std_ulogic := '1'; 
+      forcee   : in  std_ulogic := '0'; 
+      thold_b : in  std_ulogic := '1'; 
+      d_mode  : in  std_ulogic := '0'; 
+      delay_lclkr : in  std_ulogic := '0'; 
+      mpw1_b  : in  std_ulogic := '1'; 
+      mpw2_b  : in  std_ulogic := '1'; 
+      din     : in  std_ulogic_vector(offset to offset+width-1);  
+      dout    : out std_ulogic_vector(offset to offset+width-1) );
+  end component;
+
+  component tri_regs
+    generic (
+      width       : integer := 4;
+      offset      : integer range 0 to 65535 := 0 ; 
+      init        : integer := 0;  
+      ibuf        : boolean := false;       
+      dualscan    : string  := ""; 
+      needs_sreset        : integer := 1 ;                  
+      expand_type : integer := 1 );
+    port (
+      vd      : inout power_logic;
+      gd      : inout power_logic;
+      nclk    : in  clk_logic;
+      forcee   : in  std_ulogic := '0'; 
+      thold_b : in  std_ulogic := '1'; 
+      delay_lclkr : in  std_ulogic := '0'; 
+      scin    : in  std_ulogic_vector(offset to offset+width-1);  
+      scout   : out std_ulogic_vector(offset to offset+width-1);
+      dout    : out std_ulogic_vector(offset to offset+width-1) );
+  end component;
+
+  component tri_rlmlatch_p
+    generic (
+      init        : integer := 0;  
+      ibuf        : boolean := false;       
+      dualscan    : string  := ""; 
+      needs_sreset: integer := 1 ; 
+      expand_type : integer := 1 );
+    port (
+      vd      : inout power_logic;
+      gd      : inout power_logic;
+      nclk    : in  clk_logic;
+      act     : in  std_ulogic := '1'; 
+      forcee   : in  std_ulogic := '0'; 
+      thold_b : in  std_ulogic := '1'; 
+      d_mode  : in  std_ulogic := '0'; 
+      sg      : in  std_ulogic := '0'; 
+      delay_lclkr : in  std_ulogic := '0'; 
+      mpw1_b  : in  std_ulogic := '1'; 
+      mpw2_b  : in  std_ulogic := '1'; 
+      scin    : in  std_ulogic := '0'; 
+      din     : in  std_ulogic;        
+      scout   : out std_ulogic;        
+      dout    : out std_ulogic);       
+  end component;
+
+  component tri_rlmreg_p
+    generic (
+      width       : integer := 4;
+      offset      : integer range 0 to 65535 := 0 ; 
+      init        : integer := 0;  
+      ibuf        : boolean := false;       
+      dualscan    : string  := ""; 
+      needs_sreset: integer := 1 ; 
+      expand_type : integer := 1 );
+    port (
+      vd      : inout power_logic;
+      gd      : inout power_logic;
+      nclk    : in  clk_logic;
+      act     : in  std_ulogic := '1'; 
+      forcee   : in  std_ulogic := '0'; 
+      thold_b : in  std_ulogic := '1'; 
+      d_mode  : in  std_ulogic := '0'; 
+      sg      : in  std_ulogic := '0'; 
+      delay_lclkr : in  std_ulogic := '0'; 
+      mpw1_b  : in  std_ulogic := '1'; 
+      mpw2_b  : in  std_ulogic := '1'; 
+      scin    : in  std_ulogic_vector(offset to offset+width-1);  
+      din     : in  std_ulogic_vector(offset to offset+width-1);  
+      scout   : out std_ulogic_vector(offset to offset+width-1);
+      dout    : out std_ulogic_vector(offset to offset+width-1) );
+  end component;
+
+  component tri_slat
+   generic (
+    width              : positive range 1 to 65536 := 1;
+    offset             : natural range 0 to 65535  := 0;
+    init               : std_ulogic_vector         := "0";
+    synthclonedlatch   : string                    := "";
+    reset_inverts_scan : boolean                   := true;
+    expand_type        : integer                   := 1);  
+   port (
+    vd       : inout power_logic;
+    gd       : inout power_logic;
+    dclk     : in    std_ulogic;
+    lclk     : in    clk_logic;
+    scan_in  : in    std_ulogic;
+    scan_out : out   std_ulogic;
+    q        : out   std_ulogic_vector(offset to offset+width-1);
+    q_b      : out   std_ulogic_vector(offset to offset+width-1));
+  end component;
+
+  component tri_slat_lbist
+   generic (
+    width              : positive range 1 to 65536 := 1;
+    offset             : natural range 0 to 65535  := 0;
+    init               : std_ulogic_vector         := "0";
+    synthclonedlatch   : string                    := "";
+    reset_inverts_scan : boolean                   := true;
+    expand_type        : integer                   := 1);  
+   port (
+    vd       : inout power_logic;
+    gd       : inout power_logic;
+    dclk     : in    std_ulogic;
+    lclk     : in    clk_logic;
+    tc_xx_lbist_ac_mode_dc : in    std_ulogic;
+    scan_in  : in    std_ulogic;
+    scan_out : out   std_ulogic;
+    q        : out   std_ulogic_vector(offset to offset+width-1);
+    q_b      : out   std_ulogic_vector(offset to offset+width-1));
+  end component;
+
+  component tri_slat_scan
+    generic (
+            width              : positive range 1 to 65536 := 1 ;
+            offset             : natural  range 0 to 65535 := 0;
+            init               : std_ulogic_vector         := "0" ;
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "c_slat_scan" ;
+            reset_inverts_scan : boolean                   := true;
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        dclk     : in    std_ulogic;
+        lclk     : in    clk_logic;
+        scan_in  : in    std_ulogic_vector(offset to offset+width-1);
+        scan_out : out   std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1)
+       );
+  end component;
+
+  component tri_ser_rlmreg_p
+   generic (
+      width             : positive range 1 to 65536 := 1 ;
+      offset            : natural  range 0 to 65535 := 0 ;
+      init              : integer := 0;
+      ibuf              : boolean := false;
+      dualscan          : string  := "";
+      needs_sreset      : integer := 1 ;
+      expand_type       : integer := 1 );
+   port (
+      vd                : inout power_logic;
+      gd                : inout power_logic;
+      nclk              : in  clk_logic;
+      act               : in  std_ulogic := '1';
+      forcee             : in  std_ulogic := '0';
+      thold_b           : in  std_ulogic := '1';
+      d_mode            : in  std_ulogic := '0';
+      sg                : in  std_ulogic := '0';
+      delay_lclkr       : in  std_ulogic := '0';
+      mpw1_b            : in  std_ulogic := '1';
+      mpw2_b            : in  std_ulogic := '1';
+      scin              : in  std_ulogic_vector(offset to offset+width-1);
+      din               : in  std_ulogic_vector(offset to offset+width-1);
+      scout             : out std_ulogic_vector(offset to offset+width-1);
+      dout              : out std_ulogic_vector(offset to offset+width-1));
+   end component;
+
+   component tri_aoi22_nlats_wlcb
+    generic (
+      width             : integer := 4;
+      offset            : integer range 0 to 65535 := 0 ; 
+      init              : integer := 0;  
+      ibuf              : boolean := false;       
+      dualscan          : string  := ""; 
+      needs_sreset      : integer := 1 ; 
+      expand_type       : integer := 1 ; 
+      synthclonedlatch  : string                    := "" ;
+      btr               : string                    := "NLL0001_X2_A12TH" );
+   port (
+      vd                : inout power_logic;
+      gd                : inout power_logic;
+      nclk              : in  clk_logic;
+      act               : in  std_ulogic := '1'; 
+      forcee             : in  std_ulogic := '0'; 
+      thold_b           : in  std_ulogic := '1'; 
+      d_mode            : in  std_ulogic := '0'; 
+      sg                : in  std_ulogic := '0'; 
+      delay_lclkr       : in  std_ulogic := '0'; 
+      mpw1_b            : in  std_ulogic := '1'; 
+      mpw2_b            : in  std_ulogic := '1'; 
+      scin              : in  std_ulogic_vector(offset to offset+width-1);  
+      scout             : out std_ulogic_vector(offset to offset+width-1);
+      A1                : in    std_ulogic_vector(offset to offset+width-1); 
+      A2                : in    std_ulogic_vector(offset to offset+width-1); 
+      B1                : in    std_ulogic_vector(offset to offset+width-1); 
+      B2                : in    std_ulogic_vector(offset to offset+width-1); 
+      QB                : out   std_ulogic_vector(offset to offset+width-1));
+   end component;
+
+end tri_latches_pkg;
+
+package body tri_latches_pkg is
+
+end tri_latches_pkg;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_array_mac.vhdl

@@ -0,0 +1,86 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_lcbcntl_array_mac is
+
+  generic ( expand_type : integer := 1 ); 
+
+  port (
+        vdd            : inout power_logic;
+        gnd            : inout power_logic;
+        sg             : in    std_ulogic;
+        nclk           : in    clk_logic;
+        scan_in        : in    std_ulogic;
+        scan_diag_dc   : in    std_ulogic;
+        thold          : in    std_ulogic;
+        clkoff_dc_b    : out   std_ulogic;
+        delay_lclkr_dc : out   std_ulogic_vector(0 to 4);
+        act_dis_dc     : out   std_ulogic;
+        d_mode_dc      : out   std_ulogic;
+        mpw1_dc_b      : out   std_ulogic_vector(0 to 4);
+        mpw2_dc_b      : out   std_ulogic;
+        scan_out       : out   std_ulogic
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_lcbcntl_array_mac;
+
+architecture tri_lcbcntl_array_mac of tri_lcbcntl_array_mac is
+
+  signal unused : std_ulogic;
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+begin
+
+  a: if expand_type = 1 generate
+      clkoff_dc_b <= '1';
+      delay_lclkr_dc <= "00000";
+      act_dis_dc <= '0';
+      d_mode_dc <= '0';
+      mpw1_dc_b <= "11111";
+      mpw2_dc_b <= '1';
+      scan_out <= '0';
+      unused <= sg or scan_in or scan_diag_dc or thold;
+  end generate a;
+
+end tri_lcbcntl_array_mac;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbcntl_mac.vhdl

@@ -0,0 +1,86 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_lcbcntl_mac is
+
+  generic ( expand_type : integer := 1 ); 
+
+  port (
+        vdd            : inout power_logic;
+        gnd            : inout power_logic;
+        sg             : in    std_ulogic;
+        nclk           : in    clk_logic;
+        scan_in        : in    std_ulogic;
+        scan_diag_dc   : in    std_ulogic;
+        thold          : in    std_ulogic;
+        clkoff_dc_b    : out   std_ulogic;
+        delay_lclkr_dc : out   std_ulogic_vector(0 to 4);
+        act_dis_dc     : out   std_ulogic;
+        d_mode_dc      : out   std_ulogic;
+        mpw1_dc_b      : out   std_ulogic_vector(0 to 4);
+        mpw2_dc_b      : out   std_ulogic;
+        scan_out       : out   std_ulogic
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_lcbcntl_mac;
+
+architecture tri_lcbcntl_mac of tri_lcbcntl_mac is
+
+  signal unused : std_ulogic;
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+begin
+
+  a: if expand_type = 1 generate
+      clkoff_dc_b <= '1';
+      delay_lclkr_dc <= "00000";
+      act_dis_dc <= '0';
+      d_mode_dc <= '0';
+      mpw1_dc_b <= "11111";
+      mpw2_dc_b <= '1';
+      scan_out <= '0';
+      unused <= sg or scan_in or scan_diag_dc or thold;
+  end generate a;
+
+end tri_lcbcntl_mac;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbnd.vhdl

@@ -0,0 +1,85 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_lcbnd is
+
+  generic ( expand_type : integer := 1 ); 
+
+  port (
+        vd          : inout power_logic;
+        gd          : inout power_logic;
+        act         : in    std_ulogic;
+        delay_lclkr : in    std_ulogic;
+        mpw1_b      : in    std_ulogic;
+        mpw2_b      : in    std_ulogic;
+        nclk        : in    clk_logic;
+        forcee       : in    std_ulogic;
+        sg          : in    std_ulogic;
+        thold_b     : in    std_ulogic;
+        d1clk       : out   std_ulogic;
+        d2clk       : out   std_ulogic;
+        lclk        : out   clk_logic
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_lcbnd;
+
+architecture tri_lcbnd of tri_lcbnd is
+
+begin
+
+  a: if expand_type = 1 generate
+    signal gate_b : std_ulogic;
+    signal unused : std_ulogic;
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    gate_b <= forcee or act;
+
+    d1clk <= gate_b;
+    d2clk <= thold_b;
+    lclk <= nclk;
+
+    unused <= delay_lclkr or mpw1_b or mpw2_b or sg;
+  end generate a;
+
+end tri_lcbnd;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbor.vhdl

@@ -0,0 +1,71 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_lcbor is
+
+  generic ( expand_type : integer := 1 ); 
+
+  port (
+        clkoff_b : in    std_ulogic;
+        thold    : in    std_ulogic;
+        sg       : in    std_ulogic;
+        act_dis  : in    std_ulogic;
+        forcee    : out   std_ulogic;
+        thold_b  : out   std_ulogic
+       );
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity tri_lcbor;
+
+architecture tri_lcbor of tri_lcbor is
+
+  signal unused : std_ulogic;
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+begin
+
+  a: if expand_type = 1 generate
+    forcee <= '0';
+    thold_b <= not thold;
+    unused <= clkoff_b or sg or act_dis;
+  end generate a;
+
+end tri_lcbor;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_lcbs.vhdl

@@ -0,0 +1,75 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_lcbs is
+
+  generic ( expand_type : integer := 1 ); 
+
+  port (
+        vd          : inout power_logic;
+        gd          : inout power_logic;
+        delay_lclkr : in    std_ulogic;
+        nclk        : in    clk_logic;
+        forcee       : in    std_ulogic;
+        thold_b     : in    std_ulogic;
+        dclk        : out   std_ulogic;
+        lclk        : out   clk_logic
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_lcbs;
+
+architecture tri_lcbs of tri_lcbs is
+
+begin
+
+  a: if expand_type = 1 generate
+    signal unused : std_ulogic;
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    dclk <= thold_b;
+    lclk <= nclk;
+    unused <= delay_lclkr or forcee;
+  end generate a;
+
+end tri_lcbs;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nand2_nlats.vhdl

@@ -0,0 +1,120 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;    use ieee.std_logic_1164.all;
+                 use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri;     use tri.tri_latches_pkg.all;
+
+entity tri_nand2_nlats is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ; 
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "NLA0001_X1_A12TH" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        LCLK     : in    clk_logic; 
+        D1CLK    : in    std_ulogic; 
+        D2CLK    : in    std_ulogic; 
+        SCANIN   : in    std_ulogic_vector(offset to offset+width-1);
+        SCANOUT  : out   std_ulogic_vector(offset to offset+width-1);
+        A1       : in    std_ulogic_vector(offset to offset+width-1); 
+        A2       : in    std_ulogic_vector(offset to offset+width-1); 
+        QB       : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_nand2_nlats;
+
+architecture tri_nand2_nlats of tri_nand2_nlats is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal din : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= LCLK.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    din   <= A1 and A2;         
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact   <= (0 to width-1 =>     D1CLK);
+    vact_b <= (0 to width-1 => not D1CLK);
+
+    vthold_b <= (0 to width-1 => D2CLK);
+    vthold   <= (0 to width-1 => not D2CLK);
+
+    l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(LCLK.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    QB <= not int_dout;
+    SCANOUT <= zeros;
+
+    unused <= SCANIN;
+  end generate a;
+
+
+
+end tri_nand2_nlats;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat.vhdl

@@ -0,0 +1,118 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_nlat is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            reset_inverts_scan : boolean                   := true;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ;
+            synthclonedlatch   : string                    := "" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        d1clk    : in    std_ulogic;
+        d2clk    : in    std_ulogic;
+        lclk     : in    clk_logic;
+        scan_in  : in    std_ulogic;
+        din      : in    std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1);
+        scan_out : out   std_ulogic
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_nlat;
+
+architecture tri_nlat of tri_nlat is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic;
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= lclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact <= (0 to width-1 => d1clk);
+    vact_b <= (0 to width-1 => not d1clk);
+
+    vthold_b <= (0 to width-1 => d2clk);
+    vthold   <= (0 to width-1 => not d2clk);
+
+    l: process (lclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(lclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    q <= int_dout;
+    q_b <= not int_dout;
+    scan_out <= zeros(0);
+    unused <= scan_in;
+  end generate a;
+
+end tri_nlat;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nlat_scan.vhdl

@@ -0,0 +1,117 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_nlat_scan is
+
+  generic ( offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ;
+            reset_inverts_scan : boolean                   := true;
+            synthclonedlatch   : string                    := "" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        d1clk    : in    std_ulogic;
+        d2clk    : in    std_ulogic;
+        lclk     : in    clk_logic;
+        din      : in    std_ulogic_vector(offset to offset+width-1);
+        scan_in  : in    std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1);
+        scan_out : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_nlat_scan;
+
+architecture tri_nlat_scan of tri_nlat_scan is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= lclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact <= (0 to width-1 => d1clk);
+    vact_b <= (0 to width-1 => not d1clk);
+
+    vthold_b <= (0 to width-1 => d2clk);
+    vthold   <= (0 to width-1 => not d2clk);
+
+    l: process (lclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(lclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    q <= int_dout;
+    q_b <= not int_dout;
+    scan_out <= zeros;
+    unused <= scan_in;
+  end generate a;
+
+end tri_nlat_scan;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_nor2_nlats.vhdl

@@ -0,0 +1,121 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;    use ieee.std_logic_1164.all;
+                 use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri;     use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_nor2_nlats is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ; 
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "NLO0001_X1_A12TH" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        LCLK     : in    clk_logic; 
+        D1CLK    : in    std_ulogic; 
+        D2CLK    : in    std_ulogic; 
+        SCANIN   : in    std_ulogic_vector(offset to offset+width-1);
+        SCANOUT  : out   std_ulogic_vector(offset to offset+width-1);
+        A1       : in    std_ulogic_vector(offset to offset+width-1); 
+        A2       : in    std_ulogic_vector(offset to offset+width-1); 
+        QB       : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_nor2_nlats;
+
+architecture tri_nor2_nlats of tri_nor2_nlats is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal din : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= LCLK.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    din   <=  A1 or A2 ;        
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact   <= (0 to width-1 =>     D1CLK);
+    vact_b <= (0 to width-1 => not D1CLK);
+
+    vthold_b <= (0 to width-1 => D2CLK);
+    vthold   <= (0 to width-1 => not D2CLK);
+
+    l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(LCLK.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    QB <= not int_dout;
+    SCANOUT <= zeros;
+
+    unused <= SCANIN;
+  end generate a;
+
+
+end tri_nor2_nlats;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_oai22_nlats.vhdl

@@ -0,0 +1,122 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee;    use ieee.std_logic_1164.all;
+                 use ieee.numeric_std.all;
+library support; 
+                 use support.power_logic_pkg.all;
+library tri;     use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_oai22_nlats is
+
+  generic (
+            offset             : natural  range 0 to 65535 := 0;
+            width              : positive range 1 to 65536 := 1 ;
+            init               : std_ulogic_vector         := "0" ; 
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "NLM0001_X1_A12TH" ;
+            needs_sreset : integer := 1 ; 
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        LCLK     : in    clk_logic; 
+        D1CLK    : in    std_ulogic; 
+        D2CLK    : in    std_ulogic; 
+        SCANIN   : in    std_ulogic_vector(offset to offset+width-1);
+        SCANOUT  : out   std_ulogic_vector(offset to offset+width-1);
+        A1       : in    std_ulogic_vector(offset to offset+width-1); 
+        A2       : in    std_ulogic_vector(offset to offset+width-1); 
+        B1       : in    std_ulogic_vector(offset to offset+width-1); 
+        B2       : in    std_ulogic_vector(offset to offset+width-1); 
+        QB       : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_oai22_nlats;
+
+architecture tri_oai22_nlats of tri_oai22_nlats is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal din : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width-1);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= LCLK.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    din   <= (A1 or A2) and (B1 or B2) ;  
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v(0 to width-1));
+
+    vact   <= (0 to width-1 =>     D1CLK);
+    vact_b <= (0 to width-1 => not D1CLK);
+
+    vthold_b <= (0 to width-1 => D2CLK);
+    vthold   <= (0 to width-1 => not D2CLK);
+
+    l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(LCLK.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    QB <= not int_dout;
+    SCANOUT <= zeros;
+
+    unused <= SCANIN;
+  end generate a;
+
+
+end tri_oai22_nlats;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_plat.vhdl

@@ -0,0 +1,99 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_plat is
+
+  generic (
+    width       : positive range 1 to 65536 := 1 ;
+    offset      : natural range 0 to 65535  := 0 ;
+    init        : integer := 0;  
+    synthclonedlatch : string                    := "" ;
+    flushlat         : boolean                   := true ;
+    expand_type : integer := 1 ); 
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in    clk_logic;
+    flush   : in    std_ulogic;
+    din     : in    std_ulogic_vector(offset to offset+width-1);
+    q       : out   std_ulogic_vector(offset to offset+width-1) );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_plat;
+
+architecture tri_plat of tri_plat is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+
+begin  
+
+  a: if expand_type /= 2 generate
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+  begin
+
+    vsreset <= (0 to width-1 => nclk.sreset);
+    vsreset_b <= (0 to width-1 => not nclk.sreset);
+
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v);
+
+    l: process (nclk, int_din, flush, din)
+    begin
+
+      if rising_edge(nclk.clk) then
+        int_dout <= int_din;
+      end if;
+
+      if (flush = '1') then
+        int_dout <= din;
+      end if;
+
+    end process l;
+
+    q <= int_dout;
+
+  end generate a;
+
+end tri_plat;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_psro_soft.vhdl

@@ -0,0 +1,56 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;
+use ieee.std_logic_1164.all ;
+library ibm;
+use ibm.std_ulogic_support.all;
+use ibm.std_ulogic_function_support.all;
+library support;
+use support.power_logic_pkg.all;
+
+
+entity tri_psro_soft is
+  port (
+         vdd            : inout power_logic;            
+         gnd            : inout power_logic;            
+         psro_enable    : in std_ulogic_vector(0 to 2); 
+         psro_ringsig   : out std_ulogic                
+       );
+
+-- synopsys translate_off
+-- synopsys translate_on
+end tri_psro_soft;
+
+
+architecture tri_psro_soft of tri_psro_soft is
+begin
+
+  psro_ringsig  <=  or_reduce(psro_enable(0 to 2));
+
+end tri_psro_soft;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regk.vhdl

@@ -0,0 +1,116 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+library support;
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_regk is
+  generic (
+    width               : integer := 4;
+    offset              : integer range 0 to 65535 := 0 ; 
+    init                : integer := 0;                   
+    synthclonedlatch    : string  := "";
+    needs_sreset        : integer := 1 ;                  
+    expand_type         : integer := 1 );                 
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    din     : in  std_ulogic_vector(offset to offset+width-1);  
+    dout    : out std_ulogic_vector(offset to offset+width-1) );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_regk;
+
+architecture tri_regk of tri_regk is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin  
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic;
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+    int_din <= (vsreset_b and din) or
+               (vsreset and init_v);
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+    dout <= int_dout;
+
+    unused <= d_mode or delay_lclkr or mpw1_b or mpw2_b;
+  end generate a;
+
+end tri_regk;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_regs.vhdl

@@ -0,0 +1,127 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_regs is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    dout    : out std_ulogic_vector(offset to offset+width-1) );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_regs;
+
+architecture tri_regs of tri_regs is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin  
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    int_din <= (vsreset_b and int_dout) or
+               (vsreset and init_v);
+
+    vact <= (0 to width-1 => forcee);
+    vact_b <= (0 to width-1 => not forcee);
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    cob: if ibuf = true generate 
+	dout <= not int_dout;
+    end generate cob;
+
+    cnob: if ibuf = false generate 
+	dout <= int_dout;
+    end generate cnob;
+
+    scout <= zeros;
+
+    unused(0) <= delay_lclkr;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_regs;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmlatch_p.vhdl

@@ -0,0 +1,180 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+
+library support; 
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_rlmlatch_p is
+
+  generic (
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic := '0'; 
+    din     : in  std_ulogic;        
+    scout   : out std_ulogic;        
+    dout    : out std_ulogic);       
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_rlmlatch_p;
+
+architecture tri_rlmlatch_p of tri_rlmlatch_p is
+
+  constant width : integer := 1;
+  constant offset : natural := 0;
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+    component c_rlmreg_p
+      generic ( width    : positive  := 4 ;          
+            init     : std_ulogic_vector := "0"; 
+            dualscan : string := ""              
+          );
+    port (
+         nclk        : in  std_ulogic;        
+         act         : in  std_ulogic;        
+         thold_b     : in  std_ulogic;        
+         sg          : in  std_ulogic;        
+         scin        : in  std_ulogic_vector(0 to width-1);  
+         din         : in  std_ulogic_vector(0 to width-1);  
+         dout        : out std_ulogic_vector(0 to width-1);  
+         scout       : out std_ulogic_vector(0 to width-1)   
+       );
+    end component;
+    signal scanin_inv : std_ulogic;
+    signal scanout_inv : std_ulogic;
+    signal act_or_force : std_ulogic;
+    signal din_buf : std_ulogic;
+    signal dout_buf : std_ulogic;
+  begin
+    act_or_force <= act or forcee;
+
+    cib: 
+    if ibuf = true generate
+      din_buf  <= not din;
+      dout     <= not dout_buf;
+    end generate cib;
+    cnib: 
+    if ibuf = false generate
+      din_buf  <= din;
+      dout     <= dout_buf;
+    end generate cnib;
+
+    l:c_rlmreg_p
+      generic map (width => width, init  => init_v, dualscan => dualscan)
+      port map (
+        nclk       => nclk.clk,
+        act        => act_or_force,
+        thold_b    => thold_b,
+        sg         => sg,
+        scin(0)    => scanin_inv,
+        din(0)     => din_buf,
+        scout(0)   => scanout_inv,
+        dout(0)    => dout_buf);
+
+    scanin_inv <= scin xor init_v(0);
+    scout <= scanout_inv xor init_v(0);
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic;
+    signal int_dout : std_ulogic := init_v(0);
+    signal unused : std_ulogic;
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    cib: if ibuf = true generate
+      int_din <= (not sreset and not din) or
+                 (sreset and init_v(0));
+    end generate cib;
+    cnib: if ibuf = false generate
+      int_din <= (not sreset and din) or
+                 (sreset and init_v(0));
+    end generate cnib;
+
+    l: process (nclk, act, forcee, int_din, int_dout, sreset, thold_b)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= ( (((act or forcee) and thold_b) or sreset ) and int_din ) or
+                    ( ((not act and not forcee) or not thold_b) and not sreset and int_dout);
+      end if;
+    end process l;
+
+    cob: if ibuf = true generate 
+	dout <= not int_dout;
+    end generate cob;
+
+    cnob: if ibuf = false generate 
+	dout <= int_dout;
+    end generate cnob;
+
+    scout <= zeros(0);
+
+    unused <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b or scin;
+  end generate a;
+
+end tri_rlmlatch_p;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_rlmreg_p.vhdl

@@ -0,0 +1,191 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+library support; use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+-- pragma translate_off
+-- pragma translate_on
+
+entity tri_rlmreg_p is
+
+  generic (
+    width       : integer := 4;
+    offset      : integer range 0 to 65535 := 0 ; 
+    init        : integer := 0;  
+    ibuf        : boolean := false;       
+    dualscan    : string  := ""; 
+    needs_sreset: integer := 1 ; 
+    expand_type : integer := 1 );
+
+  port (
+    vd      : inout power_logic;
+    gd      : inout power_logic;
+    nclk    : in  clk_logic;
+    act     : in  std_ulogic := '1'; 
+    forcee   : in  std_ulogic := '0'; 
+    thold_b : in  std_ulogic := '1'; 
+    d_mode  : in  std_ulogic := '0'; 
+    sg      : in  std_ulogic := '0'; 
+    delay_lclkr : in  std_ulogic := '0'; 
+    mpw1_b  : in  std_ulogic := '1'; 
+    mpw2_b  : in  std_ulogic := '1'; 
+    scin    : in  std_ulogic_vector(offset to offset+width-1);  
+    din     : in  std_ulogic_vector(offset to offset+width-1);  
+    scout   : out std_ulogic_vector(offset to offset+width-1);
+    dout    : out std_ulogic_vector(offset to offset+width-1) );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_rlmreg_p;
+
+architecture tri_rlmreg_p of tri_rlmreg_p is
+
+  constant init_v : std_ulogic_vector(0 to width-1) := std_ulogic_vector( to_unsigned( init, width ) );
+  constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+
+begin  
+
+  -- synopsys translate_off
+  um: if expand_type = 0 generate
+    component c_rlmreg_p
+      generic ( width    : positive  := 4 ;          
+            init     : std_ulogic_vector := "0"; 
+            dualscan : string := ""              
+          );
+    port (
+         nclk        : in  std_ulogic;        
+         act         : in  std_ulogic;        
+         thold_b     : in  std_ulogic;        
+         sg          : in  std_ulogic;        
+         scin        : in  std_ulogic_vector(0 to width-1);  
+         din         : in  std_ulogic_vector(0 to width-1);  
+         dout        : out std_ulogic_vector(0 to width-1);  
+         scout       : out std_ulogic_vector(0 to width-1)   
+       );
+    end component;
+    signal scanin_inv : std_ulogic_vector(0 to width-1);
+    signal scanout_inv : std_ulogic_vector(0 to width-1);
+    signal act_or_force : std_ulogic;
+    signal din_buf : std_ulogic_vector(0 to width-1);
+    signal dout_buf : std_ulogic_vector(0 to width-1);
+  begin
+    act_or_force <= act or forcee;
+
+    cib: 
+    if ibuf = true generate
+      din_buf  <= not din;
+      dout     <= not dout_buf;
+    end generate cib;
+    cnib: 
+    if ibuf = false generate
+      din_buf  <= din;
+      dout     <= dout_buf;
+    end generate cnib;
+
+    l:c_rlmreg_p
+      generic map (width => width, init  => init_v, dualscan => dualscan)
+      port map (
+        nclk    => nclk.clk,
+        act     => act_or_force,
+        thold_b => thold_b,
+        sg      => sg,
+        scin    => scanin_inv,
+        din     => din_buf,
+        scout   => scanout_inv,
+        dout    => dout_buf);
+
+    scanin_inv <= scin xor init_v;
+    scout <= scanout_inv xor init_v;
+  end generate um;
+  -- synopsys translate_on
+
+  a: if expand_type = 1 generate
+    signal sreset : std_ulogic;
+    signal int_din : std_ulogic_vector(0 to width-1);
+    signal int_dout : std_ulogic_vector(0 to width-1) := init_v;
+    signal vact, vact_b : std_ulogic_vector(0 to width-1);
+    signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
+    signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
+    signal unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    rst: if needs_sreset = 1 generate
+        sreset <= nclk.sreset;
+    end generate rst;
+    no_rst: if needs_sreset /=1 generate
+        sreset <= '0';
+    end generate no_rst;
+
+    vsreset <= (0 to width-1 => sreset);
+    vsreset_b <= (0 to width-1 => not sreset);
+
+    cib: if ibuf = true generate
+      int_din <= (vsreset_b and not din) or
+                 (vsreset and init_v);
+    end generate cib;
+    cnib: if ibuf = false generate
+      int_din <= (vsreset_b and din) or
+                 (vsreset and init_v);
+    end generate cnib;
+
+    vact <= (0 to width-1 => (act or forcee));
+    vact_b <= (0 to width-1 => not (act or forcee));
+
+    vthold_b <= (0 to width-1 => thold_b);
+    vthold   <= (0 to width-1 => not thold_b);
+
+    l: process (nclk, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
+    begin
+      if rising_edge(nclk.clk) then
+        int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
+                    (((vact_b or vthold) and vsreset_b) and int_dout);
+      end if;
+    end process l;
+
+    cob: if ibuf = true generate 
+	dout <= not int_dout;
+    end generate cob;
+
+    cnob: if ibuf = false generate 
+	dout <= int_dout;
+    end generate cnob;
+
+    scout <= zeros;
+
+    unused(0) <= d_mode or sg or delay_lclkr or mpw1_b or mpw2_b;
+    unused(1 to width) <= scin;
+  end generate a;
+
+end tri_rlmreg_p;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_ser_rlmreg_p.vhdl

@@ -0,0 +1,100 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee,ibm,support,tri;
+use ieee.std_logic_1164.all;
+use support.power_logic_pkg.all;
+use tri.tri_latches_pkg.all;
+
+entity tri_ser_rlmreg_p is
+generic (
+   width             : positive range 1 to 65536 := 1 ;
+   offset            : natural  range 0 to 65535 := 0 ;
+   init              : integer := 0;
+   ibuf              : boolean := false;
+   dualscan          : string  := "";
+   needs_sreset      : integer := 1 ;
+   expand_type       : integer := 1 );
+port (
+   vd                : inout power_logic;
+   gd                : inout power_logic;
+   nclk              : in  clk_logic;
+   act               : in  std_ulogic := '1';
+   forcee             : in  std_ulogic := '0';
+   thold_b           : in  std_ulogic := '1';
+   d_mode            : in  std_ulogic := '0';
+   sg                : in  std_ulogic := '0';
+   delay_lclkr       : in  std_ulogic := '0';
+   mpw1_b            : in  std_ulogic := '1';
+   mpw2_b            : in  std_ulogic := '1';
+   scin              : in  std_ulogic_vector(offset to offset+width-1);
+   din               : in  std_ulogic_vector(offset to offset+width-1);
+   scout             : out std_ulogic_vector(offset to offset+width-1);
+   dout              : out std_ulogic_vector(offset to offset+width-1));
+
+  -- synopsys translate_off
+  -- synopsys translate_on
+
+end entity tri_ser_rlmreg_p;
+
+architecture tri_ser_rlmreg_p of tri_ser_rlmreg_p is
+
+signal dout_b, act_buf, act_buf_b, dout_buf  : std_ulogic_vector(offset to offset+width-1);
+
+begin
+   
+act_buf     <= (others=>act);
+act_buf_b   <= (others=>not(act));
+dout_buf    <= not dout_b;
+dout        <= dout_buf;
+
+tri_ser_rlmreg_p : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb)
+  generic map (
+            width   => width,
+            offset  => offset,
+            init    => init,
+            ibuf    => ibuf,
+            dualscan=> dualscan,
+            expand_type => expand_type,
+            needs_sreset => needs_sreset)
+  port map (nclk    => nclk, vd => vd, gd => gd,
+            act     => act,
+            forcee   => forcee,
+            d_mode  => d_mode, delay_lclkr => delay_lclkr,
+            mpw1_b  => mpw1_b, mpw2_b  => mpw2_b,
+            thold_b => thold_b,
+            sg      => sg,
+            scin    => scin,
+            scout   => scout,
+            A1      => din,
+            A2      => act_buf,
+            B1      => dout_buf,
+            B2      => act_buf_b,
+            QB      => dout_b);
+
+end tri_ser_rlmreg_p;

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_serial_scom2.vhdl

@@ -0,0 +1,973 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+library ibm; 
+             use ibm.std_ulogic_support.all;
+             use ibm.std_ulogic_function_support.all;
+             use ibm.std_ulogic_unsigned.all;
+library support;
+                 use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_serial_scom2 is
+
+  generic (
+           width              : positive := 64;    
+           internal_addr_decode: boolean := false;
+           use_addr           : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000";
+           addr_is_rdable     : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000";
+           addr_is_wrable     : std_ulogic_vector := "1000000000000000000000000000000000000000000000000000000000000000";
+           pipeline_addr_v    : std_ulogic_vector := "0000000000000000000000000000000000000000000000000000000000000000";
+           pipeline_paritychk : boolean  := false; 
+           satid_nobits       : positive := 4;     
+           regid_nobits       : positive := 6;
+           ringid_nobits      : positive := 3;
+           expand_type        : integer := 1 );    
+
+  port (
+        nclk                 : in  clk_logic;
+        vd                   : inout power_logic;
+        gd                   : inout power_logic;
+        scom_func_thold      : in  std_ulogic;
+        sg                   : in  std_ulogic;
+        act_dis_dc           : in  std_ulogic;
+        clkoff_dc_b          : in  std_ulogic;
+        mpw1_dc_b            : in  std_ulogic;
+        mpw2_dc_b            : in  std_ulogic;
+        d_mode_dc            : in  std_ulogic;
+        delay_lclkr_dc       : in  std_ulogic;
+
+        func_scan_in         : in  std_ulogic_vector(0 to
+                             (((width+15)/16)*16)+2*(((((width+15)/16)*16)-1)/16+1)+(2**regid_nobits)+40 );
+        func_scan_out        : out std_ulogic_vector(0 to
+                             (((width+15)/16)*16)+2*(((((width+15)/16)*16)-1)/16+1)+(2**regid_nobits)+40 );
+
+
+        dcfg_scan_dclk       : in  std_ulogic;
+        dcfg_scan_lclk       : in  clk_logic;
+
+        dcfg_d1clk           : in  std_ulogic; 
+        dcfg_d2clk           : in  std_ulogic; 
+        dcfg_lclk            : in  clk_logic; 
+
+        dcfg_scan_in         : in  std_ulogic_vector(0 to 1);
+        dcfg_scan_out        : out std_ulogic_vector(0 to 1);
+
+        scom_local_act       : out std_ulogic;
+
+        sat_id               : in std_ulogic_vector(0 to satid_nobits-1);
+
+        scom_dch_in          : in  std_ulogic;
+
+        scom_cch_in          : in  std_ulogic;
+
+        scom_dch_out         : out std_ulogic;
+
+        scom_cch_out         : out std_ulogic;
+
+        sc_req               : out std_ulogic;
+
+        sc_ack               : in  std_ulogic;
+
+        sc_ack_info          : in  std_ulogic_vector(0 to 1);
+
+        sc_r_nw              : out std_ulogic;
+
+        sc_addr              : out std_ulogic_vector(0 to regid_nobits-1);
+
+        addr_v               : out std_ulogic_vector(0 to use_addr'high);
+
+        sc_rdata             : in  std_ulogic_vector(0 to width-1);
+
+        sc_wdata             : out std_ulogic_vector(0 to width-1);
+
+        sc_wparity           : out std_ulogic;
+
+        scom_err             : out std_ulogic;
+
+        fsm_reset            : in  std_ulogic
+
+        );
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end tri_serial_scom2;
+
+architecture tri_serial_scom2 of tri_serial_scom2 is
+
+begin  
+
+  a: if expand_type /= 2 generate
+     constant state_width : positive := 5 ;
+     constant i_width     : positive := (((width+15)/16)*16);  
+     constant par_nobits  : positive := (i_width-1)/16+1;
+     constant reg_nobits  : positive := regid_nobits;  
+     constant satid_regid_nobits : positive := satid_nobits + regid_nobits;  
+     constant rw_bit_index       : positive := satid_regid_nobits + 1;  
+     constant parbit_index       : positive := rw_bit_index + 1;  
+     constant head_width         : positive := parbit_index + 1;
+     constant head_init          : std_ulogic_vector( 0 to head_width-1) := "0000000000000";
+
+     constant idle         : std_ulogic_vector(0 to state_width-1) := "00000";  
+     constant rec_head     : std_ulogic_vector(0 to state_width-1) := "00011";  
+     constant check_before : std_ulogic_vector(0 to state_width-1) := "00101";  
+     constant rec_wdata    : std_ulogic_vector(0 to state_width-1) := "00110";  
+     constant rec_wpar     : std_ulogic_vector(0 to state_width-1) := "01001";  
+     constant exe_cmd      : std_ulogic_vector(0 to state_width-1) := "01010";  
+     constant filler0      : std_ulogic_vector(0 to state_width-1) := "01100";  
+     constant filler1      : std_ulogic_vector(0 to state_width-1) := "01111";  
+     constant gen_ulinfo   : std_ulogic_vector(0 to state_width-1) := "10001";  
+     constant send_ulinfo  : std_ulogic_vector(0 to state_width-1) := "10010";  
+     constant send_rdata   : std_ulogic_vector(0 to state_width-1) := "10100";  
+     constant send_0       : std_ulogic_vector(0 to state_width-1) := "10111";  
+     constant send_1       : std_ulogic_vector(0 to state_width-1) := "11000";  
+     constant check_wpar   : std_ulogic_vector(0 to state_width-1) := "11011";  
+     constant not_selected : std_ulogic_vector(0 to state_width-1) := "11110";  
+
+     constant eof_wdata : positive := parbit_index-1+64; 
+     constant eof_wpar : positive := eof_wdata + 4;
+
+     constant eof_wdata_n : positive := parbit_index-1+ i_width;
+     constant eof_wpar_m  : positive := eof_wdata + par_nobits;
+
+
+     signal is_idle        : std_ulogic;
+     signal is_rec_head    : std_ulogic;
+     signal is_check_before: std_ulogic;
+     signal is_rec_wdata   : std_ulogic;
+     signal is_rec_wpar    : std_ulogic;
+     signal is_exe_cmd     : std_ulogic;
+     signal is_gen_ulinfo  : std_ulogic;
+     signal is_send_ulinfo : std_ulogic;
+     signal is_send_rdata  : std_ulogic;
+     signal is_send_0      : std_ulogic;
+     signal is_send_1      : std_ulogic;
+     signal is_filler_0    : std_ulogic;
+     signal is_filler_1    : std_ulogic;
+
+     signal next_state, state_in, state_lt : std_ulogic_vector(0 to state_width-1);
+
+     signal dch_lt : std_ulogic;
+     signal cch_in, cch_lt : std_ulogic_vector(0 to 1);
+
+     signal reset                                                     : std_ulogic;
+     signal got_head, gor_eofwdata, got_eofwpar, sent_rdata, got_ulhead, do_send_par
+            ,cntgtheadpluswidth, cntgteofwdataplusparity                      : std_ulogic;
+     signal p0_err, any_ack_error, match                              : std_ulogic;
+     signal p0_err_in, p0_err_lt                                      : std_ulogic;
+     signal do_write, do_read                                         : std_ulogic;
+     signal enable_cnt                                                : std_ulogic;
+     signal cnt_in, cnt_lt                                            : std_ulogic_vector(0 to 6);
+     signal head_in, head_lt                                          : std_ulogic_vector(0 to head_width-1);
+     signal tail_in, tail_lt                                          : std_ulogic_vector(0 to 4);
+     signal sc_ack_info_in, sc_ack_info_lt                            : std_ulogic_vector(0 to 1);
+     signal head_mux                                                  : std_ulogic;
+
+     signal data_shifter_in, data_shifter_lt         : std_ulogic_vector(0 to i_width-1);
+     signal data_shifter_lt_tmp : std_ulogic_vector(0 to 63);
+
+     signal datapar_shifter_in, datapar_shifter_lt   : std_ulogic_vector(0 to par_nobits-1);
+     signal data_mux, par_mux                        : std_ulogic;
+     signal dch_out_internal_in, dch_out_internal_lt : std_ulogic;
+     signal parity_satid_regaddr_in                  : std_ulogic;
+     signal parity_satid_regaddr_lt                  : std_ulogic;
+     signal func_force                               : std_ulogic;
+     signal func_thold_b, d1clk, d2clk               : std_ulogic;
+     signal lclk                                     : clk_logic;
+     signal local_act, local_act_int                 : std_ulogic;
+     signal scom_err_in, scom_err_lt                 : std_ulogic;
+     signal scom_local_act_in, scom_local_act_lt     : std_ulogic;
+
+     signal wpar_err                  : std_ulogic;
+     signal wpar_err_in, wpar_err_lt  : std_ulogic;
+     signal par_data_in, par_data_lt  : std_ulogic_vector(0 to par_nobits-1);
+     signal sc_rparity : std_ulogic_vector(0 to par_nobits-1);
+
+     signal read_valid, write_valid           : std_ulogic;
+     signal dec_addr_in,  dec_addr_q          : std_ulogic_vector(use_addr'range);
+     signal addr_nvld                         : std_ulogic;
+     signal write_nvld, read_nvld             : std_ulogic;
+     signal state_par_error                   : std_ulogic;
+     signal sat_id_net                        : std_ulogic_vector(0 to satid_nobits-1);
+
+     signal unused                            : std_ulogic_vector(0 to 1);
+
+     signal scom_cch_in_int           : std_ulogic;
+     signal scom_dch_in_int           : std_ulogic;
+     signal scom_cch_input_in, scom_cch_input_lt   : std_ulogic;
+     signal scom_dch_input_in, scom_dch_input_lt   : std_ulogic;
+
+
+     signal func_scan_temp   : std_ulogic;
+     signal func_scan_temp_1 : std_ulogic;
+     signal func_scan_temp_2 : std_ulogic;
+     signal func_scan_temp_3 : std_ulogic;
+     signal func_scan_temp_4 : std_ulogic;
+
+     signal spare_latch1_in, spare_latch1_lt   : std_ulogic;
+     signal spare_latch2_in, spare_latch2_lt   : std_ulogic;
+
+     signal unused_signals : std_ulogic;
+
+
+
+  begin
+   assert (or_reduce(use_addr)='1')
+     report "pcb if component must use at least one address, generic use_addr is all zeroes"
+     severity error;
+
+   assert (use_addr'length<=2**reg_nobits)
+     report "use_addr is larger than 2^reg_nobits"
+     severity error;
+
+
+   assert (i_width > 0)
+     report "has to be in the range of 1..64"
+     severity error;
+
+   assert (i_width < 65)
+     report "has to be in the range of 1..64"
+     severity error;
+
+
+
+  lcbor_func: entity tri.tri_lcbor(tri_lcbor)
+    generic map ( expand_type => expand_type )
+    port map (
+        clkoff_b  =>  clkoff_dc_b,
+        thold     =>  scom_func_thold,
+        sg        =>  sg,
+        act_dis   =>  act_dis_dc,
+        forcee     =>  func_force,
+        thold_b   =>  func_thold_b );
+
+
+  lcb_func: entity tri.tri_lcbnd(tri_lcbnd)
+    generic map ( expand_type => expand_type )
+    port map (
+        vd          => vd,
+        gd          => gd,
+        act         => local_act_int,
+        delay_lclkr => delay_lclkr_dc,
+        mpw1_b      => mpw1_dc_b,
+        mpw2_b      => mpw2_dc_b,
+        nclk        => nclk,
+        forcee       => func_force,
+        sg          => sg,
+        thold_b     => func_thold_b,
+        d1clk       => d1clk,
+        d2clk       => d2clk,
+        lclk        => lclk
+        );
+
+   parity_err : entity tri.tri_err_rpt(tri_err_rpt)
+      generic map (
+                 width           => 1     
+               , inline          => false 
+               , mask_reset_value=> "0"   
+               , needs_sreset    => 1
+               , expand_type => expand_type )
+      port map ( vd             => vd,
+                 gd             => gd,
+                 err_d1clk      => dcfg_d1clk,
+                 err_d2clk      => dcfg_d2clk,
+                 err_lclk       => dcfg_lclk,
+                 err_scan_in    => dcfg_scan_in (0 to 0),
+                 err_scan_out   => dcfg_scan_out(0 to 0),
+                 mode_dclk      => dcfg_scan_dclk,
+                 mode_lclk      => dcfg_scan_lclk,
+                 mode_scan_in   => dcfg_scan_in (1 to 1),
+                 mode_scan_out  => dcfg_scan_out(1 to 1),
+
+                 err_in (0)     => state_par_error,
+                 err_out(0)     => scom_err_in
+               );
+
+   scom_err <= scom_err_lt;    
+
+
+   func_scan_out(state_width + i_width + 2*par_nobits+head_width+22+(2**regid_nobits) to func_scan_out'high) <=
+     func_scan_in(state_width + i_width + 2*par_nobits+head_width+22+(2**regid_nobits) to func_scan_out'high) ;
+
+
+  sat_id_net <= sat_id;
+  scom_cch_input_in <= scom_cch_in;
+  scom_cch_in_int <= scom_cch_input_lt;
+  scom_dch_input_in <= scom_dch_in;
+  scom_dch_in_int <= scom_dch_input_lt;
+
+
+
+  cch_in    <= scom_cch_in_int & cch_lt(0);
+
+  reset     <= (cch_lt(0) and not scom_cch_in_int)   
+               or fsm_reset                          
+               or scom_err_lt;                       
+
+  local_act <= or_reduce(scom_cch_input_in & cch_lt);  
+
+  local_act_int <= local_act or scom_local_act_lt;    
+
+  scom_local_act_in <= local_act;       
+  scom_local_act <= scom_local_act_lt;
+
+  scom_cch_out <= cch_lt(0);
+
+  dch_out_internal_in <= head_lt(0)            when is_send_ulinfo='1' else
+                         '0'                   when is_send_0    ='1' else
+                         '1'                   when is_send_1    ='1' else
+                         data_shifter_lt(0)    when (is_send_rdata and not do_send_par)='1' else
+                         datapar_shifter_lt(0) when (is_send_rdata and     do_send_par)='1' else
+                         dch_lt;
+
+  scom_dch_out <= dch_out_internal_lt;
+
+   sc_req  <= is_exe_cmd;
+   sc_addr <= head_lt(satid_nobits+1 to satid_regid_nobits);
+   sc_r_nw <= head_lt(rw_bit_index);
+
+   copy2sc_wdata: if width<64 generate
+     copy2sc_wdata_loop_1: for i in 0 to width-1 generate
+       sc_wdata(i) <= data_shifter_lt(i);
+     end generate copy2sc_wdata_loop_1;
+
+
+   end generate copy2sc_wdata;
+
+   copy2sc_wdata_all: if width=64 generate
+     sc_wdata     <= data_shifter_lt;
+   end generate copy2sc_wdata_all;
+
+
+   sc_wparity <= xor_reduce(datapar_shifter_lt);
+
+   fsm_transition: process (state_lt, got_head, gor_eofwdata, got_eofwpar,
+                            got_ulhead, sent_rdata, p0_err, any_ack_error,
+                            match, do_write, do_read,
+                            cch_lt(0), dch_lt, sc_ack, wpar_err, read_nvld)
+
+      begin
+        next_state <= state_lt;
+        case state_lt is
+          when idle             => if dch_lt='1' then
+                                      next_state <= rec_head;
+                                   end if;
+
+          when rec_head         => if (got_head)='1' then
+                                     next_state <= check_before;
+                                   end if;
+
+          when check_before     => if match='0' then
+                                     next_state <= not_selected;
+                                   elsif ( (read_nvld or p0_err) and do_read)='1' then
+                                     next_state <= filler0;
+                                   elsif (not p0_err and not read_nvld and do_read)='1'  then
+                                     next_state <= exe_cmd;
+                                   else
+                                     next_state <= rec_wdata;
+                                   end if;
+
+          when rec_wdata        => if gor_eofwdata='1' then
+                                     next_state <= rec_wpar;
+                                   end if;
+
+          when rec_wpar         => if (got_eofwpar and not p0_err)='1' then
+                                     next_state <= check_wpar;
+                                   elsif (got_eofwpar and p0_err)='1' then
+                                     next_state <= filler0;
+                                   end if;
+
+          when check_wpar       => if wpar_err='0' then
+                                     next_state <= exe_cmd;
+                                   else
+                                     next_state <= filler1;
+                                   end if;
+
+          when exe_cmd          => if sc_ack='1' then
+                                     next_state <= filler1;
+                                   end if;
+
+          when filler0          => next_state <= filler1;
+
+          when filler1          => next_state <= gen_ulinfo;
+
+          when gen_ulinfo       => next_state <= send_ulinfo;
+
+          when send_ulinfo      => if (got_ulhead and (do_write or (do_read and any_ack_error)))='1' then
+                                     next_state <= send_0;
+                                   elsif (got_ulhead and do_read)='1' then  
+                                     next_state <= send_rdata;
+                                   end if;
+
+          when send_rdata       => if sent_rdata='1' then
+                                     next_state <= send_0;
+                                   end if;
+
+          when send_0           => next_state <= send_1;
+
+          when send_1           => next_state <= idle;
+
+          when not_selected     => if cch_lt(0)='0' then
+                                     next_state <= idle;
+                                   end if;
+
+          when others          => next_state <= idle;
+
+        end case;
+
+      end process fsm_transition;
+
+      state_in <= state_lt when local_act='0' else
+                  idle     when reset='1' else
+                  next_state;
+
+      state_par_error <= xor_reduce(state_lt);
+
+      is_idle         <= (state_lt=idle);
+      is_rec_head     <= (state_lt=rec_head);
+      is_check_before <= (state_lt=check_before);
+      is_rec_wdata    <= (state_lt=rec_wdata);
+      is_rec_wpar     <= (state_lt=rec_wpar);
+      is_exe_cmd      <= (state_lt=exe_cmd);
+      is_gen_ulinfo   <= (state_lt=gen_ulinfo);
+      is_send_ulinfo  <= (state_lt=send_ulinfo);
+      is_send_rdata   <= (state_lt=send_rdata);
+      is_send_0       <= (state_lt=send_0);
+      is_send_1       <= (state_lt=send_1);
+      is_filler_0     <= (state_lt=filler0);
+      is_filler_1     <= (state_lt=filler1);
+
+      enable_cnt <= is_rec_head
+                    or is_check_before
+                    or is_rec_wdata
+                    or is_rec_wpar
+                    or is_send_ulinfo
+                    or is_send_rdata
+                    or is_send_0
+                    or is_send_1
+                    ;
+      cnt_in <= (others=>'0')      when ((is_idle or is_gen_ulinfo) = '1') else
+                cnt_lt + "0000001" when (enable_cnt = '1') else
+                cnt_lt;
+
+      got_head <= (cnt_lt = (1+satid_nobits+regid_nobits));
+
+      got_ulhead <= (cnt_lt = (1+satid_nobits+regid_nobits+4));
+
+      gor_eofwdata         <= (cnt_lt = eof_wdata);
+      got_eofwpar          <= (cnt_lt = eof_wpar);
+
+      sent_rdata           <= (cnt_lt=tconv(83,7));
+
+      cntgtheadpluswidth   <= (cnt_lt > eof_wdata_n);
+      cntgteofwdataplusparity <= (cnt_lt > eof_wpar_m);
+
+      do_send_par         <= (cnt_lt > 79); 
+
+      head_in(head_width-2 to head_width-1) <= head_lt(head_width-1) & dch_lt when (is_rec_head or (is_idle and dch_lt))='1' else
+                           head_lt(head_width-2 to head_width-1);
+
+      head_in(0 to satid_regid_nobits)  <= head_lt(1 to satid_regid_nobits) & head_mux when (is_rec_head or is_send_ulinfo)='1' else
+                           head_lt(0 to satid_regid_nobits);
+
+      head_mux <= head_lt(rw_bit_index) when is_rec_head='1' else
+                  tail_lt(0);
+
+
+      tail_in(4) <= xor_reduce ( parity_satid_regaddr_lt & tail_lt(0) & (wpar_err and do_write) & sc_ack_info_lt(0 to 1))
+                                                                    when is_gen_ulinfo='1'and (internal_addr_decode=false) else
+                    xor_reduce ( parity_satid_regaddr_lt & tail_lt(0) & (wpar_err and do_write) & (write_nvld or read_nvld) & addr_nvld )
+                                                                    when is_gen_ulinfo='1'and (internal_addr_decode=true)
+                    else tail_lt(4);
+
+
+
+      tail_in(2 to 3) <= sc_ack_info_lt(0 to 1)  when is_gen_ulinfo='1' and internal_addr_decode=false else
+                         (write_nvld or read_nvld) & addr_nvld when is_gen_ulinfo='1' and internal_addr_decode=true else
+                         tail_lt(3 to 4)              when is_send_ulinfo='1' else 
+                         tail_lt(2 to 3);
+
+
+
+      tail_in(1)      <= (wpar_err and do_write)   when is_gen_ulinfo='1' else 
+                         tail_lt(2) when is_send_ulinfo='1' else  
+                         tail_lt(1);
+
+      tail_in(0)      <= not p0_err     when is_check_before='1' else 
+                         tail_lt(1) when is_send_ulinfo='1' else  
+                         tail_lt(0);
+
+      sc_ack_info_in <= sc_ack_info when (is_exe_cmd and sc_ack)='1' else
+                        "00" when is_idle='1' else
+                        sc_ack_info_lt;
+
+
+      do_write <= not do_read;
+      do_read  <= head_lt(rw_bit_index);
+      match    <= (head_lt(1 to satid_nobits)=sat_id_net);
+
+      p0_err_in <= '0' when (is_idle = '1') else
+                   p0_err_lt xor head_in(parbit_index) when (is_rec_head = '1') else
+                   p0_err_lt ;
+      p0_err <= p0_err_lt;
+      parity_satid_regaddr_in   <= xor_reduce (sat_id_net & head_lt(satid_nobits+1 to satid_regid_nobits)); 
+
+      any_ack_error <= or_reduce(sc_ack_info_lt);
+
+
+      data_mux <= dch_lt when (is_check_before or is_rec_wdata)='1' else
+                  '0';
+
+      data_shifter_in_1: if (width = i_width) generate
+      data_shifter_in <= data_shifter_lt(1 to i_width-1) & data_mux when (is_check_before or
+                                                                         (is_rec_wdata and not cntgtheadpluswidth) or
+                                                                          is_send_rdata)='1' else
+                         (sc_rdata(0 to width-1)) when (is_exe_cmd and sc_ack and do_read)='1' else
+                         data_shifter_lt;
+      end generate data_shifter_in_1; 
+
+      data_shifter_in_2: if (width < i_width) generate
+      data_shifter_in <= data_shifter_lt(1 to i_width-1) & data_mux when (is_check_before or
+                                                                         (is_rec_wdata and not cntgtheadpluswidth) or
+                                                                          is_send_rdata)='1' else
+                         (sc_rdata(0 to width-1) & (width to i_width-1 =>'0')) when (is_exe_cmd and sc_ack and do_read)='1' else
+                         data_shifter_lt;
+      end generate data_shifter_in_2; 
+      par_mux <= dch_lt when (is_rec_wpar)='1' else
+                 '0';
+
+      datapar_shifter_in <= datapar_shifter_lt(1 to par_nobits-1) & par_mux when ((is_rec_wpar and not cntgteofwdataplusparity)or
+                                                                                  (is_send_rdata and do_send_par))='1' else
+                            sc_rparity when (is_filler_1 ='1') else  
+                            datapar_shifter_lt;
+
+
+      data_shifter_move_1: if (width = i_width) generate  
+         data_shifter_lt_tmp (0 to width-1) <= data_shifter_lt;
+         data_shifter_padding_1: if width < 64 generate
+            data_shifter_lt_tmp(width to 63) <= (others=>'0');
+         end generate data_shifter_padding_1;
+      end generate data_shifter_move_1;
+
+      data_shifter_move_2: if (width < i_width) generate
+          data_shifter_lt_tmp(0 to width-1) <= data_shifter_lt(0 to width-1);
+          data_shifter_lt_tmp(width to i_width-1) <= data_shifter_lt(width to i_width-1);
+          data_shifter_padding_1: if i_width < 64 generate
+             data_shifter_lt_tmp(i_width to 63) <= (others=>'0');
+          end generate data_shifter_padding_1;
+      end generate data_shifter_move_2;
+
+      wdata_par_check: for i in 0 to par_nobits-1 generate
+        par_data_in(i) <= xor_reduce(data_shifter_lt_tmp(16*i to 16*(i+1)-1));
+      end generate wdata_par_check;
+
+      wdata_par_check_pipe: if pipeline_paritychk=true generate
+        state: entity tri.tri_nlat_scan(tri_nlat_scan)
+          generic map( width => par_nobits,
+                       needs_sreset => 1,
+                       expand_type => expand_type )
+          port map
+          (   d1clk     => d1clk
+            , vd        => vd
+            , gd        => gd
+            , lclk      => lclk
+            , d2clk     => d2clk
+            , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21)
+            , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21)
+            , din       => par_data_in
+            , q         => par_data_lt
+            );
+      end generate wdata_par_check_pipe;
+
+      wdata_par_check_nopipe: if pipeline_paritychk=false generate
+        par_data_lt <= par_data_in;
+        func_scan_out(state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21)
+          <= func_scan_in (state_width+i_width+par_nobits+head_width+22 to state_width+i_width+2*par_nobits+head_width+21);
+
+      end generate wdata_par_check_nopipe;
+
+      wpar_err_in   <= or_reduce(par_data_in xor datapar_shifter_in); 
+      wpar_err <= wpar_err_lt;
+
+      rdata_parity_gen: for i in 0 to par_nobits-1 generate
+        sc_rparity(i) <= xor_reduce(data_shifter_lt_tmp(16*i to 16*(i+1)-1));
+      end generate rdata_parity_gen;
+
+   internal_addr_decoding: if internal_addr_decode=true generate
+     foralladdresses : for i in use_addr'range generate
+       addr_bit_set : if (use_addr(i) = '1') generate
+         dec_addr_in(i) <= (head_lt(satid_nobits+1 to satid_regid_nobits) = tconv(i, reg_nobits));
+
+         latch_for_onehot : if pipeline_addr_v(i) = '1' generate
+           dec_addr       : entity tri.tri_nlat(tri_nlat)
+             generic map( width  => 1,
+                          needs_sreset => 1,
+                          expand_type => expand_type)
+             port map ( d1clk    => d1clk,
+                        vd       => vd,
+                        gd       => gd,
+                        d2clk    => d2clk,
+                        lclk     => lclk,
+                        scan_in  => func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i),
+                        din(0)   => dec_addr_in(i),
+                        q(0)     => dec_addr_q(i),
+                        scan_out => func_scan_out(state_width+i_width+2*par_nobits+head_width+22 +i) );
+         end generate latch_for_onehot;
+
+         no_latch_for_onehot : if pipeline_addr_v(i) = '0' generate
+           func_scan_out(state_width+i_width+2*par_nobits+head_width+22 +i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i);
+           dec_addr_q(i) <= dec_addr_in(i);
+         end generate no_latch_for_onehot;
+
+       end generate addr_bit_set;
+       addr_bit_notset : if (use_addr(i) /= '1') generate  
+         func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i);
+         dec_addr_in(i)                                     <= '0';
+         dec_addr_q(i)                                      <= dec_addr_in(i);
+       end generate addr_bit_notset;
+     end generate foralladdresses;
+   read_valid    <=  or_reduce(dec_addr_in and addr_is_rdable);
+   write_valid   <=  or_reduce(dec_addr_in and addr_is_wrable);
+   addr_nvld     <=  not or_reduce(dec_addr_in);
+   write_nvld    <= (not write_valid and not addr_nvld) and do_write;
+   read_nvld     <= (not read_valid  and not addr_nvld) and do_read;
+
+   unused <= "00";
+   end generate internal_addr_decoding;
+
+
+   external_addr_decoding: if internal_addr_decode=false generate
+     foralladdresses : for i in use_addr'range generate
+         func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22 +i);
+         dec_addr_in(i)                                     <= '0';
+         dec_addr_q(i)                                      <= dec_addr_in(i);
+     end generate foralladdresses;
+   read_valid <= '1';
+   write_valid<= '1';
+   addr_nvld <= '0';
+   write_nvld <= '0';
+   read_nvld  <= '0';
+
+   unused <= write_valid & read_valid;
+   end generate external_addr_decoding;
+
+
+
+   short_unused_addr_range: for i in use_addr'high+1 to 63 generate
+     func_scan_out(state_width+i_width+2*par_nobits+head_width+22+i) <= func_scan_in(state_width+i_width+2*par_nobits+head_width+22+i);
+   end generate short_unused_addr_range;
+
+   addr_v <= dec_addr_q(0 to use_addr'high);
+
+
+    state: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => state_width, init => idle, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (0 to state_width-1)
+     , scan_out  => func_scan_out(0 to state_width-1)
+     , din       => state_in
+     , q         => state_lt
+     );
+
+    counter: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => 7, init => "0000000", needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width to state_width+6)
+     , scan_out  => func_scan_out(state_width to state_width+6)
+     , din       => cnt_in
+     , q         => cnt_lt
+     );
+
+    data_shifter: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => i_width, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+7 to state_width+i_width+6)
+     , scan_out  => func_scan_out(state_width+7 to state_width+i_width+6)
+     , din       => data_shifter_in
+     , q         => data_shifter_lt
+     );
+
+    datapar_shifter: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => par_nobits, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+7 to state_width+i_width+par_nobits+6)
+     , scan_out  => func_scan_out(state_width+i_width+7 to state_width+i_width+par_nobits+6)
+     , din       => datapar_shifter_in
+     , q         => datapar_shifter_lt
+     );
+
+    head_lat: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => head_width, init => head_init, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+7 to state_width+i_width+par_nobits+head_width+6)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+7 to state_width+i_width+par_nobits+head_width+6)
+     , din       => head_in
+     , q         => head_lt
+     );
+
+    tail_lat: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => 5, init => "00000", needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk,
+     vd        => vd,
+     gd        => gd,
+     lclk      => lclk,
+     d2clk     => d2clk,
+     scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+7 to state_width+i_width+par_nobits+head_width+11),
+     scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+7 to state_width+i_width+par_nobits+head_width+11),
+     din       => tail_in,
+     q         => tail_lt
+     );
+
+    dch_inlatch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+12)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+12)
+     , din(0)    => scom_dch_in_int
+     , q(0)      => dch_lt
+     );
+
+
+    ack_info: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => 2, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+13 to state_width+i_width+par_nobits+head_width+14)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+13 to state_width+i_width+par_nobits+head_width+14)
+     , din       => sc_ack_info_in
+     , q         => sc_ack_info_lt
+     );
+
+    dch_outlatch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+15)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+15)
+     , din(0)    => dch_out_internal_in
+     , q(0)      => dch_out_internal_lt
+     );
+
+    cch_latches: entity tri.tri_nlat_scan(tri_nlat_scan)
+    generic map( width => 2, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+16 to state_width+i_width+par_nobits+head_width+17)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+16 to state_width+i_width+par_nobits+head_width+17)
+     , din       => cch_in
+     , q         => cch_lt
+     );
+
+    scom_err_latch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+18)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+18)
+     , din(0)    => scom_err_in
+     , q(0)      => scom_err_lt
+     );
+
+    scom_local_act_latch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+19)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+19)
+     , din(0)    => scom_local_act_in
+     , q(0)      => scom_local_act_lt
+     );
+
+    spare_latch1: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in (state_width+i_width+par_nobits+head_width+20)
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+20)
+     , din(0)    => spare_latch1_in
+     , q(0)      => spare_latch1_lt
+     );
+
+    spare_latch2: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_in(state_width+i_width+par_nobits+head_width+21)
+     , scan_out  => func_scan_temp
+     , din(0)    => spare_latch2_in
+     , q(0)      => spare_latch2_lt
+     );
+
+    scom_cch_input_latch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_temp
+     , scan_out  => func_scan_temp_1
+     , din(0)    => scom_cch_input_in
+     , q(0)      => scom_cch_input_lt
+     );
+
+    scom_dch_input_latch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_temp_1
+     , scan_out  => func_scan_temp_2
+     , din(0)    => scom_dch_input_in
+     , q(0)      => scom_dch_input_lt
+     );
+
+    parity_reg1: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_temp_2
+     , scan_out  => func_scan_temp_3
+     , din(0)    => parity_satid_regaddr_in
+     , q(0)      => parity_satid_regaddr_lt
+     );
+
+    p0_err_latch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_temp_3
+     , scan_out  => func_scan_temp_4
+     , din(0)    => p0_err_in
+     , q(0)      => p0_err_lt
+     );
+
+    wpar_err_latch: entity tri.tri_nlat(tri_nlat)
+    generic map( width => 1, needs_sreset => 1, expand_type => expand_type )
+    port map
+     ( d1clk     => d1clk
+     , vd        => vd
+     , gd        => gd
+     , lclk      => lclk
+     , d2clk     => d2clk
+     , scan_in   => func_scan_temp_4
+     , scan_out  => func_scan_out(state_width+i_width+par_nobits+head_width+21)
+     , din(0)    => wpar_err_in
+     , q(0)      => wpar_err_lt
+     );
+
+   unused_signals <= or_reduce ( is_filler_0 & is_filler_1
+                     & spare_latch1_lt
+                     & spare_latch2_lt
+                     & par_data_lt
+                     & d_mode_dc ) ;
+   
+   spare_latch1_in <= '0';
+   spare_latch2_in <= '0';
+
+
+  end generate a;
+
+end tri_serial_scom2;
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/tri/tri_slat_scan.vhdl

@@ -0,0 +1,80 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all;
+              use ieee.numeric_std.all;
+library support;                  use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity tri_slat_scan is
+
+  generic ( width              : positive range 1 to 65536 := 1 ;
+            offset             : natural  range 0 to 65535 := 0;
+            init               : std_ulogic_vector         := "0" ;
+            synthclonedlatch   : string                    := "" ;
+            btr                : string                    := "c_slat_scan" ;
+            reset_inverts_scan : boolean                   := true;
+            expand_type : integer := 1 ); 
+  port (
+        vd       : inout power_logic;
+        gd       : inout power_logic;
+        dclk     : in    std_ulogic;
+        lclk     : in    clk_logic;
+        scan_in  : in    std_ulogic_vector(offset to offset+width-1);
+        scan_out : out   std_ulogic_vector(offset to offset+width-1);
+        q        : out   std_ulogic_vector(offset to offset+width-1);
+        q_b      : out   std_ulogic_vector(offset to offset+width-1)
+       );
+
+  -- synopsys translate_off
+
+  -- synopsys translate_on
+
+end entity tri_slat_scan;
+
+architecture tri_slat_scan of tri_slat_scan is
+
+begin
+
+  a: if expand_type = 1 generate
+    constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
+    constant initv : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
+    signal  unused : std_ulogic_vector(0 to width);
+    -- synopsys translate_off
+    -- synopsys translate_on
+  begin
+    scan_out <= zeros;
+    q <= initv(0 to width-1);
+    q_b <= not initv(0 to width-1);
+    unused(0) <= dclk;
+    unused(1 to width) <= scan_in;
+  end generate a;
+
+end tri_slat_scan;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_axi.vhdl

@@ -0,0 +1,658 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+library ieee; use ieee.std_logic_1164.all;
+library ibm;
+library work; use work.all;
+  use ibm.std_ulogic_support.all;
+  use ibm.std_ulogic_function_support.all;
+library support;
+  use support.power_logic_pkg.all;
+library tri;
+use tri.tri_latches_pkg.all;
+
+entity a2x_axi is
+	generic (
+     C_M00_AXI_ID_WIDTH	: integer	:= 4;
+     C_M00_AXI_ADDR_WIDTH	: integer	:= 32;
+	  C_M00_AXI_DATA_WIDTH	: integer	:= 32;
+     C_M00_AXI_AWUSER_WIDTH	: integer	:= 4;
+     C_M00_AXI_ARUSER_WIDTH	: integer	:= 4;
+     C_M00_AXI_WUSER_WIDTH	: integer	:= 4;
+     C_M00_AXI_RUSER_WIDTH	: integer	:= 4;
+     C_M00_AXI_BUSER_WIDTH	: integer	:= 4
+	);
+   port (
+   
+      clk               : in std_logic;
+      clk2x             : in std_logic;    
+      reset_n           : in std_logic;                        
+      thold             : in std_logic;                        
+      
+      core_id           : in std_logic_vector(0 to 7);         
+      thread_stop       : in std_logic_vector(0 to 3);         
+      thread_running    : out std_logic_vector(0 to 3);        
+      
+      ext_mchk          : in std_logic_vector(0 to 3);         
+      ext_checkstop     : in std_logic;                        
+      debug_stop        : in  std_logic;                       
+      mchk              : out std_logic_vector(0 to 3);        
+      recov_err         : out std_logic_vector(0 to 2);        
+      checkstop         : out std_logic_vector(0 to 2);        
+      a2l2_axi_err      : out std_logic_vector(0 to 3);        
+      
+      crit_interrupt    : in std_logic_vector(0 to 3);         
+      ext_interrupt     : in std_logic_vector(0 to 3);         
+      perf_interrupt    : in std_logic_vector(0 to 3);         
+      
+      tb_update_enable  : in std_logic;                        
+      tb_update_pulse   : in std_logic;                        
+      
+      scom_sat_id       : in std_logic_vector(0 to 3);         
+      scom_dch_in       : in std_logic;
+      scom_cch_in       : in std_logic;
+      scom_dch_out      : out std_logic;
+      scom_cch_out      : out std_logic;
+      
+      flh2l2_gate       : in std_logic;
+      hang_pulse        : in std_logic_vector(0 to 3);
+
+		m00_axi_awid	: out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
+		m00_axi_awaddr	: out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
+		m00_axi_awlen	: out std_logic_vector(7 downto 0);
+		m00_axi_awsize	: out std_logic_vector(2 downto 0);
+		m00_axi_awburst	: out std_logic_vector(1 downto 0);
+		m00_axi_awlock	: out std_logic;
+		m00_axi_awcache	: out std_logic_vector(3 downto 0);
+		m00_axi_awprot	: out std_logic_vector(2 downto 0);
+		m00_axi_awqos	: out std_logic_vector(3 downto 0);
+		m00_axi_awuser	: out std_logic_vector(C_M00_AXI_AWUSER_WIDTH-1 downto 0);
+		m00_axi_awvalid	: out std_logic;
+		m00_axi_awready	: in std_logic;
+		m00_axi_wdata	: out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
+		m00_axi_wstrb	: out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0);
+		m00_axi_wlast	: out std_logic;
+		m00_axi_wuser	: out std_logic_vector(C_M00_AXI_WUSER_WIDTH-1 downto 0);
+		m00_axi_wvalid	: out std_logic;
+		m00_axi_wready	: in std_logic;
+		m00_axi_bid	: in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
+		m00_axi_bresp	: in std_logic_vector(1 downto 0);
+		m00_axi_buser	: in std_logic_vector(C_M00_AXI_BUSER_WIDTH-1 downto 0);
+		m00_axi_bvalid	: in std_logic;
+		m00_axi_bready	: out std_logic;
+		m00_axi_arid	: out std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
+		m00_axi_araddr	: out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
+		m00_axi_arlen	: out std_logic_vector(7 downto 0);
+		m00_axi_arsize	: out std_logic_vector(2 downto 0);
+		m00_axi_arburst	: out std_logic_vector(1 downto 0);
+		m00_axi_arlock	: out std_logic;
+		m00_axi_arcache	: out std_logic_vector(3 downto 0);
+		m00_axi_arprot	: out std_logic_vector(2 downto 0);
+		m00_axi_arqos	: out std_logic_vector(3 downto 0);
+		m00_axi_aruser	: out std_logic_vector(C_M00_AXI_ARUSER_WIDTH-1 downto 0);
+		m00_axi_arvalid	: out std_logic;
+		m00_axi_arready	: in std_logic;
+		m00_axi_rid	: in std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
+		m00_axi_rdata	: in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
+		m00_axi_rresp	: in std_logic_vector(1 downto 0);
+		m00_axi_rlast	: in std_logic;
+		m00_axi_ruser	: in std_logic_vector(C_M00_AXI_RUSER_WIDTH-1 downto 0);
+		m00_axi_rvalid	: in std_logic;
+		m00_axi_rready	: out std_logic
+      
+   );
+end a2x_axi;   
+
+architecture a2x_axi of a2x_axi is
+
+  constant expand_type         : integer := 1;
+  constant threads             : integer := 4;
+  constant xu_real_data_add    : integer := 42;
+  constant st_data_32b_mode    : integer := 1;
+  constant ac_st_data_32b_mode : integer := 1;
+  constant error_width         : integer := 3;
+  constant expand_tlb_type     : integer := 2;
+  constant extclass_width      : integer := 2;
+  constant inv_seq_width       : integer := 4;
+  constant lpid_width          : integer := 8;
+  constant pid_width           : integer := 14;
+  constant ra_entry_width      : integer := 12;
+  constant real_addr_width     : integer := 42;
+ 
+signal a2_nclk : clk_logic;
+ 
+signal an_ac_sg_7              :  std_logic;
+signal an_ac_back_inv          :  std_logic;
+signal an_ac_back_inv_addr     :  std_logic_vector(22 to 63);
+signal an_ac_back_inv_lbit     :  std_logic;
+signal an_ac_back_inv_gs       :  std_logic;
+signal an_ac_back_inv_ind      :  std_logic;
+signal an_ac_back_inv_local    :  std_logic;
+signal an_ac_back_inv_lpar_id  :  std_logic_vector(0 to 7);
+signal an_ac_back_inv_target   :  std_logic_vector(0 to 4);
+signal an_ac_dcr_act           :  std_logic;
+signal an_ac_dcr_val           :  std_logic;
+signal an_ac_dcr_read          :  std_logic;
+signal an_ac_dcr_etid          :  std_logic_vector(0 to 1);
+signal an_ac_dcr_data          :  std_logic_vector(0 to 63);
+signal an_ac_dcr_done          :  std_logic;
+signal an_ac_flh2l2_gate       :  std_logic;                       
+signal an_ac_reld_core_tag     :  std_logic_vector(0 to 4);
+signal an_ac_reld_data         :  std_logic_vector(0 to 127);
+signal an_ac_reld_data_vld     :  std_logic;
+signal an_ac_reld_ecc_err      :  std_logic;
+signal an_ac_reld_ecc_err_ue   :  std_logic;
+signal an_ac_reld_qw           :  std_logic_vector(57 to 59);
+signal an_ac_reld_data_coming  :  std_logic;
+signal an_ac_reld_ditc         :  std_logic;
+signal an_ac_reld_crit_qw      :  std_logic;
+signal an_ac_reld_l1_dump      :  std_logic;
+
+signal an_ac_req_ld_pop        :  std_logic;
+signal an_ac_req_st_gather     :  std_logic;
+signal an_ac_req_st_pop        :  std_logic;
+signal an_ac_req_st_pop_thrd   :  std_logic_vector(0 to 2);
+
+signal an_ac_stcx_complete     :  std_logic_vector(0 to 3);
+signal an_ac_stcx_pass         :  std_logic_vector(0 to 3);
+signal an_ac_sync_ack          :  std_logic_vector(0 to 3);
+signal an_ac_user_defined      :  std_logic_vector(0 to 3);
+signal an_ac_reservation_vld   :  std_logic_vector(0 to 3);
+
+signal an_ac_icbi_ack          :  std_ulogic;
+signal an_ac_icbi_ack_thread   :  std_ulogic_vector(0 to 1);
+signal an_ac_sleep_en          :  std_ulogic_vector(0 to 3);
+signal ac_an_back_inv_reject   :  std_ulogic;
+signal ac_an_box_empty         :  std_ulogic_vector(0 to 3);
+signal ac_an_lpar_id           :  std_ulogic_vector(0 to 7);
+signal ac_an_power_managed     :  std_ulogic;
+signal ac_an_req               :  std_ulogic;
+signal ac_an_req_endian        :  std_ulogic;
+signal ac_an_req_ld_core_tag   :  std_ulogic_vector(0 to 4);
+signal ac_an_req_ld_xfr_len    :  std_ulogic_vector(0 to 2);
+signal ac_an_req_pwr_token     :  std_ulogic;
+signal ac_an_req_ra            :  std_ulogic_vector(22 to 63);
+signal ac_an_req_spare_ctrl_a0 :  std_ulogic_vector(0 to 3);
+signal ac_an_req_thread        :  std_ulogic_vector(0 to 2);
+signal ac_an_req_ttype         :  std_ulogic_vector(0 to 5);
+signal ac_an_req_user_defined  :  std_ulogic_vector(0 to 3);
+signal ac_an_req_wimg_g        :  std_ulogic;
+signal ac_an_req_wimg_i        :  std_ulogic;
+signal ac_an_req_wimg_m        :  std_ulogic;
+signal ac_an_req_wimg_w        :  std_ulogic;
+signal ac_an_reld_ditc_pop     :  std_ulogic_vector(0 to 3);
+signal ac_an_rvwinkle_mode     :  std_ulogic;
+signal ac_an_st_byte_enbl      :  std_ulogic_vector(0 to 31);
+signal ac_an_st_data           :  std_ulogic_vector(0 to 255);
+signal ac_an_st_data_pwr_token :  std_ulogic;
+signal ac_an_fu_bypass_events  :  std_ulogic_vector(0 to 7);
+signal ac_an_iu_bypass_events  :  std_ulogic_vector(0 to 7);
+signal ac_an_mm_bypass_events  :  std_ulogic_vector(0 to 7);
+signal an_ac_debug_stop        :  std_ulogic;
+signal ac_an_psro_ringsig      :  std_ulogic;
+signal an_ac_psro_enable_dc    :  std_ulogic_vector(0 to 2);
+signal an_ac_req_spare_ctrl_a1 :  std_ulogic_vector(0 to 3);
+signal alt_disp                :  std_ulogic;
+signal d_mode                  :  std_ulogic;
+signal delay_lclkr             :  std_ulogic;
+signal mpw1_b                  :  std_ulogic;
+signal mpw2_b                  :  std_ulogic;
+signal scdis_b                 :  std_ulogic;
+
+signal an_ac_abist_mode_dc     :  std_ulogic;
+signal an_ac_abist_start_test  :  std_ulogic;
+signal an_ac_abst_scan_in      :  std_ulogic_vector(0 to 9);
+signal an_ac_atpg_en_dc        :  std_ulogic;
+signal an_ac_bcfg_scan_in          :  std_ulogic_vector(0 to 4);
+signal an_ac_lbist_ary_wrt_thru_dc  :  std_ulogic;
+signal an_ac_ccenable_dc           :  std_ulogic;
+signal an_ac_ccflush_dc            :  std_ulogic;
+signal an_ac_reset_1_complete      :  std_ulogic;
+signal an_ac_reset_2_complete      :  std_ulogic;
+signal an_ac_reset_3_complete      :  std_ulogic;
+signal an_ac_reset_wd_complete     :  std_ulogic;
+signal an_ac_dcfg_scan_in          :  std_ulogic_vector(0 to 2);
+signal an_ac_fce_7                 :  std_ulogic;
+signal an_ac_func_scan_in          :  std_ulogic_vector(0 to 63);
+signal an_ac_gptr_scan_in      :  std_ulogic;
+signal an_ac_hang_pulse        :  std_ulogic_vector(0 to 3);
+signal an_ac_lbist_en_dc       :  std_ulogic;    
+signal an_ac_lbist_ac_mode_dc  :  std_ulogic; 
+signal an_ac_lbist_ip_dc       :  std_ulogic;  
+signal an_ac_malf_alert        :  std_ulogic;  
+signal an_ac_gsd_test_enable_dc :  std_ulogic;
+signal an_ac_gsd_test_acmode_dc :  std_ulogic;
+signal an_ac_repr_scan_in      :  std_ulogic;
+signal an_ac_scan_diag_dc      :  std_ulogic;
+signal an_ac_scan_dis_dc_b     :  std_ulogic;
+signal an_ac_scan_type_dc      :  std_ulogic_vector(0 to 8);
+signal an_ac_scom_sat_id       :  std_ulogic_vector(0 to 3);
+signal an_ac_checkstop         :  std_ulogic;
+signal an_ac_machine_check     :  std_ulogic_vector(0 to 3);
+signal an_ac_tb_update_enable  : std_ulogic;
+signal an_ac_tb_update_pulse   : std_ulogic;
+signal an_ac_time_scan_in      :  std_ulogic;
+signal an_ac_regf_scan_in      :  std_ulogic_vector(0 to 11);
+
+signal ac_an_debug_bus         :  std_ulogic_vector(0 to 87);
+signal ac_an_event_bus         :  std_ulogic_vector(0 to 7);
+signal ac_an_trace_triggers    :  std_ulogic_vector(0 to 11);
+signal ac_an_abist_done_dc     :  std_ulogic;
+signal ac_an_abst_scan_out     :  std_ulogic_vector(0 to 9);
+signal ac_an_bcfg_scan_out     :  std_ulogic_vector(0 to 4);
+signal ac_an_dcfg_scan_out     :  std_ulogic_vector(0 to 2);
+signal ac_an_debug_trigger     :  std_ulogic_vector(0 to 3);
+signal ac_an_func_scan_out     :  std_ulogic_vector(0 to 63);
+signal ac_an_gptr_scan_out     :  std_ulogic;
+signal ac_an_repr_scan_out     :  std_ulogic;
+signal ac_an_time_scan_out     :  std_ulogic;
+signal ac_an_special_attn      :  std_ulogic_vector(0 to 3);
+signal ac_an_checkstop         :  std_ulogic_vector(0 to 2);
+signal ac_an_dcr_act	       :  std_ulogic;
+signal ac_an_dcr_val	       :  std_ulogic;
+signal ac_an_dcr_read          :  std_ulogic;
+signal ac_an_dcr_user          :  std_ulogic;
+signal ac_an_dcr_etid          :  std_ulogic_vector(0 to 1);
+signal ac_an_dcr_addr          :  std_ulogic_vector(11 to 20);
+signal ac_an_dcr_data          :  std_ulogic_vector(0 to 63);
+
+signal ac_an_machine_check     :  std_ulogic_vector(0 to 3);
+signal ac_an_pm_thread_running :  std_ulogic_vector(0 to 3);
+signal ac_an_recov_err         :  std_ulogic_vector(0 to 2);
+signal ac_an_local_checkstop   :  std_ulogic_vector(0 to 2);  
+signal an_ac_external_mchk     :  std_ulogic_vector(0 to 3);     
+
+signal gnd                     :  power_logic;
+signal vcs                     :  power_logic;
+signal vdd                     :  power_logic;
+signal vio                     :  power_logic;
+
+signal node_scom_dch_in         : std_ulogic;
+signal node_scom_cch_in         : std_ulogic;
+signal node_scom_dch_out        : std_ulogic;
+signal node_scom_cch_out        : std_ulogic;
+
+signal an_ac_camfence_en_dc  : std_ulogic;
+
+signal tidn                     : std_ulogic;
+signal tiup                     : std_ulogic;
+
+begin
+
+tidn <= '0';
+tiup <= '1';
+
+a2_nclk.clk <= clk;
+a2_nclk.clk2x <= clk2x;
+a2_nclk.clk4x <= '0';
+a2_nclk.sreset <= not reset_n;
+
+alt_disp           <= tidn;
+d_mode             <= tiup;
+delay_lclkr        <= tidn;
+mpw1_b             <= tidn;
+mpw2_b             <= tidn;
+scdis_b            <= tidn;
+an_ac_ccenable_dc  <= tiup;
+an_ac_scan_type_dc <= tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup;   
+
+an_ac_func_scan_in <= (others => '0');
+an_ac_regf_scan_in <= (others => '0');
+an_ac_bcfg_scan_in <= (others => '0');
+an_ac_dcfg_scan_in <= (others => '0');
+an_ac_abst_scan_in <= (others => '0');
+an_ac_gptr_scan_in <= '0';
+an_ac_repr_scan_in <= '0';
+an_ac_time_scan_in <= '0';
+an_ac_atpg_en_dc <= '0';
+an_ac_scan_dis_dc_b <= '1';
+an_ac_camfence_en_dc <= '0';
+an_ac_abist_start_test <= '0';
+an_ac_abist_mode_dc <= '0';
+an_ac_lbist_en_dc <= '0';
+an_ac_lbist_ac_mode_dc <= '0';
+an_ac_lbist_ip_dc <= '0';
+an_ac_fce_7 <= '0';
+an_ac_sg_7 <= '0';
+an_ac_gsd_test_acmode_dc <= '0';
+an_ac_lbist_ary_wrt_thru_dc <= '0';
+an_ac_gsd_test_enable_dc <= '0';
+an_ac_scan_diag_dc <= '0';
+an_ac_psro_enable_dc <= (others => '0');
+an_ac_ccflush_dc <= '0'; 
+
+an_ac_flh2l2_gate <= flh2l2_gate;
+an_ac_external_mchk <= ext_mchk;
+an_ac_checkstop <= ext_checkstop; 
+an_ac_debug_stop <= debug_stop;   
+an_ac_hang_pulse <= hang_pulse;
+thread_running <= ac_an_pm_thread_running;
+
+mchk           <= ac_an_machine_check;
+recov_err      <= ac_an_recov_err;
+checkstop      <= ac_an_local_checkstop;      
+
+an_ac_scom_sat_id <= scom_sat_id;
+node_scom_dch_in <= scom_dch_in;
+node_scom_cch_in <= scom_cch_in;
+scom_dch_out <= node_scom_dch_out;
+scom_cch_out <= node_scom_cch_out;
+
+an_ac_user_defined <= (others => '0');
+an_ac_req_spare_ctrl_a1 <= (others => '0');
+
+an_ac_icbi_ack <= '0';
+an_ac_icbi_ack_thread <= (others => '0');
+
+an_ac_back_inv <= '0';
+an_ac_back_inv_gs <= '0';
+an_ac_back_inv_local <= '0';
+an_ac_back_inv_lbit <= '0';
+an_ac_back_inv_ind <= '0';
+an_ac_back_inv_addr <= (others => '0');
+an_ac_back_inv_lpar_id <= (others => '0');
+an_ac_back_inv_target <= (others => '0');
+
+an_ac_reld_ditc <= '0';
+
+an_ac_dcr_act <= '0';
+an_ac_dcr_val <= '0';
+an_ac_dcr_read <= '0';
+an_ac_dcr_etid <= (others => '0');
+an_ac_dcr_data <= (others => '0');
+an_ac_dcr_done <= '0';
+
+an_ac_reset_1_complete <= '0';
+an_ac_reset_2_complete <= '0';
+an_ac_reset_3_complete <= '0';
+an_ac_reset_wd_complete <= '0';
+
+an_ac_sleep_en <= (others => '0'); 
+an_ac_malf_alert <= '0';
+
+acq: entity work.acq_soft(acq_soft) 
+  generic map(
+  error_width         => error_width,
+  expand_type         => expand_type,
+  expand_tlb_type     => expand_tlb_type,
+  extclass_width      => extclass_width,
+  inv_seq_width       => inv_seq_width,
+  lpid_width          => lpid_width,
+  pid_width           => pid_width,
+  ra_entry_width      => ra_entry_width,
+  real_addr_width     => real_addr_width,
+  threads             => threads,
+
+  xu_real_data_add    => xu_real_data_add,
+  st_data_32b_mode    => st_data_32b_mode,
+  ac_st_data_32b_mode => ac_st_data_32b_mode
+   )
+   port map (
+      an_ac_back_inv          => an_ac_back_inv,
+      an_ac_back_inv_addr     => an_ac_back_inv_addr,
+      an_ac_back_inv_lbit     => an_ac_back_inv_lbit,
+      an_ac_back_inv_gs       => an_ac_back_inv_gs,
+      an_ac_back_inv_ind      => an_ac_back_inv_ind,
+      an_ac_back_inv_local    => an_ac_back_inv_local,
+      an_ac_back_inv_lpar_id  => an_ac_back_inv_lpar_id,
+      an_ac_back_inv_target   => an_ac_back_inv_target,
+      an_ac_crit_interrupt    => crit_interrupt,
+      an_ac_dcr_act           => an_ac_dcr_act,
+      an_ac_dcr_val           => an_ac_dcr_val,
+      an_ac_dcr_read          => an_ac_dcr_read,
+      an_ac_dcr_etid          => an_ac_dcr_etid,
+      an_ac_dcr_data          => an_ac_dcr_data,
+      an_ac_dcr_done          => an_ac_dcr_done,
+      an_ac_ext_interrupt     => ext_interrupt,
+      an_ac_flh2l2_gate       => an_ac_flh2l2_gate,
+      an_ac_reld_core_tag     => an_ac_reld_core_tag,
+      an_ac_reld_data         => an_ac_reld_data,
+      an_ac_reld_data_vld     => an_ac_reld_data_vld,
+      an_ac_reld_ecc_err      => an_ac_reld_ecc_err,
+      an_ac_reld_ecc_err_ue   => an_ac_reld_ecc_err_ue,
+      an_ac_reld_qw           => an_ac_reld_qw,
+      an_ac_reld_data_coming  => an_ac_reld_data_coming,
+      an_ac_reld_ditc         => an_ac_reld_ditc,
+      an_ac_reld_crit_qw      => an_ac_reld_crit_qw,
+      an_ac_reld_l1_dump      => an_ac_reld_l1_dump,
+      an_ac_regf_scan_in      => an_ac_regf_scan_in,
+      an_ac_req_ld_pop        => an_ac_req_ld_pop,
+      an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1,
+      an_ac_req_st_gather     => an_ac_req_st_gather,
+      an_ac_req_st_pop        => an_ac_req_st_pop,
+      an_ac_req_st_pop_thrd   => an_ac_req_st_pop_thrd,
+      an_ac_reservation_vld   => an_ac_reservation_vld,
+      an_ac_sleep_en          => an_ac_sleep_en,
+      an_ac_stcx_complete     => an_ac_stcx_complete,
+      an_ac_stcx_pass         => an_ac_stcx_pass,
+      an_ac_sync_ack          => an_ac_sync_ack,
+      an_ac_icbi_ack          => an_ac_icbi_ack,
+      an_ac_icbi_ack_thread   => an_ac_icbi_ack_thread,
+      a2_nclk                 => a2_nclk,
+      an_ac_abist_mode_dc     => an_ac_abist_mode_dc,
+      an_ac_abist_start_test  => an_ac_abist_start_test,
+      an_ac_abst_scan_in      => an_ac_abst_scan_in,
+      an_ac_rtim_sl_thold_7   => thold,
+      an_ac_ary_nsl_thold_7   => thold,
+      an_ac_func_nsl_thold_7  => thold,
+      an_ac_func_sl_thold_7   => thold,       
+      an_ac_atpg_en_dc        => an_ac_atpg_en_dc,
+      an_ac_bcfg_scan_in      => an_ac_bcfg_scan_in,
+      an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc,
+      an_ac_ccenable_dc       => an_ac_ccenable_dc,
+      an_ac_ccflush_dc        => an_ac_ccflush_dc,
+      an_ac_coreid            => core_id,
+      an_ac_lbist_ip_dc       => an_ac_lbist_ip_dc,    
+      an_ac_malf_alert        => an_ac_malf_alert,        
+      an_ac_reset_1_complete  => an_ac_reset_1_complete,
+      an_ac_reset_2_complete  => an_ac_reset_2_complete,
+      an_ac_reset_3_complete  => an_ac_reset_3_complete,
+      an_ac_reset_wd_complete => an_ac_reset_wd_complete,
+      an_ac_dcfg_scan_in      => an_ac_dcfg_scan_in,
+      an_ac_debug_stop        => an_ac_debug_stop,
+      an_ac_external_mchk     => an_ac_external_mchk,
+      an_ac_fce_7             => an_ac_fce_7,
+     
+      an_ac_func_scan_in      => an_ac_func_scan_in,
+      an_ac_gptr_scan_in      => an_ac_gptr_scan_in,
+      an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc,
+      an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc,
+      an_ac_hang_pulse        => an_ac_hang_pulse,
+      an_ac_lbist_en_dc       => an_ac_lbist_en_dc,
+      an_ac_lbist_ac_mode_dc  => an_ac_lbist_ac_mode_dc,
+      an_ac_perf_interrupt    => perf_interrupt,
+      an_ac_pm_thread_stop    => thread_stop,
+      an_ac_psro_enable_dc    => an_ac_psro_enable_dc,
+      an_ac_repr_scan_in      => an_ac_repr_scan_in,
+      an_ac_scan_diag_dc      => an_ac_scan_diag_dc,
+      an_ac_scan_dis_dc_b     => an_ac_scan_dis_dc_b,
+      an_ac_scan_type_dc      => an_ac_scan_type_dc,
+      an_ac_scom_cch          => node_scom_cch_in,     
+      an_ac_scom_dch          => node_scom_dch_in,    
+      an_ac_scom_sat_id       => an_ac_scom_sat_id,
+      an_ac_sg_7              => an_ac_sg_7,
+      an_ac_checkstop         => an_ac_checkstop,
+      an_ac_tb_update_enable  => tb_update_enable,
+      an_ac_tb_update_pulse   => tb_update_pulse,
+      an_ac_time_scan_in      => an_ac_time_scan_in,
+      ac_an_back_inv_reject   => ac_an_back_inv_reject,
+      ac_an_box_empty         => ac_an_box_empty,
+      ac_an_lpar_id           => ac_an_lpar_id,
+      ac_an_machine_check     => ac_an_machine_check,
+      ac_an_power_managed     => ac_an_power_managed,
+      ac_an_req               => ac_an_req,
+      ac_an_req_endian        => ac_an_req_endian,
+      ac_an_req_ld_core_tag   => ac_an_req_ld_core_tag,
+      ac_an_req_ld_xfr_len    => ac_an_req_ld_xfr_len,
+      ac_an_req_pwr_token     => ac_an_req_pwr_token,
+      ac_an_req_ra            => ac_an_req_ra,
+      ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0,
+      ac_an_req_thread        => ac_an_req_thread,
+      ac_an_req_ttype         => ac_an_req_ttype,
+      ac_an_req_user_defined  => ac_an_req_user_defined,
+      ac_an_req_wimg_g        => ac_an_req_wimg_g,
+      ac_an_req_wimg_i        => ac_an_req_wimg_i,
+      ac_an_req_wimg_m        => ac_an_req_wimg_m,
+      ac_an_req_wimg_w        => ac_an_req_wimg_w,
+      ac_an_reld_ditc_pop     => ac_an_reld_ditc_pop,
+      ac_an_rvwinkle_mode     => ac_an_rvwinkle_mode,
+      ac_an_st_byte_enbl      => ac_an_st_byte_enbl,
+      ac_an_st_data           => ac_an_st_data,
+      ac_an_st_data_pwr_token => ac_an_st_data_pwr_token,
+      ac_an_fu_bypass_events  => ac_an_fu_bypass_events,
+      ac_an_iu_bypass_events  => ac_an_iu_bypass_events,
+      ac_an_mm_bypass_events  => ac_an_mm_bypass_events,
+      ac_an_debug_bus         => ac_an_debug_bus,
+      ac_an_event_bus         => ac_an_event_bus,
+      ac_an_trace_triggers    => ac_an_trace_triggers,
+      ac_an_abist_done_dc     => ac_an_abist_done_dc,
+      ac_an_abst_scan_out     => ac_an_abst_scan_out,
+      ac_an_bcfg_scan_out     => ac_an_bcfg_scan_out,
+      ac_an_dcfg_scan_out     => ac_an_dcfg_scan_out,
+      ac_an_debug_trigger     => ac_an_debug_trigger, 
+      ac_an_func_scan_out     => ac_an_func_scan_out,
+      ac_an_gptr_scan_out     => ac_an_gptr_scan_out,
+      ac_an_pm_thread_running => ac_an_pm_thread_running,
+      ac_an_psro_ringsig      => ac_an_psro_ringsig,
+      ac_an_recov_err         => ac_an_recov_err,
+      ac_an_repr_scan_out     => ac_an_repr_scan_out,
+      ac_an_scom_cch          => node_scom_cch_out,    
+      ac_an_scom_dch          => node_scom_dch_out,
+      ac_an_time_scan_out     => ac_an_time_scan_out,
+      ac_an_special_attn      => ac_an_special_attn,
+      ac_an_checkstop         => ac_an_checkstop,
+      ac_an_local_checkstop   => ac_an_local_checkstop,
+      ac_an_dcr_act           => ac_an_dcr_act,
+      ac_an_dcr_val           => ac_an_dcr_val,
+      ac_an_dcr_read          => ac_an_dcr_read,
+      ac_an_dcr_user          => ac_an_dcr_user,
+      ac_an_dcr_etid          => ac_an_dcr_etid,
+      ac_an_dcr_addr          => ac_an_dcr_addr,
+      ac_an_dcr_data          => ac_an_dcr_data,
+      an_ac_camfence_en_dc    => an_ac_camfence_en_dc, 
+  
+      gnd                     => gnd,
+      vcs                     => vcs,
+      vdd                     => vdd
+   ); 
+   
+a2l2_axi: entity work.a2l2_axi(a2l2_axi) 
+generic map(
+     C_M00_AXI_ID_WIDTH	               => C_M00_AXI_ID_WIDTH,
+     C_M00_AXI_ADDR_WIDTH              => C_M00_AXI_ADDR_WIDTH,
+	  C_M00_AXI_DATA_WIDTH	            => C_M00_AXI_DATA_WIDTH,
+     C_M00_AXI_AWUSER_WIDTH	         => C_M00_AXI_AWUSER_WIDTH,
+     C_M00_AXI_ARUSER_WIDTH	         => C_M00_AXI_ARUSER_WIDTH, 
+     C_M00_AXI_WUSER_WIDTH	            => C_M00_AXI_WUSER_WIDTH,
+     C_M00_AXI_RUSER_WIDTH	            => C_M00_AXI_RUSER_WIDTH,
+     C_M00_AXI_BUSER_WIDTH	            => C_M00_AXI_BUSER_WIDTH
+     )
+port map(
+		clk                     => clk,
+		reset_n                 => reset_n,
+		err                     => a2l2_axi_err,
+      ac_an_req               => ac_an_req,
+      ac_an_req_endian        => ac_an_req_endian,
+      ac_an_req_ld_core_tag   => ac_an_req_ld_core_tag,
+      ac_an_req_ld_xfr_len    => ac_an_req_ld_xfr_len,
+      ac_an_req_pwr_token     => ac_an_req_pwr_token,
+      ac_an_req_ra            => ac_an_req_ra,
+      ac_an_req_thread        => ac_an_req_thread,
+      ac_an_req_ttype         => ac_an_req_ttype,
+      ac_an_req_user_defined  => ac_an_req_user_defined,
+      ac_an_req_wimg_g        => ac_an_req_wimg_g,
+      ac_an_req_wimg_i        => ac_an_req_wimg_i,
+      ac_an_req_wimg_m        => ac_an_req_wimg_m,
+      ac_an_req_wimg_w        => ac_an_req_wimg_w,
+      ac_an_st_byte_enbl      => ac_an_st_byte_enbl,
+      ac_an_st_data           => ac_an_st_data,
+      ac_an_st_data_pwr_token => ac_an_st_data_pwr_token,     
+      an_ac_reld_core_tag     => an_ac_reld_core_tag,
+      an_ac_reld_data         => an_ac_reld_data,
+      an_ac_reld_data_vld     => an_ac_reld_data_vld,
+      an_ac_reld_ecc_err      => an_ac_reld_ecc_err,
+      an_ac_reld_ecc_err_ue   => an_ac_reld_ecc_err_ue,
+      an_ac_reld_qw           => an_ac_reld_qw,
+      an_ac_reld_data_coming  => an_ac_reld_data_coming,
+      an_ac_reld_crit_qw      => an_ac_reld_crit_qw,
+      an_ac_reld_l1_dump      => an_ac_reld_l1_dump,
+      an_ac_req_ld_pop        => an_ac_req_ld_pop,
+      an_ac_req_st_pop        => an_ac_req_st_pop,
+      an_ac_req_st_gather     => an_ac_req_st_gather,      
+      an_ac_req_st_pop_thrd   => an_ac_req_st_pop_thrd,
+      an_ac_reservation_vld   => an_ac_reservation_vld,      
+      an_ac_stcx_complete     => an_ac_stcx_complete,
+      an_ac_stcx_pass         => an_ac_stcx_pass,
+      an_ac_sync_ack          => an_ac_sync_ack,
+		m00_axi_awid	 =>  m00_axi_awid,
+		m00_axi_awaddr	 =>  m00_axi_awaddr,
+		m00_axi_awlen	 =>  m00_axi_awlen,
+		m00_axi_awsize	 =>  m00_axi_awsize,
+		m00_axi_awburst	 =>  m00_axi_awburst,
+		m00_axi_awlock	 =>  m00_axi_awlock,
+		m00_axi_awcache	 =>  m00_axi_awcache,
+		m00_axi_awprot	 =>  m00_axi_awprot,
+		m00_axi_awqos	 =>  m00_axi_awqos,
+		m00_axi_awuser	 =>  m00_axi_awuser,
+		m00_axi_awvalid	 =>  m00_axi_awvalid,
+		m00_axi_awready	 =>  m00_axi_awready,
+		m00_axi_wdata	 =>  m00_axi_wdata,
+		m00_axi_wstrb	 =>  m00_axi_wstrb,
+		m00_axi_wlast	 =>  m00_axi_wlast,
+		m00_axi_wuser	 =>  m00_axi_wuser,
+		m00_axi_wvalid	 =>  m00_axi_wvalid,
+		m00_axi_wready	 =>  m00_axi_wready,
+		m00_axi_bid	 =>  m00_axi_bid,
+		m00_axi_bresp	 =>  m00_axi_bresp,
+		m00_axi_buser	 =>  m00_axi_buser,
+		m00_axi_bvalid	 =>  m00_axi_bvalid,
+		m00_axi_bready	 =>  m00_axi_bready,
+		m00_axi_arid	 =>  m00_axi_arid,
+		m00_axi_araddr	 =>  m00_axi_araddr,
+		m00_axi_arlen	 =>  m00_axi_arlen,
+		m00_axi_arsize	 =>  m00_axi_arsize,
+		m00_axi_arburst	 =>  m00_axi_arburst,
+		m00_axi_arlock	 =>  m00_axi_arlock,
+		m00_axi_arcache	 =>  m00_axi_arcache,
+		m00_axi_arprot	 =>  m00_axi_arprot,
+		m00_axi_arqos	 =>  m00_axi_arqos,
+		m00_axi_aruser	 =>  m00_axi_aruser,
+		m00_axi_arvalid	 =>  m00_axi_arvalid,
+		m00_axi_arready	 =>  m00_axi_arready,
+		m00_axi_rid	 =>  m00_axi_rid,
+		m00_axi_rdata	 =>  m00_axi_rdata,
+		m00_axi_rresp	 =>  m00_axi_rresp,
+		m00_axi_rlast	 =>  m00_axi_rlast,
+		m00_axi_ruser	 =>  m00_axi_ruser,
+		m00_axi_rvalid	 =>  m00_axi_rvalid,
+		m00_axi_rready	 =>  m00_axi_rready
+	   );
+
+end a2x_axi;

rel/build/ip_user/a2x_axi/a2x_axi/src/work/a2x_pkg.vhdl

@@ -0,0 +1,501 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package a2x_pkg is 
+
+attribute dont_touch : string;
+
+constant c_ld_queue_size : integer := 4;   
+constant c_ld_queue_bits : integer := 2;  
+constant c_st_queue_size : integer := 16;
+constant c_st_queue_bits : integer := 4;
+constant c_max_pointer : integer := 2;
+
+
+constant IFETCH    : std_logic_vector(0 to 5) := "000000";
+constant IFETCHPRE : std_logic_vector(0 to 5) := "000001";
+constant LOAD      : std_logic_vector(0 to 5) := "001000";
+constant STORE     : std_logic_vector(0 to 5) := "100000";
+
+constant LARX      : std_logic_vector(0 to 5) := "001001";
+constant LARXHINT  : std_logic_vector(0 to 5) := "001011";
+constant STCX      : std_logic_vector(0 to 5) := "101011";
+
+constant LWSYNC    : std_logic_vector(0 to 5) := "101010";
+constant HWSYNC    : std_logic_vector(0 to 5) := "101011";
+constant MBAR      : std_logic_vector(0 to 5) := "110010";
+constant TLBSYNC   : std_logic_vector(0 to 5) := "111010";
+
+constant DCBI      : std_logic_vector(0 to 5) := "111111";
+
+
+function or_reduce(slv: in std_logic_vector) return std_logic;
+function and_reduce(slv: in std_logic_vector) return std_logic;
+function inc(a: in std_logic_vector) return std_logic_vector;
+function inc(a: in std_logic_vector; b: in integer) return std_logic_vector;
+function dec(a: in std_logic_vector) return std_logic_vector;
+function eq(a: in std_logic_vector; b: in integer) return boolean;
+function eq(a: in std_logic_vector; b: in integer) return std_logic;
+function eq(a: in std_logic_vector; b: in std_logic_vector) return boolean;
+function eq(a: in std_logic_vector; b: in std_logic_vector) return std_logic;
+function gt(a: in std_logic_vector; b: in integer) return boolean;
+function gt(a: in std_logic_vector; b: in std_logic_vector) return boolean;
+function gt(a: in std_logic_vector; b: in std_logic_vector) return std_logic;
+function nz(a: in std_logic_vector) return boolean;
+function nz(a: in std_logic_vector) return std_logic;
+function b(a: in boolean) return std_logic;
+function b(a: in std_logic) return boolean;
+
+function clog2(n : in integer) return integer;            
+function conv_integer(a: in std_logic_vector) return integer; 
+function max(a: in integer; b: in integer) return integer;
+
+function right_one(a: in std_logic_vector) return std_logic_vector;
+function gate_and(a: in std_logic; b: in std_logic_vector) return std_logic_vector;
+function rotl(a: in std_logic_vector; b: in integer) return std_logic_vector;
+function rotl(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector;
+function rotr(a: in std_logic_vector; b: in integer) return std_logic_vector;
+function rotr(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector;
+function enc(a: in std_logic_vector) return std_logic_vector;
+function enc(a: in std_logic_vector; b: in integer) return std_logic_vector;
+
+subtype RADDR is std_logic_vector(64-42 to 63);
+subtype LINEADDR is std_logic_vector(64-42 to 59);
+
+type A2L2REQUEST is record
+	valid                      : std_logic;                       
+   sent                       : std_logic;                       
+   data                       : std_logic;                       
+	dseq                       : std_logic_vector(0 to 2);        
+   endian                     : std_logic;
+   tag                        : std_logic_vector(0 to 4);
+   len                        : std_logic_vector(0 to 2);
+   ra                         : RADDR;   
+   thread                     : std_logic_vector(0 to 1);
+   spec                       : std_logic;   
+   ditc                       : std_logic;
+   ttype                      : std_logic_vector(0 to 5);
+   user                       : std_logic_vector(0 to 3);
+   wimg                       : std_logic_vector(0 to 3);
+   hwsync                     : std_logic;
+end record;
+
+type A2L2STOREDATA is record
+   data                       : std_logic_vector(0 to 127);
+   be                         : std_logic_vector(0 to 15);   
+end record;
+	
+type A2L2RELOAD is record
+   coming                     : std_logic;	
+   valid                      : std_logic;
+   tag                        : std_logic_vector(0 to 4);
+   data                       : std_logic_vector(0 to 127);
+   ee                         : std_logic;
+   ue                         : std_logic;
+   qw                         : std_logic_vector(57 to 59);
+   crit                       : std_logic;
+   dump                       : std_logic;
+end record;
+
+type A2L2STATUS is record
+   ld_pop                     : std_logic;
+   st_pop                     : std_logic;
+   st_pop_thrd                : std_logic_vector(0 to 2);
+   gather                     : std_logic;      
+   res_valid                  : std_logic_vector(0 to 3);
+   stcx_complete              : std_logic_vector(0 to 3);
+   stcx_pass                  : std_logic_vector(0 to 3);
+   sync_ack                   : std_logic_vector(0 to 3);	
+end record;	
+
+type A2L2RESV is record
+   valid                      : std_logic;
+   ra                         : LINEADDR;
+end record;
+	
+type LOADQUEUE is array(0 to c_ld_queue_size-1) of A2L2REQUEST;
+type LOADDATAQUEUE is array(0 to 63) of std_logic_vector(0 to 31);   
+type LOADQUEUEDEP is array(0 to c_ld_queue_size-1) of std_logic_vector(0 to c_st_queue_bits);   
+type STOREQUEUE is array(0 to c_st_queue_size-1) of A2L2REQUEST;	
+type STOREDATAQUEUE is array(0 to c_st_queue_size-1) of A2L2STOREDATA;
+type STOREQUEUEDEP is array(0 to c_st_queue_size-1) of std_logic_vector(0 to c_ld_queue_bits);  
+type RESVARRAY is array(0 to 3) of A2L2RESV;
+
+function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic;
+
+function mux_queue(a: in LOADQUEUE; b: in std_logic_vector) return A2L2REQUEST;
+function mux_queue(a: in LOADDATAQUEUE; b: in integer) return std_logic_vector;
+function mux_queue(a: in LOADDATAQUEUE; b: in std_logic_vector) return std_logic_vector;
+function mux_queue(a: in LOADQUEUEDEP; b: in std_logic_vector) return std_logic_vector;
+function mux_queue(a: in STOREQUEUE; b: in std_logic_vector) return A2L2REQUEST;
+function mux_queue(a: in STOREDATAQUEUE; b: in std_logic_vector) return A2L2STOREDATA;
+function mux_queue(a: in STOREQUEUEDEP; b: in std_logic_vector) return std_logic_vector;
+
+end a2x_pkg;
+
+package body a2x_pkg is 
+
+
+function or_reduce(slv: in std_logic_vector) return std_logic is
+  variable res: std_logic := '0';
+begin
+  for i in slv'range loop
+    res := res or slv(i);
+  end loop;
+  return res;
+end function;
+
+function and_reduce(slv: in std_logic_vector) return std_logic is
+  variable res: std_logic := '1';
+begin
+  for i in slv'range loop
+    res := res and slv(i);
+  end loop;
+  return res;
+end function;
+
+function inc(a: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to a'length-1);
+begin
+  res := std_logic_vector(unsigned(a) + 1);
+  return res;
+end function;
+
+function inc(a: in std_logic_vector; b: in integer) return std_logic_vector is
+  variable res: std_logic_vector(0 to a'length-1);
+begin
+  res := std_logic_vector(unsigned(a) + b);
+  return res;
+end function;
+
+function dec(a: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to a'length-1);
+begin
+  res := std_logic_vector(unsigned(a) - 1);
+  return res;
+end function;
+
+function eq(a: in std_logic_vector; b: in integer) return boolean is
+  variable res: boolean;
+begin
+  res := unsigned(a) = b;
+  return res;
+end function;
+
+function eq(a: in std_logic_vector; b: in integer) return std_logic is
+  variable res: std_logic;
+begin
+  if unsigned(a) = b then
+   res := '1';
+  else
+   res := '0';
+  end if;
+  return res;
+end function;
+
+function eq(a: in std_logic_vector; b: in std_logic_vector) return boolean is
+  variable res: boolean;
+begin
+  res := unsigned(a) = unsigned(b);
+  return res;
+end function;
+
+function eq(a: in std_logic_vector; b: in std_logic_vector) return std_logic is
+  variable res: std_logic;
+begin
+  if unsigned(a) = unsigned(b) then
+    res := '1';
+  else
+    res := '0';
+  end if;
+  return res;
+end function;
+
+function gt(a: in std_logic_vector; b: in integer) return boolean is
+  variable res: boolean;
+begin
+  res := unsigned(a) > b;
+  return res;
+end function;
+
+function gt(a: in std_logic_vector; b: in std_logic_vector) return boolean is
+  variable res: boolean;
+begin
+  res := unsigned(a) > unsigned(b);
+  return res;
+end function;
+
+function gt(a: in std_logic_vector; b: in std_logic_vector) return std_logic is
+  variable res: std_logic;
+begin
+  if unsigned(a) > unsigned(b) then
+    res := '1';
+  else
+    res := '0';
+  end if;
+  return res;
+end function;
+
+function nz(a: in std_logic_vector) return boolean is
+  variable res: boolean;
+begin
+  res := unsigned(a) /= 0;
+  return res;
+end function;
+
+function nz(a: in std_logic_vector) return std_logic is
+  variable res: std_logic;
+begin
+  if unsigned(a) /= 0 then
+    res := '1';
+  else
+    res := '0';
+  end if;
+  return res;
+end function;
+
+function b(a: in boolean) return std_logic is
+  variable res: std_logic;
+begin
+  if a then
+    res := '1';
+  else
+    res := '0';
+  end if;
+  return res;
+end function;
+
+function b(a: in std_logic) return boolean is
+  variable res: boolean;
+begin
+  if a = '1' then
+    res := true;
+  else
+    res := false;
+  end if;
+  return res;
+end function;
+
+function right_one(a: in std_logic_vector) return std_logic_vector is
+  variable res : std_logic_vector(0 to a'length - 1);
+begin
+  for i in a'length - 1 downto 0 loop                        
+    if a(i) = '1' then
+      res(i) := '1';
+      exit;
+    end if; 
+  end loop;
+  return res;
+end function;
+
+function rotl(a: in std_logic_vector; b: in integer) return std_logic_vector is
+  variable res : std_logic_vector(0 to a'length - 1);
+begin
+  res := a(b to a'length - 1) & a(0 to b - 1);
+  return res;
+end function;
+
+function rotl(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector is
+  variable res : std_logic_vector(0 to a'length - 1) := a;
+  variable c : integer := conv_integer(b);
+  variable i : integer;
+begin
+  for i in 0 to a'length - 1 loop  
+    if (i + c < a'length) then
+       res(i) := a(i + c);
+    else
+       res(i) := a(i + c - a'length);    
+    end if;
+  end loop;
+  return res;
+end function;
+
+function rotr(a: in std_logic_vector; b: in integer) return std_logic_vector is
+  variable res: std_logic_vector(0 to a'length - 1);
+begin
+  res := a(a'length - b to a'length - 1) & a(0 to a'length - b - 1);
+  return res;
+end function;
+
+function rotr(a: in std_logic_vector; b: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to a'length - 1);
+  variable c : integer := conv_integer(b);
+begin
+  for i in 0 to a'length - 1 loop  
+    if (a'length - c + i < a'length) then
+       res(i) := a(a'length - c + i);
+    else
+       res(i) := a(-c + i);    
+    end if;
+  end loop;
+  return res;
+end function;
+
+function gate_and(a: in std_logic; b: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to b'length-1);
+begin
+  if a = '1' then
+     res := b;
+  else   
+     res := (others => '0');  
+  end if;
+  return res;
+end function;		
+
+function enc(a: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to clog2(a'length)-1) := (others => '0');
+begin
+  for i in 0 to a'length - 1 loop  
+     if (a(i) = '1') then
+        res := std_logic_vector(to_unsigned(i, res'length));
+        exit;
+     end if;
+  end loop;
+  return res;
+end function;		
+
+function enc(a: in std_logic_vector; b: in integer) return std_logic_vector is
+  variable res: std_logic_vector(0 to b-1) := (others => '0');
+begin
+  for i in 0 to a'length - 1 loop  
+     if (a(i) = '1') then
+        res := std_logic_vector(to_unsigned(i, res'length));
+        exit;
+     end if;
+  end loop;
+  return res;
+end function;		
+
+function conv_integer(a: in std_logic_vector) return integer is
+  variable res: integer;
+begin
+  res := to_integer(unsigned(a));
+  return res; 
+end function;
+
+function max(a: in integer; b: in integer) return integer is
+  variable res : integer;
+begin
+  if (a > b) then
+     res := a;
+  else
+     res := b;
+  end if;
+  return res;
+end function;
+
+function mux_queue(a: in LOADQUEUE; b: in std_logic_vector) return A2L2REQUEST is
+  variable res: A2L2REQUEST;
+begin
+  res := a(conv_integer(b));
+  return res;
+end function;
+
+function mux_queue(a: in LOADDATAQUEUE; b: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to a(0)'length-1);
+begin
+  res := a(conv_integer(b));
+  return res;
+end function;
+
+function mux_queue(a: in LOADDATAQUEUE; b: in integer) return std_logic_vector is
+  variable res: std_logic_vector(0 to a(0)'length-1);
+begin
+  res := a(b);
+  return res;
+end function;
+
+function mux_queue(a: in LOADQUEUEDEP; b: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to a(0)'length-1);
+begin
+  res := a(conv_integer(b));
+  return res;
+end function;
+
+
+function mux_queue(a: in STOREQUEUE; b: in std_logic_vector) return A2L2REQUEST is
+  variable res: A2L2REQUEST;
+begin
+  res := a(conv_integer(b));
+  return res;
+end function;
+
+function mux_queue(a: in STOREDATAQUEUE; b: in std_logic_vector) return A2L2STOREDATA is
+  variable res: A2L2STOREDATA;
+begin
+  res := a(conv_integer(b));
+  return res;
+end function;
+
+function mux_queue(a: in STOREQUEUEDEP; b: in std_logic_vector) return std_logic_vector is
+  variable res: std_logic_vector(0 to a(0)'length-1);
+begin
+  res := a(conv_integer(b));
+  return res;
+end function;
+
+function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic is
+  variable res: std_logic := '0';
+  variable a_start, a_end, b_start, b_end : unsigned(0 to a.ra'length-1);
+begin
+   a_start := unsigned(a.ra);
+   a_end := unsigned(a.ra) + unsigned(a.len);
+   b_start := unsigned(b.ra);
+   b_end := unsigned(b.ra) + unsigned(b.len);
+   if ((a.valid = '1') and (a.spec = '0') and (b.valid = '1') and (b.spec = '0')) then       
+      if ((a_start >= b_start) and (a_start <= b_end)) then
+         res := '1';
+      elsif ((a_end >= b_start) and (a_end <= b_end)) then
+         res := '1';
+      end if;
+   end if;
+   return res;
+end function;
+
+function clog2(n : in integer) return integer is            
+   variable i : integer;
+   variable j : integer := n - 1;
+	variable res : integer := 1;                                       
+begin                                                                   
+   for i in 0 to 31 loop
+      if (j > 1) then
+         j := j / 2;
+         res := res + 1;
+      else
+         exit;
+      end if;
+   end loop;
+   return res;        	                                              
+end;                                                                    
+                                                                                    
+end a2x_pkg;
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add.vhdl

@@ -0,0 +1,580 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+entity fuq_add is
+generic(       expand_type               : integer := 2  ); 
+port(
+
+       vdd                                       :inout power_logic;
+       gnd                                       :inout power_logic;
+       clkoff_b                                  :in   std_ulogic; 
+       act_dis                                   :in   std_ulogic; 
+       flush                                     :in   std_ulogic; 
+       delay_lclkr                               :in   std_ulogic_vector(3 to 4); 
+       mpw1_b                                    :in   std_ulogic_vector(3 to 4); 
+       mpw2_b                                    :in   std_ulogic_vector(0 to 0); 
+       sg_1                                      :in   std_ulogic;
+       thold_1                                   :in   std_ulogic;
+       fpu_enable                                :in   std_ulogic; 
+       nclk                                      :in   clk_logic;
+
+       f_add_si                  :in  std_ulogic; 
+       f_add_so                  :out std_ulogic; 
+       ex1_act_b                 :in  std_ulogic; 
+
+       f_sa3_ex3_s                :in  std_ulogic_vector(0  to 162); 
+       f_sa3_ex3_c                :in  std_ulogic_vector(53 to 161); 
+
+       f_alg_ex3_frc_sel_p1       :in  std_ulogic; 
+       f_alg_ex3_sticky           :in  std_ulogic; 
+       f_alg_ex2_effsub_eac_b     :in  std_ulogic; 
+       f_alg_ex2_prod_z           :in  std_ulogic; 
+
+       f_pic_ex3_is_gt            :in  std_ulogic; 
+       f_pic_ex3_is_lt            :in  std_ulogic; 
+       f_pic_ex3_is_eq            :in  std_ulogic; 
+       f_pic_ex3_is_nan           :in  std_ulogic; 
+       f_pic_ex3_cmp_sgnpos       :in  std_ulogic; 
+       f_pic_ex3_cmp_sgnneg       :in  std_ulogic; 
+
+       f_add_ex4_res              :out std_ulogic_vector(0 to 162); 
+       f_add_ex4_flag_nan         :out std_ulogic;                  
+       f_add_ex4_flag_gt          :out std_ulogic;                  
+       f_add_ex4_flag_lt          :out std_ulogic;                  
+       f_add_ex4_flag_eq          :out std_ulogic;                  
+       f_add_ex4_fpcc_iu          :out std_ulogic_vector(0 to 3);   
+       f_add_ex4_sign_carry       :out std_ulogic;                  
+       f_add_ex4_to_int_ovf_wd    :out std_ulogic_vector(0 to 1);   
+       f_add_ex4_to_int_ovf_dw    :out std_ulogic_vector(0 to 1);   
+       f_add_ex4_sticky           :out std_ulogic                   
+
+);
+
+
+
+end fuq_add; 
+
+architecture fuq_add of fuq_add is
+
+  constant tiup : std_ulogic := '1';
+  constant tidn : std_ulogic := '0';
+
+
+  signal thold_0_b, thold_0    :std_ulogic;
+  signal sg_0, forcee        :std_ulogic;
+
+  signal ex1_act      :std_ulogic;
+  signal ex2_act      :std_ulogic;
+  signal ex3_act   :std_ulogic;
+
+  signal act_si         :std_ulogic_vector(0 to 8);
+  signal act_so         :std_ulogic_vector(0 to 8);
+  signal ex4_res_so     :std_ulogic_vector(0 to 162);                      
+  signal ex4_res_si     :std_ulogic_vector(0 to 162);                    
+  signal ex4_cmp_so     :std_ulogic_vector(0 to 9);                      
+  signal ex4_cmp_si     :std_ulogic_vector(0 to 9);                    
+
+  signal spare_unused   :std_ulogic_vector(0 to 3);
+
+
+  signal ex3_s           :std_ulogic_vector( 0 to 162);
+  signal ex3_c           :std_ulogic_vector(53 to 161);
+
+  signal ex3_flag_nan       :std_ulogic;    
+  signal ex3_flag_gt        :std_ulogic;   
+  signal ex3_flag_lt        :std_ulogic;   
+  signal ex3_flag_eq        :std_ulogic;   
+  signal ex3_sign_carry     :std_ulogic; 
+
+  signal ex3_inc_all1       :std_ulogic;
+  signal ex3_inc_byt_c_glb  :std_ulogic_vector(1 to 6);
+  signal ex3_inc_byt_c_glb_b  :std_ulogic_vector(1 to 6);
+  signal ex3_inc_p1         :std_ulogic_vector(0 to 52);
+  signal ex3_inc_p0         :std_ulogic_vector(0 to 52);
+
+  signal ex3_s_p0           :std_ulogic_vector(53 to 162);
+  signal ex3_s_p1           :std_ulogic_vector(53 to 162);
+  signal ex3_res            :std_ulogic_vector(0 to 162);
+
+  signal ex2_effsub         :std_ulogic;
+  signal ex3_effsub         :std_ulogic;
+
+  signal ex2_effadd_npz     :std_ulogic;
+  signal ex2_effsub_npz     :std_ulogic;
+  signal ex3_effsub_npz     :std_ulogic;
+  signal ex3_effadd_npz     :std_ulogic;
+  signal ex3_flip_inc_p0    :std_ulogic;
+  signal ex3_flip_inc_p1    :std_ulogic;
+  signal ex3_inc_sel_p0     :std_ulogic;
+  signal ex3_inc_sel_p1     :std_ulogic;
+
+  signal ex4_res, ex4_res_b , ex4_res_l2_b :std_ulogic_vector(0 to 162) ;
+  signal ex4_flag_nan_b       :std_ulogic;    
+  signal ex4_flag_gt_b        :std_ulogic;   
+  signal ex4_flag_lt_b        :std_ulogic;   
+  signal ex4_flag_eq_b        :std_ulogic;   
+  signal ex4_fpcc_iu_b        :std_ulogic_vector(0 to 3) ;
+  signal ex4_sign_carry_b     :std_ulogic; 
+  signal ex4_sticky_b         :std_ulogic;
+
+  signal ex3_g16  :std_ulogic_vector(0 to 6);
+  signal ex3_t16  :std_ulogic_vector(0 to 6);
+  signal ex3_g128, ex3_t128, ex3_g128_b, ex3_t128_b :std_ulogic_vector(1 to 6);
+  signal ex3_inc_byt_c_b  :std_ulogic_vector(0 to 6);
+  signal ex3_eac_sel_p0n, ex3_eac_sel_p0,  ex3_eac_sel_p1 : std_ulogic_vector(0 to 6);
+  signal ex3_flag_nan_cp1, ex3_flag_gt_cp1, ex3_flag_lt_cp1, ex3_flag_eq_cp1 :std_ulogic;
+  signal add_ex4_d1clk , add_ex4_d2clk  :std_ulogic ;
+  signal add_ex4_lclk :clk_logic ;
+
+ signal ex3_s_p0n, ex3_res_p0n_b, ex3_res_p0_b, ex3_res_p1_b :std_ulogic_vector(53 to 162);
+ signal ex3_inc_p0_x, ex3_inc_p1_x, ex3_incx_p0_b, ex3_incx_p1_b :std_ulogic_vector(0 to 52);
+ signal ex3_sel_a1, ex3_sel_a2, ex3_sel_a3 :std_ulogic_vector(53 to 162);
+
+
+
+
+
+
+
+
+
+
+
+begin
+
+
+    thold_reg_0:  tri_plat  generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,  
+         flush     => flush ,
+         din(0)    => thold_1,   
+         q(0)      => thold_0  ); 
+    
+    sg_reg_0:  tri_plat     generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,
+         flush     => flush ,
+         din(0)    => sg_1  ,     
+         q(0)      => sg_0  );   
+
+    lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
+        clkoff_b     => clkoff_b,
+        thold        => thold_0,  
+        sg           => sg_0,
+        act_dis      => act_dis,
+        forcee => forcee,
+        thold_b      => thold_0_b );
+
+
+    ex1_act        <= not ex1_act_b ;
+    ex2_effsub     <= not f_alg_ex2_effsub_eac_b ;
+    ex2_effsub_npz <= not f_alg_ex2_effsub_eac_b and not  f_alg_ex2_prod_z;
+    ex2_effadd_npz <=     f_alg_ex2_effsub_eac_b and not  f_alg_ex2_prod_z;
+
+    act_lat:  tri_rlmreg_p generic map (width=> 9, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(3)  ,
+        mpw1_b           => mpw1_b(3)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        nclk             => nclk,
+        act              => fpu_enable,
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        vd               => vdd,
+        gd               => gnd,
+        scout            => act_so  ,                      
+        scin             => act_si  ,                    
+        din(0)            => spare_unused(0),
+        din(1)            => spare_unused(1),
+        din(2)            => ex1_act,
+        din(3)            => ex2_act,
+        din(4)            => ex2_effsub ,
+        din(5)            => ex2_effsub_npz,
+        din(6)            => ex2_effadd_npz,
+        din(7)            => spare_unused(2),
+        din(8)            => spare_unused(3),
+        dout(0)           => spare_unused(0),
+        dout(1)           => spare_unused(1),
+        dout(2)           => ex2_act,
+        dout(3)           => ex3_act,
+        dout(4)           => ex3_effsub ,
+        dout(5)           => ex3_effsub_npz,
+        dout(6)           => ex3_effadd_npz,
+        dout(7)           => spare_unused(2) ,
+        dout(8)           => spare_unused(3) );
+
+    add_ex4_lcb : tri_lcbnd generic map (expand_type => expand_type) port map(
+        delay_lclkr =>  delay_lclkr(4) ,
+        mpw1_b      =>  mpw1_b(4)      ,
+        mpw2_b      =>  mpw2_b(0)      ,
+        forcee => forcee,
+        nclk        =>  nclk                 ,
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        act         =>  ex3_act              ,
+        sg          =>  sg_0                 ,
+        thold_b     =>  thold_0_b            ,
+        d1clk       =>  add_ex4_d1clk        ,
+        d2clk       =>  add_ex4_d2clk        ,
+        lclk        =>  add_ex4_lclk        );
+
+
+
+        ex3_s(0 to 162)  <= f_sa3_ex3_s(0  to 162); 
+        ex3_c(53 to 161) <= f_sa3_ex3_c(53 to 161);
+
+
+
+ all1: entity work.fuq_add_all1(fuq_add_all1) port map(
+         ex3_inc_byt_c_b(0 to 6)      => ex3_inc_byt_c_b(0 to 6)      ,
+         ex3_inc_byt_c_glb(1 to 6)    => ex3_inc_byt_c_glb(1 to 6)    ,
+         ex3_inc_byt_c_glb_b(1 to 6)  => ex3_inc_byt_c_glb_b(1 to 6)  ,
+         ex3_inc_all1                 => ex3_inc_all1                );
+      
+
+ inc8_6: entity work.fuq_loc8inc_lsb(fuq_loc8inc_lsb) port map(
+      co_b         => ex3_inc_byt_c_b(6)          ,
+      x            => ex3_s     ( 48 to  52)      ,
+      s0           => ex3_inc_p0( 48 to  52)      ,
+      s1           => ex3_inc_p1( 48 to  52)     );
+
+ inc8_5: entity work.fuq_loc8inc(fuq_loc8inc) port map(
+      ci           => ex3_inc_byt_c_glb(6)        ,
+      ci_b         => ex3_inc_byt_c_glb_b(6)      ,
+      co_b         => ex3_inc_byt_c_b(5)          ,
+      x            => ex3_s     ( 40 to  47)      ,
+      s0           => ex3_inc_p0( 40 to  47)      ,
+      s1           => ex3_inc_p1( 40 to  47)     );
+
+ inc8_4: entity work.fuq_loc8inc(fuq_loc8inc) port map(
+      ci           => ex3_inc_byt_c_glb(5)        ,
+      ci_b         => ex3_inc_byt_c_glb_b(5)      ,
+      co_b         => ex3_inc_byt_c_b(4)          ,
+      x            => ex3_s     ( 32 to  39)      ,
+      s0           => ex3_inc_p0( 32 to  39)      ,
+      s1           => ex3_inc_p1( 32 to  39)     );
+
+ inc8_3: entity work.fuq_loc8inc(fuq_loc8inc) port map(
+      ci           => ex3_inc_byt_c_glb(4)        ,
+      ci_b         => ex3_inc_byt_c_glb_b(4)      ,
+      co_b         => ex3_inc_byt_c_b(3)          ,
+      x            => ex3_s     ( 24 to  31)      ,
+      s0           => ex3_inc_p0( 24 to  31)      ,
+      s1           => ex3_inc_p1( 24 to  31)     );
+
+ inc8_2: entity work.fuq_loc8inc(fuq_loc8inc) port map(
+      ci           => ex3_inc_byt_c_glb(3)        ,
+      ci_b         => ex3_inc_byt_c_glb_b(3)      ,
+      co_b         => ex3_inc_byt_c_b(2)          ,
+      x            => ex3_s     ( 16 to  23)      ,
+      s0           => ex3_inc_p0( 16 to  23)      ,
+      s1           => ex3_inc_p1( 16 to  23)     );
+
+ inc8_1: entity work.fuq_loc8inc(fuq_loc8inc) port map(
+      ci           => ex3_inc_byt_c_glb(2)        ,
+      ci_b         => ex3_inc_byt_c_glb_b(2)      ,
+      co_b         => ex3_inc_byt_c_b(1)          ,
+      x            => ex3_s     (  8 to  15)      ,
+      s0           => ex3_inc_p0(  8 to  15)      ,
+      s1           => ex3_inc_p1(  8 to  15)     );
+
+ inc8_0: entity work.fuq_loc8inc(fuq_loc8inc) port map(
+      ci           => ex3_inc_byt_c_glb(1)        ,
+      ci_b         => ex3_inc_byt_c_glb_b(1)      ,
+      co_b         => ex3_inc_byt_c_b(0)          ,
+      x            => ex3_s     (  0 to   7)      ,
+      s0           => ex3_inc_p0(  0 to   7)      ,
+      s1           => ex3_inc_p1(  0 to   7)     );
+
+
+
+
+
+
+
+ hc16_0: entity work.fuq_hc16pp_msb(fuq_hc16pp_msb) port map(
+      x            => ex3_s( 53 to  68)         ,
+      y            => ex3_c( 53 to  68)         ,
+      ci0          => ex3_g128(1)               ,
+      ci0_b        => ex3_g128_b(1)             ,
+      ci1          => ex3_t128(1)               ,
+      ci1_b        => ex3_t128_b(1)             ,
+      s0           => ex3_s_p0( 53 to  68)      ,
+      s1           => ex3_s_p1( 53 to  68)      ,
+      g16          => ex3_g16(0)                ,
+      t16          => ex3_t16(0)               );
+
+ hc16_1: entity work.fuq_hc16pp(fuq_hc16pp) port map(
+      x            => ex3_s( 69 to  84)         ,
+      y            => ex3_c( 69 to  84)         ,
+      ci0          => ex3_g128(2)               ,
+      ci0_b        => ex3_g128_b(2)             ,
+      ci1          => ex3_t128(2)               ,
+      ci1_b        => ex3_t128_b(2)             ,
+      s0           => ex3_s_p0( 69 to  84)      ,
+      s1           => ex3_s_p1( 69 to  84)      ,
+      g16          => ex3_g16(1)                ,
+      t16          => ex3_t16(1)               );
+
+ hc16_2: entity work.fuq_hc16pp(fuq_hc16pp) port map(
+      x            => ex3_s( 85 to 100)         ,
+      y            => ex3_c( 85 to 100)         ,
+      ci0          => ex3_g128(3)               ,
+      ci0_b        => ex3_g128_b(3)             ,
+      ci1          => ex3_t128(3)               ,
+      ci1_b        => ex3_t128_b(3)             ,
+      s0           => ex3_s_p0( 85 to 100)      ,
+      s1           => ex3_s_p1( 85 to 100)      ,
+      g16          => ex3_g16(2)                ,
+      t16          => ex3_t16(2)               );
+
+ hc16_3: entity work.fuq_hc16pp(fuq_hc16pp) port map(
+      x            => ex3_s(101 to 116)         ,
+      y            => ex3_c(101 to 116)         ,
+      ci0          => ex3_g128(4)               ,
+      ci0_b        => ex3_g128_b(4)             ,
+      ci1          => ex3_t128(4)               ,
+      ci1_b        => ex3_t128_b(4)             ,
+      s0           => ex3_s_p0(101 to 116)      ,
+      s1           => ex3_s_p1(101 to 116)      ,
+      g16          => ex3_g16(3)                ,
+      t16          => ex3_t16(3)               );
+
+ hc16_4: entity work.fuq_hc16pp(fuq_hc16pp) port map(
+      x            => ex3_s(117 to 132)         ,
+      y            => ex3_c(117 to 132)         ,
+      ci0          => ex3_g128(5)               ,
+      ci0_b        => ex3_g128_b(5)             ,
+      ci1          => ex3_t128(5)               ,
+      ci1_b        => ex3_t128_b(5)             ,
+      s0           => ex3_s_p0(117 to 132)      ,
+      s1           => ex3_s_p1(117 to 132)      ,
+      g16          => ex3_g16(4)                ,
+      t16          => ex3_t16(4)               );
+
+ hc16_5: entity work.fuq_hc16pp(fuq_hc16pp) port map(
+      x            => ex3_s(133 to 148)         ,
+      y            => ex3_c(133 to 148)         ,
+      ci0          => ex3_g128(6)               ,
+      ci0_b        => ex3_g128_b(6)             ,
+      ci1          => ex3_t128(6)               ,
+      ci1_b        => ex3_t128_b(6)             ,
+      s0           => ex3_s_p0(133 to 148)      ,
+      s1           => ex3_s_p1(133 to 148)      ,
+      g16          => ex3_g16(5)                ,
+      t16          => ex3_t16(5)               );
+
+ hc16_6: entity work.fuq_hc16pp_lsb(fuq_hc16pp_lsb) port map(
+      x(0 to 13)   => ex3_s(149 to 162)         ,
+      y(0 to 12)   => ex3_c(149 to 161)         ,
+      s0           => ex3_s_p0(149 to 162)      ,
+      s1           => ex3_s_p1(149 to 162)      ,
+      g16          => ex3_g16(6)                ,
+      t16          => ex3_t16(6)               );
+
+
+
+
+
+  u_incmx_p0x: ex3_inc_p0_x(0 to 52) <= ex3_inc_p0(0 to 52) xor (0 to 52=> ex3_flip_inc_p0);
+  u_incmx_p1x: ex3_inc_p1_x(0 to 52) <= ex3_inc_p1(0 to 52) xor (0 to 52=> ex3_flip_inc_p1);
+  
+  u_incmx_p0:  ex3_incx_p0_b(0 to 52) <= not( (0 to 52=> ex3_inc_sel_p0) and ex3_inc_p0_x(0 to 52)  );
+  u_incmx_p1:  ex3_incx_p1_b(0 to 52) <= not( (0 to 52=> ex3_inc_sel_p1) and ex3_inc_p1_x(0 to 52)  );
+  u_incmx:     ex3_res      (0 to 52) <= not( ex3_incx_p0_b(0 to 52) and ex3_incx_p1_b(0 to 52) );
+
+ 
+  ex3_sel_a1(53 to 68)   <= (53 to 68   => ex3_eac_sel_p0n(0) ); 
+  ex3_sel_a1(69 to 84)   <= (69 to 84   => ex3_eac_sel_p0n(1) ); 
+  ex3_sel_a1(85 to 100)  <= (85 to 100  => ex3_eac_sel_p0n(2) ); 
+  ex3_sel_a1(101 to 116) <= (101 to 116 => ex3_eac_sel_p0n(3) ); 
+  ex3_sel_a1(117 to 132) <= (117 to 132 => ex3_eac_sel_p0n(4) ); 
+  ex3_sel_a1(133 to 148) <= (133 to 148 => ex3_eac_sel_p0n(5) ); 
+  ex3_sel_a1(149 to 162) <= (149 to 162 => ex3_eac_sel_p0n(6) ); 
+
+  ex3_sel_a2(53 to 68)   <= (53 to 68   => ex3_eac_sel_p0(0) ); 
+  ex3_sel_a2(69 to 84)   <= (69 to 84   => ex3_eac_sel_p0(1) ); 
+  ex3_sel_a2(85 to 100)  <= (85 to 100  => ex3_eac_sel_p0(2) ); 
+  ex3_sel_a2(101 to 116) <= (101 to 116 => ex3_eac_sel_p0(3) ); 
+  ex3_sel_a2(117 to 132) <= (117 to 132 => ex3_eac_sel_p0(4) ); 
+  ex3_sel_a2(133 to 148) <= (133 to 148 => ex3_eac_sel_p0(5) ); 
+  ex3_sel_a2(149 to 162) <= (149 to 162 => ex3_eac_sel_p0(6) ); 
+
+  ex3_sel_a3(53 to 68)   <= (53 to 68   => ex3_eac_sel_p1(0) ); 
+  ex3_sel_a3(69 to 84)   <= (69 to 84   => ex3_eac_sel_p1(1) ); 
+  ex3_sel_a3(85 to 100)  <= (85 to 100  => ex3_eac_sel_p1(2) ); 
+  ex3_sel_a3(101 to 116) <= (101 to 116 => ex3_eac_sel_p1(3) ); 
+  ex3_sel_a3(117 to 132) <= (117 to 132 => ex3_eac_sel_p1(4) ); 
+  ex3_sel_a3(133 to 148) <= (133 to 148 => ex3_eac_sel_p1(5) ); 
+  ex3_sel_a3(149 to 162) <= (149 to 162 => ex3_eac_sel_p1(6) ); 
+
+  u_eacmx_i:  ex3_s_p0n    (53 to 162) <= not( ex3_s_p0(53 to 162) );
+  u_eacmx_a1: ex3_res_p0n_b(53 to 162) <= not( ex3_sel_a1(53 to 162) and ex3_s_p0n(53 to 162) );
+  u_eacmx_a2: ex3_res_p0_b (53 to 162) <= not( ex3_sel_a2(53 to 162) and ex3_s_p0(53 to 162)  );
+  u_eacmx_a3: ex3_res_p1_b (53 to 162) <= not( ex3_sel_a3(53 to 162) and ex3_s_p1(53 to 162)  );
+  u_eacmx:    ex3_res      (53 to 162) <= not( ex3_res_p0n_b(53 to 162) and ex3_res_p0_b(53 to 162) and ex3_res_p1_b(53 to 162) );
+ 
+
+
+ glbc: entity work.fuq_add_glbc(fuq_add_glbc) port map(
+         ex3_g16(0 to 6)         => ex3_g16(0 to 6)       ,
+         ex3_t16(0 to 6)         => ex3_t16(0 to 6)       ,
+         ex3_inc_all1            => ex3_inc_all1          ,
+         ex3_effsub              => ex3_effsub            ,
+         ex3_effsub_npz          => ex3_effsub_npz        ,
+         ex3_effadd_npz          => ex3_effadd_npz        ,
+         f_alg_ex3_frc_sel_p1    => f_alg_ex3_frc_sel_p1  ,
+         f_alg_ex3_sticky        => f_alg_ex3_sticky      ,
+         f_pic_ex3_is_nan        => f_pic_ex3_is_nan      ,
+         f_pic_ex3_is_gt         => f_pic_ex3_is_gt       ,
+         f_pic_ex3_is_lt         => f_pic_ex3_is_lt       ,
+         f_pic_ex3_is_eq         => f_pic_ex3_is_eq       ,
+         f_pic_ex3_cmp_sgnpos    => f_pic_ex3_cmp_sgnpos  ,
+         f_pic_ex3_cmp_sgnneg    => f_pic_ex3_cmp_sgnneg  ,
+         ex3_g128(1 to 6)        => ex3_g128(1 to 6)      ,
+         ex3_g128_b(1 to 6)      => ex3_g128_b(1 to 6)    ,
+         ex3_t128(1 to 6)        => ex3_t128(1 to 6)      ,
+         ex3_t128_b(1 to 6)      => ex3_t128_b(1 to 6)    ,
+         ex3_flip_inc_p0         => ex3_flip_inc_p0       ,
+         ex3_flip_inc_p1         => ex3_flip_inc_p1       ,
+         ex3_inc_sel_p0          => ex3_inc_sel_p0        ,
+         ex3_inc_sel_p1          => ex3_inc_sel_p1        ,
+         ex3_eac_sel_p0n(0 to 6) => ex3_eac_sel_p0n       ,
+         ex3_eac_sel_p0 (0 to 6) => ex3_eac_sel_p0        ,
+         ex3_eac_sel_p1 (0 to 6) => ex3_eac_sel_p1        ,
+         ex3_sign_carry          => ex3_sign_carry        ,
+         ex3_flag_nan_cp1        => ex3_flag_nan_cp1      ,
+         ex3_flag_gt_cp1         => ex3_flag_gt_cp1       ,
+         ex3_flag_lt_cp1         => ex3_flag_lt_cp1       ,
+         ex3_flag_eq_cp1         => ex3_flag_eq_cp1       ,
+         ex3_flag_nan            => ex3_flag_nan          ,
+         ex3_flag_gt             => ex3_flag_gt           ,
+         ex3_flag_lt             => ex3_flag_lt           ,
+         ex3_flag_eq             => ex3_flag_eq          );
+
+
+
+
+   ex4_res_hi_lat:  entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 53, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0   ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK           => add_ex4_lclk               ,
+        D1CLK          => add_ex4_d1clk              ,
+        D2CLK          => add_ex4_d2clk              ,
+        SCANIN         => ex4_res_si(0 to 52)        ,                    
+        SCANOUT        => ex4_res_so(0 to 52)        ,
+        D              => ex3_res(0 to 52)           , 
+        QB             => ex4_res_l2_b(0 to 52)     ); 
+
+
+   ex4_res_lo_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 110, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0   ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK           => add_ex4_lclk               ,
+        D1CLK          => add_ex4_d1clk              ,
+        D2CLK          => add_ex4_d2clk              ,
+        SCANIN         => ex4_res_si(53 to 162)      ,                    
+        SCANOUT        => ex4_res_so(53 to 162)      ,
+        D               => ex3_res(53 to 162)        ,
+        QB              => ex4_res_l2_b(53 to 162)  ); 
+
+              ex4_res  (0 to 162) <= not ex4_res_l2_b(0 to 162) ;    
+a_oinv:       ex4_res_b(0 to 162) <= not ex4_res  (0 to 162);
+a_obuf: f_add_ex4_res  (0 to 162) <= not ex4_res_b(0 to 162) ; 
+
+   ex4_cmp_lat: entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 10, btr => "NLI0001_X2_A12TH", expand_type => expand_type, needs_sreset => 0   ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK           => add_ex4_lclk               ,
+        D1CLK          => add_ex4_d1clk              ,
+        D2CLK          => add_ex4_d2clk              ,
+        SCANIN         => ex4_cmp_si                 ,                    
+        SCANOUT        => ex4_cmp_so                 ,
+        D( 0)   => ex3_flag_lt        ,     
+        D( 1)   => ex3_flag_lt_cp1    ,     
+        D( 2)   => ex3_flag_gt        ,     
+        D( 3)   => ex3_flag_gt_cp1    ,     
+        D( 4)   => ex3_flag_eq        ,     
+        D( 5)   => ex3_flag_eq_cp1    ,     
+        D( 6)   => ex3_flag_nan       ,     
+        D( 7)   => ex3_flag_nan_cp1   ,     
+        D( 8)   => ex3_sign_carry     , 
+        D( 9)   => f_alg_ex3_sticky   , 
+        QB( 0)   => ex4_flag_lt_b        ,  
+        QB( 1)   => ex4_fpcc_iu_b(0)     ,  
+        QB( 2)   => ex4_flag_gt_b        ,  
+        QB( 3)   => ex4_fpcc_iu_b(1)     ,  
+        QB( 4)   => ex4_flag_eq_b        ,  
+        QB( 5)   => ex4_fpcc_iu_b(2)     ,  
+        QB( 6)   => ex4_flag_nan_b       ,  
+        QB( 7)   => ex4_fpcc_iu_b(3)     ,  
+        QB( 8)   => ex4_sign_carry_b     ,  
+        QB( 9)   => ex4_sticky_b         ); 
+
+
+       f_add_ex4_flag_nan         <= not ex4_flag_nan_b        ;
+       f_add_ex4_flag_gt          <= not ex4_flag_gt_b         ;
+       f_add_ex4_flag_lt          <= not ex4_flag_lt_b         ;
+       f_add_ex4_flag_eq          <= not ex4_flag_eq_b         ;
+       f_add_ex4_fpcc_iu(0 to 3)  <= not ex4_fpcc_iu_b(0 to 3) ;
+       f_add_ex4_sign_carry       <= not ex4_sign_carry_b      ;
+       f_add_ex4_sticky           <= not ex4_sticky_b          ;
+
+
+       f_add_ex4_to_int_ovf_wd(0) <= ex4_res(130)   ;
+       f_add_ex4_to_int_ovf_wd(1) <= ex4_res(131)   ;
+       f_add_ex4_to_int_ovf_dw(0) <= ex4_res(98)    ;
+       f_add_ex4_to_int_ovf_dw(1) <= ex4_res(99)    ;
+
+
+
+
+
+  act_si  (0 to 8)       <= act_so  (1 to 8)       & f_add_si ;
+  ex4_res_si  (0 to 162) <= ex4_res_so  (1 to 162) & act_so(0);
+  ex4_cmp_si  (0 to 9)   <= ex4_cmp_so  (1 to 9)  & ex4_res_so(0);
+  f_add_so               <= ex4_cmp_so  (0) ;
+
+end; 

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_all1.vhdl

@@ -0,0 +1,124 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm; 
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+
+
+entity fuq_add_all1 is port(
+     ex3_inc_byt_c_b       :in  std_ulogic_vector(0 to 6); 
+     ex3_inc_byt_c_glb     :out std_ulogic_vector(1 to 6);
+     ex3_inc_byt_c_glb_b   :out std_ulogic_vector(1 to 6);
+     ex3_inc_all1          :out std_ulogic
+ );
+
+
+
+END                                 fuq_add_all1;
+
+
+ARCHITECTURE fuq_add_all1  OF fuq_add_all1  IS
+
+ constant tiup : std_ulogic := '1';
+ constant tidn : std_ulogic := '0';
+
+ signal ex3_inc_byt_g1 :std_ulogic_vector(0 to 6);
+ signal ex3_inc_byt_g2_b :std_ulogic_vector(0 to 6);
+ signal ex3_inc_byt_g4   :std_ulogic_vector(0 to 6);
+ signal ex3_inc_byt_g8_b :std_ulogic_vector(0 to 6);
+ signal ex3_inc_byt_g_glb_int  :std_ulogic_vector(1 to 6);
+  
+
+
+
+
+
+
+
+
+BEGIN
+
+ ii:    ex3_inc_byt_g1(0 to 6)  <= not ex3_inc_byt_c_b(0 to 6);
+
+ g26:   ex3_inc_byt_g2_b(6) <= not( ex3_inc_byt_g1(6) );
+ g25:   ex3_inc_byt_g2_b(5) <= not( ex3_inc_byt_g1(5) and ex3_inc_byt_g1(6) );
+ g24:   ex3_inc_byt_g2_b(4) <= not( ex3_inc_byt_g1(4) and ex3_inc_byt_g1(5) );
+ g23:   ex3_inc_byt_g2_b(3) <= not( ex3_inc_byt_g1(3) and ex3_inc_byt_g1(4) );
+ g22:   ex3_inc_byt_g2_b(2) <= not( ex3_inc_byt_g1(2) and ex3_inc_byt_g1(3) );
+ g21:   ex3_inc_byt_g2_b(1) <= not( ex3_inc_byt_g1(1) and ex3_inc_byt_g1(2) );
+ g20:   ex3_inc_byt_g2_b(0) <= not( ex3_inc_byt_g1(0) and ex3_inc_byt_g1(1) );
+
+ g46:   ex3_inc_byt_g4(6) <= not( ex3_inc_byt_g2_b(6) ); 
+ g45:   ex3_inc_byt_g4(5) <= not( ex3_inc_byt_g2_b(5) ); 
+ g44:   ex3_inc_byt_g4(4) <= not( ex3_inc_byt_g2_b(4) or   ex3_inc_byt_g2_b(6) ); 
+ g43:   ex3_inc_byt_g4(3) <= not( ex3_inc_byt_g2_b(3) or   ex3_inc_byt_g2_b(5) ); 
+ g42:   ex3_inc_byt_g4(2) <= not( ex3_inc_byt_g2_b(2) or   ex3_inc_byt_g2_b(4) ); 
+ g41:   ex3_inc_byt_g4(1) <= not( ex3_inc_byt_g2_b(1) or   ex3_inc_byt_g2_b(3) ); 
+ g40:   ex3_inc_byt_g4(0) <= not( ex3_inc_byt_g2_b(0) or   ex3_inc_byt_g2_b(2) ); 
+
+ g86:   ex3_inc_byt_g8_b(6) <= not( ex3_inc_byt_g4(6) );
+ g85:   ex3_inc_byt_g8_b(5) <= not( ex3_inc_byt_g4(5) );
+ g84:   ex3_inc_byt_g8_b(4) <= not( ex3_inc_byt_g4(4) );
+ g83:   ex3_inc_byt_g8_b(3) <= not( ex3_inc_byt_g4(3) );
+ g82:   ex3_inc_byt_g8_b(2) <= not( ex3_inc_byt_g4(2) and  ex3_inc_byt_g4(6) );
+ g81:   ex3_inc_byt_g8_b(1) <= not( ex3_inc_byt_g4(1) and  ex3_inc_byt_g4(5) );
+ g80:   ex3_inc_byt_g8_b(0) <= not( ex3_inc_byt_g4(0) and  ex3_inc_byt_g4(4) );
+
+ all1:   ex3_inc_all1           <= not ex3_inc_byt_g8_b(0);
+ iop1:   ex3_inc_byt_c_glb(1)   <= not ex3_inc_byt_g8_b(1); 
+ iop2:   ex3_inc_byt_c_glb(2)   <= not ex3_inc_byt_g8_b(2); 
+ iop3:   ex3_inc_byt_c_glb(3)   <= not ex3_inc_byt_g8_b(3); 
+ iop4:   ex3_inc_byt_c_glb(4)   <= not ex3_inc_byt_g8_b(4); 
+ iop5:   ex3_inc_byt_c_glb(5)   <= not ex3_inc_byt_g8_b(5); 
+ iop6:   ex3_inc_byt_c_glb(6)   <= not ex3_inc_byt_g8_b(6); 
+
+ ionn1:  ex3_inc_byt_g_glb_int(1) <= not ex3_inc_byt_g8_b(1); 
+ ionn2:  ex3_inc_byt_g_glb_int(2) <= not ex3_inc_byt_g8_b(2); 
+ ionn3:  ex3_inc_byt_g_glb_int(3) <= not ex3_inc_byt_g8_b(3); 
+ ionn4:  ex3_inc_byt_g_glb_int(4) <= not ex3_inc_byt_g8_b(4); 
+ ionn5:  ex3_inc_byt_g_glb_int(5) <= not ex3_inc_byt_g8_b(5); 
+ ionn6:  ex3_inc_byt_g_glb_int(6) <= not ex3_inc_byt_g8_b(6); 
+
+ ion1:  ex3_inc_byt_c_glb_b(1) <= not ex3_inc_byt_g_glb_int(1) ; 
+ ion2:  ex3_inc_byt_c_glb_b(2) <= not ex3_inc_byt_g_glb_int(2) ; 
+ ion3:  ex3_inc_byt_c_glb_b(3) <= not ex3_inc_byt_g_glb_int(3) ; 
+ ion4:  ex3_inc_byt_c_glb_b(4) <= not ex3_inc_byt_g_glb_int(4) ; 
+ ion5:  ex3_inc_byt_c_glb_b(5) <= not ex3_inc_byt_g_glb_int(5) ; 
+ ion6:  ex3_inc_byt_c_glb_b(6) <= not ex3_inc_byt_g_glb_int(6) ; 
+
+      
+
+END; 
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_add_glbc.vhdl

@@ -0,0 +1,605 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm; 
+
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+
+
+entity fuq_add_glbc is port(
+     ex3_g16               :in  std_ulogic_vector(0 to 6); 
+     ex3_t16               :in  std_ulogic_vector(0 to 6); 
+
+     ex3_inc_all1          :in  std_ulogic;
+     ex3_effsub            :in  std_ulogic; 
+     ex3_effsub_npz        :in  std_ulogic; 
+     ex3_effadd_npz        :in  std_ulogic; 
+     f_alg_ex3_frc_sel_p1  :in  std_ulogic;
+     f_alg_ex3_sticky      :in  std_ulogic;
+     f_pic_ex3_is_nan      :in  std_ulogic;
+     f_pic_ex3_is_gt       :in  std_ulogic;
+     f_pic_ex3_is_lt       :in  std_ulogic;
+     f_pic_ex3_is_eq       :in  std_ulogic;
+     f_pic_ex3_cmp_sgnpos  :in  std_ulogic;
+     f_pic_ex3_cmp_sgnneg  :in  std_ulogic;
+     ex3_g128              :out std_ulogic_vector(1 to 6); 
+     ex3_g128_b            :out std_ulogic_vector(1 to 6); 
+     ex3_t128              :out std_ulogic_vector(1 to 6); 
+     ex3_t128_b            :out std_ulogic_vector(1 to 6); 
+     ex3_flip_inc_p0       :out std_ulogic;
+     ex3_flip_inc_p1       :out std_ulogic;
+     ex3_inc_sel_p0        :out std_ulogic;
+     ex3_inc_sel_p1        :out std_ulogic;
+     ex3_eac_sel_p0n       :out std_ulogic_vector(0 to 6);
+     ex3_eac_sel_p0        :out std_ulogic_vector(0 to 6);
+     ex3_eac_sel_p1        :out std_ulogic_vector(0 to 6);
+
+     ex3_sign_carry        :out std_ulogic;
+     ex3_flag_nan_cp1      :out std_ulogic;
+     ex3_flag_gt_cp1       :out std_ulogic;
+     ex3_flag_lt_cp1       :out std_ulogic;
+     ex3_flag_eq_cp1       :out std_ulogic;
+     ex3_flag_nan          :out std_ulogic;
+     ex3_flag_gt           :out std_ulogic;
+     ex3_flag_lt           :out std_ulogic;
+     ex3_flag_eq           :out std_ulogic
+ );
+
+
+
+END                                 fuq_add_glbc;
+
+
+ARCHITECTURE fuq_add_glbc  OF fuq_add_glbc  IS
+
+ constant tiup : std_ulogic := '1';
+ constant tidn : std_ulogic := '0';
+
+
+ signal cp0_g32_01_b,  cp0_g32_23_b,  cp0_g32_45_b, cp0_g32_66_b :std_ulogic;
+ signal cp0_t32_01_b , cp0_t32_23_b,  cp0_t32_45_b, cp0_t32_66_b :std_ulogic;
+ signal cp0_g64_03,    cp0_g64_46,    cp0_t64_03,   cp0_t64_46   :std_ulogic;
+ signal cp0_g128_06_b, cp0_t128_06_b :std_ulogic;
+ signal cp0_all1_b, cp0_all1_p,  cp0_co_p0, cp0_co_p1 :std_ulogic;
+ signal cp0_flip_inc_p1_b, ex3_inc_sel_p0_b, ex3_sign_carry_b  :std_ulogic;
+ signal ex3_my_gt_b,   ex3_my_lt , ex3_my_eq_b   :std_ulogic;
+ signal ex3_my_gt ,    ex3_my_eq      :std_ulogic;
+ signal ex3_gt_pos_b , ex3_gt_neg_b , ex3_lt_pos_b , ex3_lt_neg_b , ex3_eq_eq_b    :std_ulogic;
+ signal ex3_is_gt_b,   ex3_is_lt_b,   ex3_is_eq_b,  ex3_sgn_eq :std_ulogic;
+
+ signal  cp7_g32_00_b    ,  cp7_g32_12_b    ,  cp7_g32_34_b    ,  cp7_g32_56_b    :std_ulogic;
+ signal  cp7_t32_00_b    ,  cp7_t32_12_b    ,  cp7_t32_34_b      :std_ulogic;
+ signal  cp7_g64_02      ,  cp7_g64_36      ,  cp7_t64_02         :std_ulogic;
+ signal  cp7_g128_06_b   :std_ulogic;
+ signal  cp7_all1_b      ,  cp7_all1_p      ,  cp7_co_p0       :std_ulogic;
+ signal  cp7_sel_p0n_x_b ,  cp7_sel_p0n_y_b :std_ulogic;
+ signal  cp7_sel_p0_b    ,  cp7_sel_p1_b    :std_ulogic;
+ signal  cp7_sub_sticky  ,  cp7_sub_stickyn :std_ulogic;
+ signal  cp7_add_frcp1_b ,  cp7_add_frcp0_b :std_ulogic;
+
+ signal  cp6_g32_00_b    ,  cp6_g32_12_b    ,  cp6_g32_34_b    ,  cp6_g32_56_b    :std_ulogic;
+ signal  cp6_t32_00_b    ,  cp6_t32_12_b    ,  cp6_t32_34_b       :std_ulogic;
+ signal  cp6_g64_02      ,  cp6_g64_36      ,  cp6_t64_02          :std_ulogic;
+ signal  cp6_g128_06_b   :std_ulogic;
+ signal  cp6_all1_b      ,  cp6_all1_p      ,  cp6_co_p0       :std_ulogic;
+ signal  cp6_sel_p0n_x_b ,  cp6_sel_p0n_y_b :std_ulogic;
+ signal  cp6_sel_p0_b    ,  cp6_sel_p1_b    :std_ulogic;
+ signal  cp6_sub_sticky  ,  cp6_sub_stickyn :std_ulogic;
+ signal  cp6_add_frcp1_b ,  cp6_add_frcp0_b :std_ulogic;
+
+ signal  cp5_g32_00_b    ,  cp5_g32_12_b    ,  cp5_g32_34_b    ,  cp5_g32_56_b    :std_ulogic;
+ signal  cp5_t32_00_b    ,  cp5_t32_12_b    ,  cp5_t32_34_b    ,  cp5_t32_56_b    :std_ulogic;
+ signal  cp5_g64_02      ,  cp5_g64_36      ,  cp5_t64_02        :std_ulogic;
+ signal  cp5_g128_06_b   :std_ulogic;
+ signal  cp5_all1_b      ,  cp5_all1_p      ,  cp5_co_p0       :std_ulogic;
+ signal  cp5_sel_p0n_x_b ,  cp5_sel_p0n_y_b :std_ulogic;
+ signal  cp5_sel_p0_b    ,  cp5_sel_p1_b    :std_ulogic;
+ signal  cp5_sub_sticky  ,  cp5_sub_stickyn :std_ulogic;
+ signal  cp5_add_frcp1_b ,  cp5_add_frcp0_b :std_ulogic;
+
+
+
+ signal  cp4_g32_01_b,  cp4_g32_23_b,  cp4_g32_45_b, cp4_g32_66_b :std_ulogic;
+ signal  cp4_t32_01_b , cp4_t32_23_b,  cp4_t32_45_b, cp4_t32_66_b :std_ulogic;
+ signal  cp4_g64_03,    cp4_g64_46,    cp4_t64_03,   cp4_t64_46   :std_ulogic;
+ signal  cp4_g128_06_b :std_ulogic;
+ signal  cp4_all1_b      ,  cp4_all1_p      ,  cp4_co_p0       :std_ulogic;
+ signal  cp4_sel_p0n_x_b ,  cp4_sel_p0n_y_b :std_ulogic;
+ signal  cp4_sel_p0_b    ,  cp4_sel_p1_b    :std_ulogic;
+ signal  cp4_sub_sticky  ,  cp4_sub_stickyn :std_ulogic;
+ signal  cp4_add_frcp1_b ,  cp4_add_frcp0_b :std_ulogic;
+
+
+ signal  cp3_g32_00_b    ,  cp3_g32_12_b    ,  cp3_g32_34_b    ,  cp3_g32_56_b    :std_ulogic;
+ signal  cp3_t32_00_b    ,  cp3_t32_12_b    ,  cp3_t32_34_b    ,  cp3_t32_56_b    :std_ulogic;
+ signal  cp3_g64_02      ,  cp3_g64_36      ,  cp3_t64_02      ,  cp3_t64_36      :std_ulogic;
+ signal  cp3_g128_06_b     :std_ulogic;
+ signal  cp3_all1_b      ,  cp3_all1_p      ,  cp3_co_p0        :std_ulogic;
+ signal  cp3_sel_p0n_x_b ,  cp3_sel_p0n_y_b :std_ulogic;
+ signal  cp3_sel_p0_b    ,  cp3_sel_p1_b    :std_ulogic;
+ signal  cp3_sub_sticky  ,  cp3_sub_stickyn :std_ulogic;
+ signal  cp3_add_frcp1_b ,  cp3_add_frcp0_b :std_ulogic;
+
+ signal  cp2_g32_01_b,  cp2_g32_23_b,  cp2_g32_45_b, cp2_g32_66_b :std_ulogic;
+ signal  cp2_t32_01_b , cp2_t32_23_b,  cp2_t32_45_b, cp2_t32_66_b :std_ulogic;
+ signal  cp2_g64_03,    cp2_g64_46,    cp2_t64_03,   cp2_t64_46   :std_ulogic;
+ signal  cp2_g128_06_b :std_ulogic;
+ signal  cp2_all1_b      ,  cp2_all1_p      ,  cp2_co_p0        :std_ulogic;
+ signal  cp2_sel_p0n_x_b ,  cp2_sel_p0n_y_b :std_ulogic;
+ signal  cp2_sel_p0_b    ,  cp2_sel_p1_b    :std_ulogic;
+ signal  cp2_sub_sticky  ,  cp2_sub_stickyn :std_ulogic;
+ signal  cp2_add_frcp1_b ,  cp2_add_frcp0_b :std_ulogic;
+
+ signal  cp1_g32_01_b,  cp1_g32_23_b,  cp1_g32_45_b, cp1_g32_66_b :std_ulogic;
+ signal  cp1_t32_01_b , cp1_t32_23_b,  cp1_t32_45_b, cp1_t32_66_b :std_ulogic;
+ signal  cp1_g64_03,    cp1_g64_46,    cp1_t64_03,   cp1_t64_46   :std_ulogic;
+ signal  cp1_g128_06_b :std_ulogic;
+ signal  cp1_all1_b      ,  cp1_all1_p      ,  cp1_co_p0        :std_ulogic;
+ signal  cp1_sel_p0n_x_b ,  cp1_sel_p0n_y_b :std_ulogic;
+ signal  cp1_sel_p0_b    ,  cp1_sel_p1_b    :std_ulogic;
+ signal  cp1_sub_sticky  ,  cp1_sub_stickyn :std_ulogic;
+ signal  cp1_add_frcp1_b ,  cp1_add_frcp0_b :std_ulogic;
+
+signal cp1_g32_11_b, cp1_t32_11_b, cp1_g64_13, cp1_t64_13, cp1_g128_16_b, cp1_t128_16_b :std_ulogic; 
+signal cp2_g64_23, cp2_t64_23, cp2_g128_26_b, cp2_t128_26_b :std_ulogic;
+signal cp3_g128_36_b, cp3_t128_36_b :std_ulogic;
+signal cp4_g128_46_b, cp4_t128_46_b :std_ulogic;
+signal cp5_g64_56,    cp5_t64_56, cp5_g128_56_b, cp5_t128_56_b :std_ulogic;
+signal cp6_g32_66_b,  cp6_t32_66_b :std_ulogic;
+
+signal cp1_g128_16,  cp1_t128_16  :std_ulogic; 
+signal cp2_g128_26,  cp2_t128_26  :std_ulogic;
+signal cp3_g128_36,  cp3_t128_36  :std_ulogic;
+signal cp4_g128_46,  cp4_t128_46  :std_ulogic;
+signal cp5_g128_56,  cp5_t128_56  :std_ulogic;
+signal cp6_g128_66,  cp6_t128_66  :std_ulogic;
+
+ 
+
+
+
+
+
+   
+
+
+
+BEGIN
+
+
+
+
+ucp0_g32_01:   cp0_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); 
+ucp0_g32_23:   cp0_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); 
+ucp0_g32_45:   cp0_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); 
+ucp0_g32_66:   cp0_g32_66_b <= not( ex3_g16(6)                                  ); 
+
+ucp0_t32_01:   cp0_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); 
+ucp0_t32_23:   cp0_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); 
+ucp0_t32_45:   cp0_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); 
+ucp0_t32_66:   cp0_t32_66_b <= not( ex3_t16(6)                ); 
+
+ucp0_g64_03:   cp0_g64_03   <= not( cp0_g32_01_b and (cp0_t32_01_b or  cp0_g32_23_b) ); 
+ucp0_g64_46:   cp0_g64_46   <= not( cp0_g32_45_b and (cp0_t32_45_b or  cp0_g32_66_b) ); 
+
+ucp0_t64_03:   cp0_t64_03   <= not(                   cp0_t32_01_b or  cp0_t32_23_b  ); 
+ucp0_t64_46:   cp0_t64_46   <= not( cp0_g32_45_b and (cp0_t32_45_b or  cp0_t32_66_b) ); 
+
+ucp0_g128_06:  cp0_g128_06_b <= not( cp0_g64_03 or ( cp0_t64_03 and cp0_g64_46 ) ); 
+ucp0_t128_06:  cp0_t128_06_b <= not( cp0_g64_03 or ( cp0_t64_03 and cp0_t64_46 ) ); 
+
+ucp0_all1n:    cp0_all1_b     <= not ex3_inc_all1     ;
+ucp0_all1p:    cp0_all1_p     <= not  cp0_all1_b      ;
+ucp0_co_p0:    cp0_co_p0      <= not( cp0_g128_06_b ) ;
+ucp0_co_p1:    cp0_co_p1      <= not( cp0_t128_06_b ) ;
+
+
+
+               ex3_flip_inc_p0   <= ex3_effsub; 
+ucp0_f1in:     cp0_flip_inc_p1_b <= not( ex3_effsub and cp0_all1_b ); 
+ucp0_f1i:      ex3_flip_inc_p1   <= not( cp0_flip_inc_p1_b ); 
+
+ucp0_s1i:      ex3_inc_sel_p1    <= not cp0_g128_06_b   ; 
+ucp0_s0in:     ex3_inc_sel_p0_b  <= not cp0_g128_06_b   ; 
+ucp0_s0i:      ex3_inc_sel_p0    <= not ex3_inc_sel_p0_b; 
+
+
+ucp0_sgn0:     ex3_sign_carry_b <= not( ex3_effsub and cp0_all1_p and cp0_co_p0 );
+ucp0_sgn1:     ex3_sign_carry   <= not( ex3_sign_carry_b ); 
+
+
+ucp0_my_gtn:  ex3_my_gt_b   <= not( cp0_co_p0 and cp0_all1_p );
+ucp0_my_lt:   ex3_my_lt     <= not( cp0_co_p1 and cp0_all1_p );
+ucp0_my_eqb:  ex3_my_eq_b   <= not( cp0_co_p1 and cp0_all1_p and cp0_g128_06_b );
+
+ucp0_my_gt:   ex3_my_gt     <= not ex3_my_gt_b ; 
+ucp0_my_eq:   ex3_my_eq     <= not ex3_my_eq_b ; 
+
+ucp0_gt_pos:  ex3_gt_pos_b  <= not( ex3_my_gt and f_pic_ex3_cmp_sgnpos);
+ucp0_gt_neg:  ex3_gt_neg_b  <= not( ex3_my_lt and f_pic_ex3_cmp_sgnneg);
+ucp0_lt_pos:  ex3_lt_pos_b  <= not( ex3_my_lt and f_pic_ex3_cmp_sgnpos);
+ucp0_lt_neg:  ex3_lt_neg_b  <= not( ex3_my_gt and f_pic_ex3_cmp_sgnneg);
+ucp0_eq_eq:   ex3_eq_eq_b   <= not( ex3_my_eq and       ex3_sgn_eq    );
+
+ucp0_flg_gt:  ex3_flag_gt       <= not( ex3_gt_pos_b and ex3_gt_neg_b and ex3_is_gt_b );
+ucp0_flg_gt1: ex3_flag_gt_cp1   <= not( ex3_gt_pos_b and ex3_gt_neg_b and ex3_is_gt_b );
+ucp0_flg_lt:  ex3_flag_lt       <= not( ex3_lt_pos_b and ex3_lt_neg_b and ex3_is_lt_b );
+ucp0_flg_lt1: ex3_flag_lt_cp1   <= not( ex3_lt_pos_b and ex3_lt_neg_b and ex3_is_lt_b );
+ucp0_flg_eq:  ex3_flag_eq       <= not( ex3_eq_eq_b                   and ex3_is_eq_b );
+ucp0_flg_eq1: ex3_flag_eq_cp1   <= not( ex3_eq_eq_b                   and ex3_is_eq_b );
+
+              ex3_flag_nan      <=  f_pic_ex3_is_nan;    
+              ex3_flag_nan_cp1  <=  f_pic_ex3_is_nan;    
+
+              ex3_is_gt_b <= not( f_pic_ex3_is_gt );
+              ex3_is_lt_b <= not( f_pic_ex3_is_lt );
+              ex3_is_eq_b <= not( f_pic_ex3_is_eq );
+              ex3_sgn_eq  <= f_pic_ex3_cmp_sgnpos or f_pic_ex3_cmp_sgnneg ; 
+
+
+
+ucp1_g32_11:   cp1_g32_11_b <= not( ex3_g16(1)                                  ); 
+ucp1_g32_01:   cp1_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); 
+ucp1_g32_23:   cp1_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); 
+ucp1_g32_45:   cp1_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); 
+ucp1_g32_66:   cp1_g32_66_b <= not( ex3_g16(6)                                  ); 
+
+ucp1_t32_11:   cp1_t32_11_b <= not(                ex3_t16(1) ); 
+ucp1_t32_01:   cp1_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); 
+ucp1_t32_23:   cp1_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); 
+ucp1_t32_45:   cp1_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); 
+ucp1_t32_66:   cp1_t32_66_b <= not( ex3_t16(6)                ); 
+
+ucp1_g64_03:   cp1_g64_03   <= not( cp1_g32_01_b and (cp1_t32_01_b or  cp1_g32_23_b) ); 
+ucp1_g64_13:   cp1_g64_13   <= not( cp1_g32_11_b and (cp1_t32_11_b or  cp1_g32_23_b) ); 
+ucp1_g64_46:   cp1_g64_46   <= not( cp1_g32_45_b and (cp1_t32_45_b or  cp1_g32_66_b) ); 
+
+ucp1_t64_03:   cp1_t64_03   <= not(                   cp1_t32_01_b or  cp1_t32_23_b  ); 
+ucp1_t64_13:   cp1_t64_13   <= not(                   cp1_t32_11_b or  cp1_t32_23_b  ); 
+ucp1_t64_46:   cp1_t64_46   <= not( cp1_g32_45_b and (cp1_t32_45_b or  cp1_t32_66_b) ); 
+
+ucp1_g128_06:  cp1_g128_06_b <= not( cp1_g64_03 or ( cp1_t64_03 and cp1_g64_46 ) ); 
+ucp1_g128_16:  cp1_g128_16_b <= not( cp1_g64_13 or ( cp1_t64_13 and cp1_g64_46 ) ); 
+ucp1_t128_16:  cp1_t128_16_b <= not( cp1_g64_13 or ( cp1_t64_13 and cp1_t64_46 ) ); 
+
+
+ucp1_cog:  ex3_g128(1)   <= not( cp1_g128_16_b);
+ucp1_cogx: cp1_g128_16   <= not( cp1_g128_16_b);
+ucp1_cogb: ex3_g128_b(1) <= not( cp1_g128_16  );
+ucp1_cot:  ex3_t128(1)   <= not( cp1_t128_16_b);
+ucp1_cotx: cp1_t128_16   <= not( cp1_t128_16_b);
+ucp1_cotb: ex3_t128_b(1) <= not( cp1_t128_16  );
+
+ucp1_all1n:    cp1_all1_b <= not ex3_inc_all1     ;
+ucp1_all1p:    cp1_all1_p <= not  cp1_all1_b      ;
+ucp1_co_p0:    cp1_co_p0  <= not( cp1_g128_06_b ) ;
+
+ucp1_espnx: cp1_sel_p0n_x_b <= not( cp1_all1_b    and ex3_effsub_npz);
+ucp1_espny: cp1_sel_p0n_y_b <= not( cp1_g128_06_b and ex3_effsub_npz);
+ucp1_selp0: cp1_sel_p0_b    <= not( cp1_co_p0     and cp1_all1_p and cp1_sub_sticky  );
+ucp1_selp1: cp1_sel_p1_b    <= not( cp1_co_p0     and cp1_all1_p and cp1_sub_stickyn );
+
+ucp1_espn:  ex3_eac_sel_p0n(0) <= not( cp1_sel_p0n_x_b and cp1_sel_p0n_y_b);
+ucp1_esp0:  ex3_eac_sel_p0(0)  <= not( cp1_sel_p0_b    and cp1_add_frcp0_b);
+ucp1_esp1:  ex3_eac_sel_p1(0)  <= not( cp1_sel_p1_b    and cp1_add_frcp1_b);
+
+    cp1_sub_sticky  <=      ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp1_sub_stickyn <=      ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp1_add_frcp1_b <= not( ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp1_add_frcp0_b <= not( ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+
+
+ucp2_g32_01:   cp2_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); 
+ucp2_g32_23:   cp2_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); 
+ucp2_g32_45:   cp2_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); 
+ucp2_g32_66:   cp2_g32_66_b <= not( ex3_g16(6)                                  ); 
+
+ucp2_t32_01:   cp2_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); 
+ucp2_t32_23:   cp2_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); 
+ucp2_t32_45:   cp2_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); 
+ucp2_t32_66:   cp2_t32_66_b <= not( ex3_t16(6)                ); 
+
+ucp2_g64_23:   cp2_g64_23   <= not(                                    cp2_g32_23_b  ); 
+ucp2_g64_03:   cp2_g64_03   <= not( cp2_g32_01_b and (cp2_t32_01_b or  cp2_g32_23_b) ); 
+ucp2_g64_46:   cp2_g64_46   <= not( cp2_g32_45_b and (cp2_t32_45_b or  cp2_g32_66_b) ); 
+
+ucp2_t64_23:   cp2_t64_23   <= not(                                    cp2_t32_23_b  ); 
+ucp2_t64_03:   cp2_t64_03   <= not(                   cp2_t32_01_b or  cp2_t32_23_b  ); 
+ucp2_t64_46:   cp2_t64_46   <= not( cp2_g32_45_b and (cp2_t32_45_b or  cp2_t32_66_b) ); 
+
+ucp2_g128_06:  cp2_g128_06_b <= not( cp2_g64_03 or ( cp2_t64_03 and cp2_g64_46 ) ); 
+ucp2_g128_26:  cp2_g128_26_b <= not( cp2_g64_23 or ( cp2_t64_23 and cp2_g64_46 ) ); 
+ucp2_t128_26:  cp2_t128_26_b <= not( cp2_g64_23 or ( cp2_t64_23 and cp2_t64_46 ) ); 
+
+
+ucp2_cog:  ex3_g128(2)   <= not( cp2_g128_26_b);
+ucp2_cogx: cp2_g128_26   <= not( cp2_g128_26_b);
+ucp2_cogb: ex3_g128_b(2) <= not( cp2_g128_26  );
+ucp2_cot:  ex3_t128(2)   <= not( cp2_t128_26_b);
+ucp2_cotx: cp2_t128_26   <= not( cp2_t128_26_b);
+ucp2_cotb: ex3_t128_b(2) <= not( cp2_t128_26  );
+
+
+ucp2_all1n:    cp2_all1_b <= not ex3_inc_all1     ;
+ucp2_all1p:    cp2_all1_p <= not  cp2_all1_b      ;
+ucp2_co_p0:    cp2_co_p0  <= not( cp2_g128_06_b ) ;
+
+ucp2_espnx: cp2_sel_p0n_x_b <= not( cp2_all1_b    and ex3_effsub_npz);
+ucp2_espny: cp2_sel_p0n_y_b <= not( cp2_g128_06_b and ex3_effsub_npz);
+ucp2_selp0: cp2_sel_p0_b    <= not( cp2_co_p0     and cp2_all1_p and cp2_sub_sticky  );
+ucp2_selp1: cp2_sel_p1_b    <= not( cp2_co_p0     and cp2_all1_p and cp2_sub_stickyn );
+
+ucp2_espn:  ex3_eac_sel_p0n(1) <= not( cp2_sel_p0n_x_b and cp2_sel_p0n_y_b);
+ucp2_esp0:  ex3_eac_sel_p0(1)  <= not( cp2_sel_p0_b    and cp2_add_frcp0_b);
+ucp2_esp1:  ex3_eac_sel_p1(1)  <= not( cp2_sel_p1_b    and cp2_add_frcp1_b);
+
+    cp2_sub_sticky  <=          ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp2_sub_stickyn <=          ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp2_add_frcp1_b <= not(     ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp2_add_frcp0_b <= not(     ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+
+
+ucp3_g32_00:   cp3_g32_00_b <= not( ex3_g16(0)                                  ) ; 
+ucp3_g32_12:   cp3_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); 
+ucp3_g32_34:   cp3_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); 
+ucp3_g32_56:   cp3_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); 
+
+ucp3_t32_00:   cp3_t32_00_b <= not( ex3_t16(0)                ); 
+ucp3_t32_12:   cp3_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); 
+ucp3_t32_34:   cp3_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); 
+ucp3_t32_56:   cp3_t32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_t16(6) ) ); 
+
+ucp3_g64_02:   cp3_g64_02   <= not( cp3_g32_00_b and (cp3_t32_00_b or  cp3_g32_12_b) ); 
+ucp3_g64_36:   cp3_g64_36   <= not( cp3_g32_34_b and (cp3_t32_34_b or  cp3_g32_56_b) ); 
+
+ucp3_t64_02:   cp3_t64_02   <= not(                   cp3_t32_00_b or  cp3_t32_12_b  ); 
+ucp3_t64_36:   cp3_t64_36   <= not( cp3_g32_34_b and (cp3_t32_34_b or  cp3_t32_56_b) ); 
+
+ucp3_g128_06:  cp3_g128_06_b <= not( cp3_g64_02 or ( cp3_t64_02 and cp3_g64_36 ) ); 
+ucp3_g128_36:  cp3_g128_36_b <= not(                                cp3_g64_36   ); 
+ucp3_t128_36:  cp3_t128_36_b <= not(                                cp3_t64_36   ); 
+
+
+ucp3_cog:  ex3_g128(3)   <= not( cp3_g128_36_b);
+ucp3_cogx: cp3_g128_36   <= not( cp3_g128_36_b);
+ucp3_cogb: ex3_g128_b(3) <= not( cp3_g128_36  );
+ucp3_cot:  ex3_t128(3)   <= not( cp3_t128_36_b);
+ucp3_cotx: cp3_t128_36   <= not( cp3_t128_36_b);
+ucp3_cotb: ex3_t128_b(3) <= not( cp3_t128_36  );
+
+
+ucp3_all1n:    cp3_all1_b <= not ex3_inc_all1     ;
+ucp3_all1p:    cp3_all1_p <= not  cp3_all1_b      ;
+ucp3_co_p0:    cp3_co_p0  <= not( cp3_g128_06_b ) ;
+
+ucp3_espnx: cp3_sel_p0n_x_b <= not( cp3_all1_b    and ex3_effsub_npz);
+ucp3_espny: cp3_sel_p0n_y_b <= not( cp3_g128_06_b and ex3_effsub_npz);
+ucp3_selp0: cp3_sel_p0_b    <= not( cp3_co_p0     and cp3_all1_p and cp3_sub_sticky  );
+ucp3_selp1: cp3_sel_p1_b    <= not( cp3_co_p0     and cp3_all1_p and cp3_sub_stickyn );
+
+ucp3_espn:  ex3_eac_sel_p0n(2) <= not( cp3_sel_p0n_x_b and cp3_sel_p0n_y_b);
+ucp3_esp0:  ex3_eac_sel_p0(2)  <= not( cp3_sel_p0_b    and cp3_add_frcp0_b);
+ucp3_esp1:  ex3_eac_sel_p1(2)  <= not( cp3_sel_p1_b    and cp3_add_frcp1_b);
+
+    cp3_sub_sticky  <=          ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp3_sub_stickyn <=          ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp3_add_frcp1_b <= not(     ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp3_add_frcp0_b <= not(     ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+
+
+
+ucp4_g32_01:   cp4_g32_01_b <= not( ex3_g16(0) or ( ex3_t16(0) and ex3_g16(1) ) ); 
+ucp4_g32_23:   cp4_g32_23_b <= not( ex3_g16(2) or ( ex3_t16(2) and ex3_g16(3) ) ); 
+ucp4_g32_45:   cp4_g32_45_b <= not( ex3_g16(4) or ( ex3_t16(4) and ex3_g16(5) ) ); 
+ucp4_g32_66:   cp4_g32_66_b <= not( ex3_g16(6)                                  ); 
+
+ucp4_t32_01:   cp4_t32_01_b <= not( ex3_t16(0) and ex3_t16(1) ); 
+ucp4_t32_23:   cp4_t32_23_b <= not( ex3_t16(2) and ex3_t16(3) ); 
+ucp4_t32_45:   cp4_t32_45_b <= not( ex3_t16(4) and ex3_t16(5) ); 
+ucp4_t32_66:   cp4_t32_66_b <= not( ex3_t16(6)                ); 
+
+ucp4_g64_03:   cp4_g64_03   <= not( cp4_g32_01_b and (cp4_t32_01_b or  cp4_g32_23_b) ); 
+ucp4_g64_46:   cp4_g64_46   <= not( cp4_g32_45_b and (cp4_t32_45_b or  cp4_g32_66_b) ); 
+
+ucp4_t64_03:   cp4_t64_03   <= not(                   cp4_t32_01_b or  cp4_t32_23_b  ); 
+ucp4_t64_46:   cp4_t64_46   <= not( cp4_g32_45_b and (cp4_t32_45_b or  cp4_t32_66_b) ); 
+
+ucp4_g128_06:  cp4_g128_06_b <= not( cp4_g64_03 or ( cp4_t64_03 and cp4_g64_46 ) ); 
+ucp4_g128_46:  cp4_g128_46_b <= not(                                cp4_g64_46   ); 
+ucp4_t128_46:  cp4_t128_46_b <= not(                                cp4_t64_46   ); 
+
+ucp4_cog:  ex3_g128(4)   <= not( cp4_g128_46_b);
+ucp4_cogx: cp4_g128_46   <= not( cp4_g128_46_b);
+ucp4_cogb: ex3_g128_b(4) <= not( cp4_g128_46  );
+ucp4_cot:  ex3_t128(4)   <= not( cp4_t128_46_b);
+ucp4_cotx: cp4_t128_46   <= not( cp4_t128_46_b);
+ucp4_cotb: ex3_t128_b(4) <= not( cp4_t128_46  );
+
+ucp4_all1n:    cp4_all1_b <= not ex3_inc_all1     ;
+ucp4_all1p:    cp4_all1_p <= not  cp4_all1_b      ;
+ucp4_co_p0:    cp4_co_p0  <= not( cp4_g128_06_b ) ;
+
+ucp4_espnx: cp4_sel_p0n_x_b <= not( cp4_all1_b    and ex3_effsub_npz);
+ucp4_espny: cp4_sel_p0n_y_b <= not( cp4_g128_06_b and ex3_effsub_npz);
+ucp4_selp0: cp4_sel_p0_b    <= not( cp4_co_p0     and cp4_all1_p and cp4_sub_sticky  );
+ucp4_selp1: cp4_sel_p1_b    <= not( cp4_co_p0     and cp4_all1_p and cp4_sub_stickyn );
+
+ucp4_espn:  ex3_eac_sel_p0n(3) <= not( cp4_sel_p0n_x_b and cp4_sel_p0n_y_b);
+ucp4_esp0:  ex3_eac_sel_p0(3)  <= not( cp4_sel_p0_b    and cp4_add_frcp0_b);
+ucp4_esp1:  ex3_eac_sel_p1(3)  <= not( cp4_sel_p1_b    and cp4_add_frcp1_b);
+
+    cp4_sub_sticky  <=          ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp4_sub_stickyn <=          ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp4_add_frcp1_b <= not(     ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp4_add_frcp0_b <= not(     ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+
+
+ucp5_g32_00:   cp5_g32_00_b <= not( ex3_g16(0)                                  ); 
+ucp5_g32_12:   cp5_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); 
+ucp5_g32_34:   cp5_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); 
+ucp5_g32_56:   cp5_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); 
+
+ucp5_t32_00:   cp5_t32_00_b <= not( ex3_t16(0)                ); 
+ucp5_t32_12:   cp5_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); 
+ucp5_t32_34:   cp5_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); 
+ucp5_t32_56:   cp5_t32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_t16(6) ) ); 
+
+
+ucp5_g64_02:   cp5_g64_02   <= not( cp5_g32_00_b and (cp5_t32_00_b or  cp5_g32_12_b) ); 
+ucp5_g64_36:   cp5_g64_36   <= not( cp5_g32_34_b and (cp5_t32_34_b or  cp5_g32_56_b) ); 
+ucp5_g64_56:   cp5_g64_56   <= not(                                    cp5_g32_56_b  ); 
+
+ucp5_t64_02:   cp5_t64_02   <= not(                   cp5_t32_00_b or  cp5_t32_12_b  ); 
+ucp5_t64_56:   cp5_t64_56   <= not(                                    cp5_t32_56_b  ); 
+
+ucp5_g128_06:  cp5_g128_06_b <= not( cp5_g64_02 or ( cp5_t64_02 and cp5_g64_36 ) ); 
+ucp5_g128_56:  cp5_g128_56_b <= not(                                cp5_g64_56   ); 
+ucp5_t128_56:  cp5_t128_56_b <= not(                                cp5_t64_56   ); 
+
+
+ucp5_cog:  ex3_g128(5)   <= not( cp5_g128_56_b);
+ucp5_cogx: cp5_g128_56   <= not( cp5_g128_56_b);
+ucp5_cogb: ex3_g128_b(5) <= not( cp5_g128_56  );
+ucp5_cot:  ex3_t128(5)   <= not( cp5_t128_56_b);
+ucp5_cotx: cp5_t128_56   <= not( cp5_t128_56_b);
+ucp5_cotb: ex3_t128_b(5) <= not( cp5_t128_56  );
+
+ucp5_all1n:    cp5_all1_b <= not ex3_inc_all1     ;
+ucp5_all1p:    cp5_all1_p <= not  cp5_all1_b      ;
+ucp5_co_p0:    cp5_co_p0  <= not( cp5_g128_06_b ) ;
+
+ucp5_espnx: cp5_sel_p0n_x_b <= not( cp5_all1_b    and ex3_effsub_npz);
+ucp5_espny: cp5_sel_p0n_y_b <= not( cp5_g128_06_b and ex3_effsub_npz);
+ucp5_selp0: cp5_sel_p0_b    <= not( cp5_co_p0     and cp5_all1_p and cp5_sub_sticky  );
+ucp5_selp1: cp5_sel_p1_b    <= not( cp5_co_p0     and cp5_all1_p and cp5_sub_stickyn );
+
+ucp5_espn:  ex3_eac_sel_p0n(4) <= not( cp5_sel_p0n_x_b and cp5_sel_p0n_y_b);
+ucp5_esp0:  ex3_eac_sel_p0(4)  <= not( cp5_sel_p0_b    and cp5_add_frcp0_b);
+ucp5_esp1:  ex3_eac_sel_p1(4)  <= not( cp5_sel_p1_b    and cp5_add_frcp1_b);
+
+    cp5_sub_sticky  <=          ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp5_sub_stickyn <=          ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp5_add_frcp1_b <= not(     ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp5_add_frcp0_b <= not(     ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+
+
+ucp6_g32_00:   cp6_g32_00_b <= not( ex3_g16(0)                                  ); 
+ucp6_g32_12:   cp6_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); 
+ucp6_g32_34:   cp6_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); 
+ucp6_g32_56:   cp6_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); 
+ucp6_g32_66:   cp6_g32_66_b <= not( ex3_g16(6)                                  ); 
+
+ucp6_t32_00:   cp6_t32_00_b <= not( ex3_t16(0)                ); 
+ucp6_t32_12:   cp6_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); 
+ucp6_t32_34:   cp6_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); 
+ucp6_t32_66:   cp6_t32_66_b <= not( ex3_t16(6)                                  ); 
+
+ucp6_g64_02:   cp6_g64_02   <= not( cp6_g32_00_b and (cp6_t32_00_b or  cp6_g32_12_b) ); 
+ucp6_g64_36:   cp6_g64_36   <= not( cp6_g32_34_b and (cp6_t32_34_b or  cp6_g32_56_b) ); 
+
+ucp6_t64_02:   cp6_t64_02   <= not(                   cp6_t32_00_b or  cp6_t32_12_b  ); 
+
+ucp6_g128_06:  cp6_g128_06_b <= not( cp6_g64_02 or ( cp6_t64_02 and cp6_g64_36 ) ); 
+
+
+ucp6_cog:  ex3_g128(6)   <= not( cp6_g32_66_b );
+ucp6_cogx: cp6_g128_66   <= not( cp6_g32_66_b );
+ucp6_cogb: ex3_g128_b(6) <= not( cp6_g128_66  );
+ucp6_cot:  ex3_t128(6)   <= not( cp6_t32_66_b );
+ucp6_cotx: cp6_t128_66   <= not( cp6_t32_66_b );
+ucp6_cotb: ex3_t128_b(6) <= not( cp6_t128_66  );
+
+
+ucp6_all1n:    cp6_all1_b <= not ex3_inc_all1     ;
+ucp6_all1p:    cp6_all1_p <= not  cp6_all1_b      ;
+ucp6_co_p0:    cp6_co_p0  <= not( cp6_g128_06_b ) ;
+
+ucp6_espnx: cp6_sel_p0n_x_b <= not( cp6_all1_b    and ex3_effsub_npz);
+ucp6_espny: cp6_sel_p0n_y_b <= not( cp6_g128_06_b and ex3_effsub_npz);
+ucp6_selp0: cp6_sel_p0_b    <= not( cp6_co_p0     and cp6_all1_p and cp6_sub_sticky  );
+ucp6_selp1: cp6_sel_p1_b    <= not( cp6_co_p0     and cp6_all1_p and cp6_sub_stickyn );
+
+ucp6_espn:  ex3_eac_sel_p0n(5) <= not( cp6_sel_p0n_x_b and cp6_sel_p0n_y_b);
+ucp6_esp0:  ex3_eac_sel_p0(5)  <= not( cp6_sel_p0_b    and cp6_add_frcp0_b);
+ucp6_esp1:  ex3_eac_sel_p1(5)  <= not( cp6_sel_p1_b    and cp6_add_frcp1_b);
+
+    cp6_sub_sticky  <=          ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp6_sub_stickyn <=          ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp6_add_frcp1_b <= not(     ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp6_add_frcp0_b <= not(     ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+
+
+ucp7_g32_00:   cp7_g32_00_b <= not( ex3_g16(0)                                  ) ; 
+ucp7_g32_12:   cp7_g32_12_b <= not( ex3_g16(1) or ( ex3_t16(1) and ex3_g16(2) ) ); 
+ucp7_g32_34:   cp7_g32_34_b <= not( ex3_g16(3) or ( ex3_t16(3) and ex3_g16(4) ) ); 
+ucp7_g32_56:   cp7_g32_56_b <= not( ex3_g16(5) or ( ex3_t16(5) and ex3_g16(6) ) ); 
+
+ucp7_t32_00:   cp7_t32_00_b <= not( ex3_t16(0)                ); 
+ucp7_t32_12:   cp7_t32_12_b <= not( ex3_t16(1) and ex3_t16(2) ); 
+ucp7_t32_34:   cp7_t32_34_b <= not( ex3_t16(3) and ex3_t16(4) ); 
+
+
+ucp7_g64_02:   cp7_g64_02   <= not( cp7_g32_00_b and (cp7_t32_00_b or  cp7_g32_12_b) ); 
+ucp7_g64_36:   cp7_g64_36   <= not( cp7_g32_34_b and (cp7_t32_34_b or  cp7_g32_56_b) ); 
+
+ucp7_t64_02:   cp7_t64_02   <= not(                   cp7_t32_00_b or  cp7_t32_12_b  ); 
+
+ucp7_g128_06:  cp7_g128_06_b <= not( cp7_g64_02 or ( cp7_t64_02 and cp7_g64_36 ) ); 
+
+ucp7_all1n:    cp7_all1_b <= not ex3_inc_all1     ;
+ucp7_all1p:    cp7_all1_p <= not  cp7_all1_b      ;
+ucp7_co_p0:    cp7_co_p0  <= not( cp7_g128_06_b ) ;
+
+ucp7_espnx: cp7_sel_p0n_x_b <= not( cp7_all1_b    and ex3_effsub_npz);
+ucp7_espny: cp7_sel_p0n_y_b <= not( cp7_g128_06_b and ex3_effsub_npz);
+ucp7_selp0: cp7_sel_p0_b    <= not( cp7_co_p0     and cp7_all1_p and cp7_sub_sticky  );
+ucp7_selp1: cp7_sel_p1_b    <= not( cp7_co_p0     and cp7_all1_p and cp7_sub_stickyn );
+
+ucp7_espn:  ex3_eac_sel_p0n(6) <= not( cp7_sel_p0n_x_b and cp7_sel_p0n_y_b);
+ucp7_esp0:  ex3_eac_sel_p0(6)  <= not( cp7_sel_p0_b    and cp7_add_frcp0_b);
+ucp7_esp1:  ex3_eac_sel_p1(6)  <= not( cp7_sel_p1_b    and cp7_add_frcp1_b);
+
+    cp7_sub_sticky  <=          ex3_effsub_npz and     f_alg_ex3_sticky      ;
+    cp7_sub_stickyn <=          ex3_effsub_npz and not f_alg_ex3_sticky      ;
+    cp7_add_frcp1_b <= not(     ex3_effadd_npz and     f_alg_ex3_frc_sel_p1 );
+    cp7_add_frcp0_b <= not(     ex3_effadd_npz and not f_alg_ex3_frc_sel_p1 );
+
+END; 
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg.vhdl

@@ -0,0 +1,958 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+ 
+entity fuq_alg is
+generic(       expand_type               : integer := 2  ); 
+port(
+
+       vdd                                       :inout power_logic;
+       gnd                                       :inout power_logic;
+       clkoff_b                                  :in   std_ulogic; 
+       act_dis                                   :in   std_ulogic; 
+       flush                                     :in   std_ulogic; 
+       delay_lclkr                               :in   std_ulogic_vector(1 to 3); 
+       mpw1_b                                    :in   std_ulogic_vector(1 to 3); 
+       mpw2_b                                    :in   std_ulogic_vector(0 to 0); 
+       sg_1                                      :in   std_ulogic;
+       thold_1                                   :in   std_ulogic;
+       fpu_enable                                :in   std_ulogic; 
+       nclk                                      :in   clk_logic;
+
+
+       f_alg_si                  :in  std_ulogic; 
+       f_alg_so                  :out std_ulogic; 
+       rf1_act                   :in  std_ulogic; 
+       ex1_act                   :in  std_ulogic; 
+
+       f_byp_alg_ex1_b_expo      :in  std_ulogic_vector(1 to 13);
+       f_byp_alg_ex1_a_expo      :in  std_ulogic_vector(1 to 13);
+       f_byp_alg_ex1_c_expo      :in  std_ulogic_vector(1 to 13);
+       f_byp_alg_ex1_b_frac      :in  std_ulogic_vector(0 to 52);
+       f_byp_alg_ex1_b_sign      :in  std_ulogic; 
+
+       f_fmt_ex1_prod_zero        :in  std_ulogic; 
+       f_fmt_ex1_b_zero           :in  std_ulogic; 
+       f_fmt_ex1_pass_sel         :in  std_ulogic; 
+       f_fmt_ex2_pass_frac        :in  std_ulogic_vector(0 to 52);
+
+       f_dcd_rf1_sp               :in  std_ulogic;
+       f_dcd_rf1_from_integer_b   :in  std_ulogic; 
+       f_dcd_rf1_to_integer_b     :in  std_ulogic; 
+       f_dcd_rf1_word_b           :in  std_ulogic;
+       f_dcd_rf1_uns_b            :in  std_ulogic;
+ 
+       f_pic_ex1_rnd_to_int       :in  std_ulogic;
+       f_pic_ex1_frsp_ue1         :in  std_ulogic; 
+       f_pic_ex1_effsub_raw       :in  std_ulogic; 
+       f_pic_ex1_sh_unf_ig_b      :in  std_ulogic; 
+       f_pic_ex1_sh_unf_do        :in  std_ulogic; 
+       f_pic_ex1_sh_ovf_ig_b      :in  std_ulogic; 
+       f_pic_ex1_sh_ovf_do        :in  std_ulogic; 
+       f_pic_ex2_rnd_nr           :in  std_ulogic; 
+       f_pic_ex2_rnd_inf_ok       :in  std_ulogic; 
+
+       f_alg_ex1_sign_frmw        :out std_ulogic; 
+       f_alg_ex2_byp_nonflip      :out std_ulogic;
+       f_alg_ex2_res              :out std_ulogic_vector(0 to 162); 
+       f_alg_ex2_sel_byp          :out std_ulogic; 
+       f_alg_ex2_effsub_eac_b     :out std_ulogic; 
+       f_alg_ex2_prod_z           :out std_ulogic; 
+       f_alg_ex2_sh_unf           :out std_ulogic; 
+       f_alg_ex2_sh_ovf           :out std_ulogic; 
+       f_alg_ex3_frc_sel_p1       :out std_ulogic; 
+       f_alg_ex3_sticky           :out std_ulogic; 
+       f_alg_ex3_int_fr           :out std_ulogic; 
+       f_alg_ex3_int_fi           :out std_ulogic  
+);
+
+
+
+end fuq_alg; 
+
+architecture fuq_alg of fuq_alg is
+
+    constant tiup : std_ulogic := '1';
+    constant tidn : std_ulogic := '0';
+
+    signal thold_0_b, thold_0, forcee  :std_ulogic;
+    signal sg_0                           :std_ulogic;
+    signal ex2_act                          :std_ulogic;
+    signal spare_unused                     :std_ulogic_vector(0 to 3);
+    signal act_so                           :std_ulogic_vector(0 to 4);
+    signal act_si                           :std_ulogic_vector(0 to 4);
+    signal ex1_ctl_so                       :std_ulogic_vector(0 to 4);
+    signal ex1_ctl_si                       :std_ulogic_vector(0 to 4);
+    signal ex2_shd_so, ex2_shd_si           :std_ulogic_vector(0 to 67);
+    signal ex2_shc_so, ex2_shc_si           :std_ulogic_vector(0 to 24);
+    signal ex2_ctl_so                       :std_ulogic_vector(0 to 14);
+    signal ex2_ctl_si                       :std_ulogic_vector(0 to 14);
+    signal ex3_ctl_so                       :std_ulogic_vector(0 to 10);
+    signal ex3_ctl_si                       :std_ulogic_vector(0 to 10);
+    signal ex1_from_integer       :std_ulogic;
+    signal ex2_from_integer       :std_ulogic;
+    signal ex1_to_integer         :std_ulogic;
+    signal ex1_sel_special,  ex1_sel_special_b, ex2_sel_special_b       :std_ulogic;
+    signal ex1_sh_ovf :std_ulogic;
+    signal ex1_sh_unf_x , ex2_sh_unf_x   :std_ulogic;
+    signal ex1_sel_byp_nonflip    :std_ulogic;
+    signal ex1_sel_byp_nonflip_lze    :std_ulogic;
+    signal ex1_from_integer_neg   :std_ulogic;
+    signal ex1_integer_op         :std_ulogic;
+    signal ex1_to_integer_neg     :std_ulogic;
+    signal ex1_negate             :std_ulogic;
+    signal ex1_effsub_alg         :std_ulogic;
+    signal ex2_sh_unf             :std_ulogic;
+    signal ex2_sel_byp            :std_ulogic;
+    signal ex2_effsub_alg         :std_ulogic;
+    signal ex2_prd_sel_pos_hi     :std_ulogic;
+    signal ex2_prd_sel_neg_hi     :std_ulogic;
+    signal ex2_prd_sel_pos_lo     :std_ulogic;
+    signal ex2_prd_sel_neg_lo     :std_ulogic;
+    signal ex2_prd_sel_pos_lohi   :std_ulogic;
+    signal ex2_prd_sel_neg_lohi   :std_ulogic;
+    signal ex2_byp_sel_pos        :std_ulogic;
+    signal ex2_byp_sel_neg        :std_ulogic;
+    signal ex2_byp_sel_byp_pos    :std_ulogic;
+    signal ex2_byp_sel_byp_neg    :std_ulogic;
+    signal ex2_b_sign             :std_ulogic;
+    signal ex2_to_integer         :std_ulogic;
+    signal ex1_sh_lvl2            :std_ulogic_vector(0 to 67)   ;
+    signal ex2_sh_lvl2, ex2_sh_lvl2_b            :std_ulogic_vector(0 to 67)   ;
+    signal ex2_bsha               :std_ulogic_vector(6 to 9)    ;
+    signal ex2_sticky_en16_x      :std_ulogic_vector(0 to 4)    ;
+    signal ex2_xthrm_6_ns_b :std_ulogic;
+    signal ex2_xthrm_7_ns_b :std_ulogic;
+    signal ex2_xthrm_8_b    :std_ulogic;
+    signal ex2_xthrm_8a9_b  :std_ulogic;
+    signal ex2_xthrm_8o9_b  :std_ulogic;
+    signal ex2_xthrm7o8a9   :std_ulogic;
+    signal ex2_xthrm7o8     :std_ulogic;
+    signal ex2_xthrm7o8o9   :std_ulogic;
+    signal ex2_xthrm7a8a9   :std_ulogic;
+    signal ex2_xthrm_6_ns   :std_ulogic;
+    signal ex2_ge176_b      :std_ulogic;
+    signal ex2_ge160_b      :std_ulogic;
+    signal ex2_ge144_b      :std_ulogic;
+    signal ex2_ge128_b      :std_ulogic;
+    signal ex2_ge112_b      :std_ulogic;
+    signal ex1_bsha_6, ex1_bsha_7, ex1_bsha_8, ex1_bsha_9 :std_ulogic;
+    signal ex2_bsha_pos :std_ulogic;
+    signal ex2_sh_lvl3            :std_ulogic_vector(0 to 162)  ;    
+    signal ex2_sticky_or16        :std_ulogic_vector(0 to 4)    ; 
+    signal ex1_b_zero             :std_ulogic                   ;
+    signal ex2_b_zero, ex2_b_zero_b           :std_ulogic                   ;
+
+    signal ex1_dp :std_ulogic;
+
+ signal ex2_byp_nonflip_lze :std_ulogic;
+signal ex2_sel_byp_nonflip    :std_ulogic;
+signal ex2_prod_zero             :std_ulogic;
+signal ex2_sh_ovf_en, ex2_sh_unf_en, ex2_sh_unf_do :std_ulogic;
+signal ex2_sh_ovf                    :std_ulogic;
+signal ex2_integer_op          :std_ulogic;
+signal ex2_negate                 :std_ulogic;
+signal ex2_unf_bz                   :std_ulogic;
+signal ex2_all1_x                :std_ulogic;
+signal ex2_ovf_pz          :std_ulogic;
+signal ex2_all1_y          :std_ulogic;
+ signal ex2_sel_special :std_ulogic;
+ signal rf1_from_integer , rf1_to_integer , rf1_dp :std_ulogic;
+ signal rf1_uns, rf1_word, ex1_uns, ex1_word :std_ulogic;
+ signal ex1_word_from, ex2_word_from :std_ulogic;
+ signal ex2_rnd_to_int :std_ulogic;
+ signal ex1_sign_from :std_ulogic;
+ signal ex1_b_frac :std_ulogic_vector(0 to 52);  
+ signal ex1_b_expo :std_ulogic_vector(1 to 13);  
+ signal ex1_b_sign :std_ulogic;
+ signal ex1_bsha_neg, ex2_bsha_neg : std_ulogic ;
+
+
+    signal ex1_lvl1_shdcd000_b      :std_ulogic;
+    signal ex1_lvl1_shdcd001_b      :std_ulogic;
+    signal ex1_lvl1_shdcd002_b      :std_ulogic;
+    signal ex1_lvl1_shdcd003_b      :std_ulogic;
+    signal ex1_lvl2_shdcd000      :std_ulogic;
+    signal ex1_lvl2_shdcd004      :std_ulogic;
+    signal ex1_lvl2_shdcd008      :std_ulogic;
+    signal ex1_lvl2_shdcd012      :std_ulogic;
+    signal ex1_lvl3_shdcd000      :std_ulogic;
+    signal ex1_lvl3_shdcd016      :std_ulogic;
+    signal ex1_lvl3_shdcd032      :std_ulogic;
+    signal ex1_lvl3_shdcd048      :std_ulogic;
+    signal ex1_lvl3_shdcd064      :std_ulogic;
+    signal ex1_lvl3_shdcd080      :std_ulogic;
+    signal ex1_lvl3_shdcd096      :std_ulogic;
+    signal ex1_lvl3_shdcd112      :std_ulogic;
+    signal ex1_lvl3_shdcd128      :std_ulogic;
+    signal ex1_lvl3_shdcd144      :std_ulogic;
+    signal ex1_lvl3_shdcd160      :std_ulogic;
+    signal ex1_lvl3_shdcd176      :std_ulogic;
+    signal ex1_lvl3_shdcd192 :std_ulogic;
+    signal ex1_lvl3_shdcd208 :std_ulogic;
+    signal ex1_lvl3_shdcd224 :std_ulogic;
+    signal ex1_lvl3_shdcd240 :std_ulogic;
+
+ signal  ex2_lvl3_shdcd000 :std_ulogic;
+ signal  ex2_lvl3_shdcd016 :std_ulogic;
+ signal  ex2_lvl3_shdcd032 :std_ulogic;
+ signal  ex2_lvl3_shdcd048 :std_ulogic;
+ signal  ex2_lvl3_shdcd064 :std_ulogic;
+ signal  ex2_lvl3_shdcd080 :std_ulogic;
+ signal  ex2_lvl3_shdcd096 :std_ulogic;
+ signal  ex2_lvl3_shdcd112 :std_ulogic;
+ signal  ex2_lvl3_shdcd128 :std_ulogic;
+ signal  ex2_lvl3_shdcd144 :std_ulogic;
+ signal  ex2_lvl3_shdcd160 :std_ulogic;
+ signal  ex2_lvl3_shdcd176 :std_ulogic;
+ signal  ex2_lvl3_shdcd192 :std_ulogic;
+ signal  ex2_lvl3_shdcd208 :std_ulogic;
+ signal  ex2_lvl3_shdcd224 :std_ulogic;
+ signal  ex2_lvl3_shdcd240 :std_ulogic;
+
+ signal ex3_int_fr_nr1_b, ex3_int_fr_nr2_b, ex3_int_fr_ok_b :std_ulogic;
+ signal ex3_int_fr :std_ulogic;
+ signal ex3_sel_p1_0_b, ex3_sel_p1_1_b :std_ulogic;
+ signal ex3_sticky_math     :std_ulogic;
+ signal ex3_sticky_toint    :std_ulogic;
+ signal ex3_sticky_toint_nr :std_ulogic;
+ signal ex3_sticky_toint_ok :std_ulogic;
+ signal ex3_frmneg_o_toneg  :std_ulogic;
+ signal ex3_frmneg_o_topos  :std_ulogic;
+ signal ex3_lsb_toint_nr    :std_ulogic;
+ signal ex3_g_math          :std_ulogic;
+ signal ex3_g_toint         :std_ulogic;
+ signal ex3_g_toint_nr      :std_ulogic;
+ signal ex3_g_toint_ok      :std_ulogic;
+ signal ex2_frmneg          :std_ulogic;
+ signal ex2_toneg           :std_ulogic;
+ signal ex2_topos           :std_ulogic;
+ signal ex2_frmneg_o_toneg  :std_ulogic;
+ signal ex2_frmneg_o_topos  :std_ulogic;
+ signal ex2_toint_gate_x    :std_ulogic;
+ signal ex2_toint_gate_g    :std_ulogic;
+ signal ex2_toint_gt_nr_x   :std_ulogic;
+ signal ex2_toint_gt_nr_g   :std_ulogic;
+ signal ex2_toint_gt_ok_x   :std_ulogic;
+ signal ex2_toint_gt_ok_g   :std_ulogic;
+ signal ex2_math_gate_x     :std_ulogic;
+ signal ex2_math_gate_g     :std_ulogic;
+ signal ex2_sticky_eac_x    :std_ulogic;
+ signal ex2_sticky_math     :std_ulogic;
+ signal ex2_sticky_toint    :std_ulogic;
+ signal ex2_sticky_toint_nr :std_ulogic;
+ signal ex2_sticky_toint_ok :std_ulogic;
+ signal ex2_lsb_toint_nr    :std_ulogic;
+ signal ex2_g_math          :std_ulogic;
+ signal ex2_g_toint         :std_ulogic;
+ signal ex2_g_toint_nr      :std_ulogic;
+ signal ex2_g_toint_ok      :std_ulogic;
+ signal ex2_sh16_162, ex2_sh16_163 :std_ulogic;
+ signal alg_ex2_d1clk, alg_ex2_d2clk :std_ulogic;
+
+ signal alg_ex2_lclk :clk_logic;
+
+  signal ex2_bsha_b           :std_ulogic_vector(6 to 9);
+  signal ex2_bsha_neg_b       :std_ulogic;
+  signal ex2_sh_ovf_b         :std_ulogic;
+  signal ex2_sh_unf_x_b       :std_ulogic;
+  signal ex2_lvl3_shdcd000_b  :std_ulogic;
+  signal ex2_lvl3_shdcd016_b  :std_ulogic;
+  signal ex2_lvl3_shdcd032_b  :std_ulogic;
+  signal ex2_lvl3_shdcd048_b  :std_ulogic;
+  signal ex2_lvl3_shdcd064_b  :std_ulogic;
+  signal ex2_lvl3_shdcd080_b  :std_ulogic;
+  signal ex2_lvl3_shdcd096_b  :std_ulogic;
+  signal ex2_lvl3_shdcd112_b  :std_ulogic;
+  signal ex2_lvl3_shdcd128_b  :std_ulogic;
+  signal ex2_lvl3_shdcd144_b  :std_ulogic;
+  signal ex2_lvl3_shdcd160_b  :std_ulogic;
+  signal ex2_lvl3_shdcd176_b  :std_ulogic;
+  signal ex2_lvl3_shdcd192_b  :std_ulogic;
+  signal ex2_lvl3_shdcd208_b  :std_ulogic;
+  signal ex2_lvl3_shdcd224_b  :std_ulogic;
+  signal ex2_lvl3_shdcd240_b  :std_ulogic;
+  signal ex2_b_zero_l2_b           :std_ulogic;
+  signal ex2_prod_zero_b           :std_ulogic;
+  signal ex2_byp_nonflip_lze_b     :std_ulogic;
+  signal ex2_sel_byp_nonflip_b     :std_ulogic;
+  signal ex2_sh_unf_do_b           :std_ulogic;
+  signal ex2_sh_unf_en_b           :std_ulogic;
+  signal ex2_sh_ovf_en_b           :std_ulogic;
+  signal ex2_effsub_alg_b          :std_ulogic;
+  signal ex2_negate_b              :std_ulogic;
+  signal ex2_b_sign_b              :std_ulogic;
+  signal ex2_to_integer_b          :std_ulogic;
+  signal ex2_from_integer_b        :std_ulogic;
+  signal ex2_rnd_to_int_b          :std_ulogic;
+  signal ex2_integer_op_b          :std_ulogic;
+  signal ex2_word_from_b           :std_ulogic;
+
+ signal unused :std_ulogic;
+
+
+begin
+
+   unused <= ex1_b_expo(1) or ex1_b_expo(2) or
+             ex1_dp or 
+             ex2_lvl3_shdcd176 ;
+
+   ex1_b_frac(0 to 52) <=  f_byp_alg_ex1_b_frac(0 to 52); 
+   ex1_b_sign          <=  f_byp_alg_ex1_b_sign ;         
+   ex1_b_expo(1 to 13) <=  f_byp_alg_ex1_b_expo(1 to 13); 
+
+
+    thold_reg_0:  tri_plat  generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,  
+         flush     => flush ,
+         din(0)    => thold_1,   
+         q(0)      => thold_0  ); 
+    
+    sg_reg_0:  tri_plat     generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,
+         flush     => flush ,
+         din(0)    => sg_1  ,     
+         q(0)      => sg_0  );   
+
+
+    lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
+        clkoff_b     => clkoff_b,
+        thold        => thold_0,  
+        sg           => sg_0,
+        act_dis      => act_dis,
+        forcee => forcee,
+        thold_b      => thold_0_b );
+
+
+
+
+
+    act_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( 
+        vd               => vdd,
+        gd               => gnd,
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)  ,
+        mpw1_b           => mpw1_b(2)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        nclk             => nclk,
+        act              => fpu_enable,
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        scout            => act_so  ,                      
+        scin             => act_si  ,                    
+         din(0)             => spare_unused(0),
+         din(1)             => spare_unused(1),
+         din(2)             => ex1_act,
+         din(3)             => spare_unused(2),
+         din(4)             => spare_unused(3),
+        dout(0)             => spare_unused(0),
+        dout(1)             => spare_unused(1),
+        dout(2)             => ex2_act,
+        dout(3)             => spare_unused(2) ,
+        dout(4)             => spare_unused(3) );
+
+
+    alg_ex2_lcb : tri_lcbnd generic map (expand_type => expand_type) port map(
+        delay_lclkr =>  delay_lclkr(2) ,
+        mpw1_b      =>  mpw1_b(2)      ,
+        mpw2_b      =>  mpw2_b(0)      ,
+        forcee => forcee,
+        nclk        =>  nclk                 ,
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        act         =>  ex1_act              ,
+        sg          =>  sg_0                 ,
+        thold_b     =>  thold_0_b            ,
+        d1clk       =>  alg_ex2_d1clk        ,
+        d2clk       =>  alg_ex2_d2clk        ,
+        lclk        =>  alg_ex2_lclk        );
+
+
+
+
+
+
+
+ 
+
+
+
+    rf1_from_integer    <= not f_dcd_rf1_from_integer_b ;
+    rf1_to_integer      <= not f_dcd_rf1_to_integer_b ;
+    rf1_dp              <= not f_dcd_rf1_sp ;
+    rf1_word            <= not f_dcd_rf1_word_b ;
+    rf1_uns             <= not f_dcd_rf1_uns_b ;
+
+
+   ex1_ctl_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(1)  ,
+        mpw1_b           => mpw1_b(1)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd          ,
+        gd               => gnd          ,
+        nclk             => nclk         , 
+        thold_b          => thold_0_b    ,
+        sg               => sg_0         , 
+        act              => rf1_act      , 
+        scout            => ex1_ctl_so   ,                      
+        scin             => ex1_ctl_si   ,                    
+        din(0)           => rf1_from_integer ,
+        din(1)           => rf1_to_integer ,
+        din(2)           => rf1_dp  ,
+        din(3)           => rf1_word  ,
+        din(4)           => rf1_uns  ,
+        dout(0)          => ex1_from_integer ,
+        dout(1)          => ex1_to_integer ,
+        dout(2)          => ex1_dp    ,
+        dout(3)          => ex1_word  ,
+        dout(4)          => ex1_uns   );
+
+
+
+
+ sha: entity work.fuq_alg_add(fuq_alg_add) generic map (expand_type => expand_type) port map(
+       vdd                           => vdd,
+       gnd                           => gnd,
+       f_byp_alg_ex1_b_expo(1 to 13) => f_byp_alg_ex1_b_expo ,
+       f_byp_alg_ex1_a_expo(1 to 13) => f_byp_alg_ex1_a_expo ,
+       f_byp_alg_ex1_c_expo(1 to 13) => f_byp_alg_ex1_c_expo ,
+       ex1_sel_special_b             => ex1_sel_special_b    ,
+       ex1_bsha_6_o                  => ex1_bsha_6           ,
+       ex1_bsha_7_o                  => ex1_bsha_7           ,
+       ex1_bsha_8_o                  => ex1_bsha_8           ,
+       ex1_bsha_9_o                  => ex1_bsha_9           ,
+       ex1_bsha_neg_o                => ex1_bsha_neg         ,
+       ex1_sh_ovf                    => ex1_sh_ovf           ,
+       ex1_sh_unf_x                  => ex1_sh_unf_x         ,
+       ex1_lvl1_shdcd000_b           => ex1_lvl1_shdcd000_b  ,
+       ex1_lvl1_shdcd001_b           => ex1_lvl1_shdcd001_b  ,
+       ex1_lvl1_shdcd002_b           => ex1_lvl1_shdcd002_b  ,
+       ex1_lvl1_shdcd003_b           => ex1_lvl1_shdcd003_b  ,
+       ex1_lvl2_shdcd000             => ex1_lvl2_shdcd000    ,
+       ex1_lvl2_shdcd004             => ex1_lvl2_shdcd004    ,
+       ex1_lvl2_shdcd008             => ex1_lvl2_shdcd008    ,
+       ex1_lvl2_shdcd012             => ex1_lvl2_shdcd012    ,
+       ex1_lvl3_shdcd000             => ex1_lvl3_shdcd000    ,
+       ex1_lvl3_shdcd016             => ex1_lvl3_shdcd016    ,
+       ex1_lvl3_shdcd032             => ex1_lvl3_shdcd032    ,
+       ex1_lvl3_shdcd048             => ex1_lvl3_shdcd048    ,
+       ex1_lvl3_shdcd064             => ex1_lvl3_shdcd064    ,
+       ex1_lvl3_shdcd080             => ex1_lvl3_shdcd080    ,
+       ex1_lvl3_shdcd096             => ex1_lvl3_shdcd096    ,
+       ex1_lvl3_shdcd112             => ex1_lvl3_shdcd112    ,
+       ex1_lvl3_shdcd128             => ex1_lvl3_shdcd128    ,
+       ex1_lvl3_shdcd144             => ex1_lvl3_shdcd144    ,
+       ex1_lvl3_shdcd160             => ex1_lvl3_shdcd160    ,
+       ex1_lvl3_shdcd176             => ex1_lvl3_shdcd176    ,
+       ex1_lvl3_shdcd192             => ex1_lvl3_shdcd192    ,
+       ex1_lvl3_shdcd208             => ex1_lvl3_shdcd208    ,
+       ex1_lvl3_shdcd224             => ex1_lvl3_shdcd224    ,
+       ex1_lvl3_shdcd240             => ex1_lvl3_shdcd240   );
+
+       ex1_sel_special   <= ex1_from_integer ;
+       ex1_sel_special_b <= not ex1_from_integer ;
+
+
+
+
+    ex1_sel_byp_nonflip_lze <=
+               ( f_fmt_ex1_pass_sel   ) or 
+               ( f_pic_ex1_sh_ovf_do  )  ; 
+
+    ex1_sel_byp_nonflip <=
+               ( f_pic_ex1_frsp_ue1   ) or 
+               ( f_fmt_ex1_pass_sel   ) or 
+               ( f_pic_ex1_sh_ovf_do  )  ; 
+
+    ex1_integer_op <= ex1_from_integer or  (ex1_to_integer and not f_pic_ex1_rnd_to_int);
+
+
+    f_alg_ex1_sign_frmw <= ex1_b_frac(21) ; 
+
+    ex1_sign_from <=
+         (ex1_from_integer and     ex1_word and ex1_b_frac(21) ) or 
+         (ex1_from_integer and not ex1_word and ex1_b_sign     );
+
+    ex1_from_integer_neg <= ex1_from_integer and ex1_sign_from and not ex1_uns;
+
+    ex1_word_from <= ex1_word and ex1_from_integer ;
+
+    ex1_to_integer_neg   <= ex1_to_integer   and ex1_b_sign and not f_pic_ex1_rnd_to_int;
+                       
+    ex1_negate <=     f_pic_ex1_effsub_raw or 
+                      ex1_from_integer_neg or 
+                      ex1_to_integer_neg   ;
+
+    ex1_effsub_alg     <= f_pic_ex1_effsub_raw and not f_fmt_ex1_pass_sel;
+
+    ex1_b_zero     <= f_fmt_ex1_b_zero;
+
+
+   
+
+
+
+ sh4: entity work.fuq_alg_sh4(fuq_alg_sh4) generic map (expand_type => expand_type) port map(
+      ex1_lvl1_shdcd000_b   => ex1_lvl1_shdcd000_b   ,
+      ex1_lvl1_shdcd001_b   => ex1_lvl1_shdcd001_b   ,
+      ex1_lvl1_shdcd002_b   => ex1_lvl1_shdcd002_b   ,
+      ex1_lvl1_shdcd003_b   => ex1_lvl1_shdcd003_b   ,
+      ex1_lvl2_shdcd000     => ex1_lvl2_shdcd000     ,
+      ex1_lvl2_shdcd004     => ex1_lvl2_shdcd004     ,
+      ex1_lvl2_shdcd008     => ex1_lvl2_shdcd008     ,
+      ex1_lvl2_shdcd012     => ex1_lvl2_shdcd012     ,
+      ex1_sel_special       => ex1_sel_special       ,
+      ex1_b_sign            => ex1_b_sign            ,
+      ex1_b_expo(3 to 13)   => ex1_b_expo(3 to 13)   ,
+      ex1_b_frac(0 to 52)   => ex1_b_frac(0 to 52)   ,
+      ex1_sh_lvl2(0 to 67)  => ex1_sh_lvl2(0 to 67) );
+
+
+    ex2_shd_lat:   entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 68, btr => "NLI0001_X2_A12TH",  expand_type => expand_type,  needs_sreset => 0  ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK             => alg_ex2_lclk               ,
+        D1CLK            => alg_ex2_d1clk              ,
+        D2CLK            => alg_ex2_d2clk              ,
+        SCANIN           => ex2_shd_si                 ,                    
+        SCANOUT          => ex2_shd_so                 ,                      
+        D                => ex1_sh_lvl2  (0 to 67)     ,
+        QB               => ex2_sh_lvl2_b(0 to 67)    );
+
+    ex2_sh_lvl2(0 to 67) <= not ex2_sh_lvl2_b(0 to 67) ;   
+
+
+    ex2_shc_lat:  entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 25, btr => "NLI0001_X2_A12TH",  expand_type => expand_type,  needs_sreset => 0  ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK             => alg_ex2_lclk               ,
+        D1CLK            => alg_ex2_d1clk              ,
+        D2CLK            => alg_ex2_d2clk              ,
+        SCANIN           => ex2_shc_si                 ,                    
+        SCANOUT          => ex2_shc_so                 ,                      
+         D(0)             => ex1_bsha_neg      ,
+         D(1)             => ex1_sh_ovf        ,
+         D(2)             => ex1_sh_unf_x      ,
+         D(3)             => ex1_sel_special ,
+         D(4)             => ex1_sel_special_b,
+         D(5)             => ex1_bsha_6  ,
+         D(6)             => ex1_bsha_7  ,
+         D(7)             => ex1_bsha_8  ,
+         D(8)             => ex1_bsha_9  ,
+         D(9)             => ex1_lvl3_shdcd000 , 
+         D(10)            => ex1_lvl3_shdcd016 ,
+         D(11)            => ex1_lvl3_shdcd032 ,
+         D(12)            => ex1_lvl3_shdcd048 ,
+         D(13)            => ex1_lvl3_shdcd064 ,
+         D(14)            => ex1_lvl3_shdcd080 ,
+         D(15)            => ex1_lvl3_shdcd096 ,
+         D(16)            => ex1_lvl3_shdcd112 ,
+         D(17)            => ex1_lvl3_shdcd128 ,
+         D(18)            => ex1_lvl3_shdcd144 ,
+         D(19)            => ex1_lvl3_shdcd160 ,
+         D(20)            => ex1_lvl3_shdcd176 ,
+         D(21)            => ex1_lvl3_shdcd192 ,
+         D(22)            => ex1_lvl3_shdcd208 ,
+         D(23)            => ex1_lvl3_shdcd224 ,
+         D(24)            => ex1_lvl3_shdcd240 ,
+         QB(0)            => ex2_bsha_neg_b       ,
+         QB(1)            => ex2_sh_ovf_b         ,
+         QB(2)            => ex2_sh_unf_x_b       ,
+         QB(3)            => ex2_sel_special_b    ,
+         QB(4)            => ex2_sel_special      ,
+         QB(5)            => ex2_bsha_b(6)        ,
+         QB(6)            => ex2_bsha_b(7)        ,
+         QB(7)            => ex2_bsha_b(8)        ,
+         QB(8)            => ex2_bsha_b(9)        ,
+         QB(9)            => ex2_lvl3_shdcd000_b  , 
+         QB(10)           => ex2_lvl3_shdcd016_b  ,
+         QB(11)           => ex2_lvl3_shdcd032_b  ,
+         QB(12)           => ex2_lvl3_shdcd048_b  ,
+         QB(13)           => ex2_lvl3_shdcd064_b  ,
+         QB(14)           => ex2_lvl3_shdcd080_b  ,
+         QB(15)           => ex2_lvl3_shdcd096_b  ,
+         QB(16)           => ex2_lvl3_shdcd112_b  ,
+         QB(17)           => ex2_lvl3_shdcd128_b  ,
+         QB(18)           => ex2_lvl3_shdcd144_b  ,
+         QB(19)           => ex2_lvl3_shdcd160_b  ,
+         QB(20)           => ex2_lvl3_shdcd176_b  ,
+         QB(21)           => ex2_lvl3_shdcd192_b  ,
+         QB(22)           => ex2_lvl3_shdcd208_b  ,
+         QB(23)           => ex2_lvl3_shdcd224_b  ,
+         QB(24)           => ex2_lvl3_shdcd240_b );
+
+
+         ex2_bsha_neg         <= not ex2_bsha_neg_b       ;
+         ex2_sh_ovf           <= not ex2_sh_ovf_b         ;
+         ex2_sh_unf_x         <= not ex2_sh_unf_x_b       ;
+         ex2_bsha(6)          <= not ex2_bsha_b(6)        ;
+         ex2_bsha(7)          <= not ex2_bsha_b(7)        ;
+         ex2_bsha(8)          <= not ex2_bsha_b(8)        ;
+         ex2_bsha(9)          <= not ex2_bsha_b(9)        ;
+         ex2_lvl3_shdcd000    <= not ex2_lvl3_shdcd000_b  ;
+         ex2_lvl3_shdcd016    <= not ex2_lvl3_shdcd016_b  ;
+         ex2_lvl3_shdcd032    <= not ex2_lvl3_shdcd032_b  ;
+         ex2_lvl3_shdcd048    <= not ex2_lvl3_shdcd048_b  ;
+         ex2_lvl3_shdcd064    <= not ex2_lvl3_shdcd064_b  ;
+         ex2_lvl3_shdcd080    <= not ex2_lvl3_shdcd080_b  ;
+         ex2_lvl3_shdcd096    <= not ex2_lvl3_shdcd096_b  ;
+         ex2_lvl3_shdcd112    <= not ex2_lvl3_shdcd112_b  ;
+         ex2_lvl3_shdcd128    <= not ex2_lvl3_shdcd128_b  ;
+         ex2_lvl3_shdcd144    <= not ex2_lvl3_shdcd144_b  ;
+         ex2_lvl3_shdcd160    <= not ex2_lvl3_shdcd160_b  ;
+         ex2_lvl3_shdcd176    <= not ex2_lvl3_shdcd176_b  ;
+         ex2_lvl3_shdcd192    <= not ex2_lvl3_shdcd192_b  ;
+         ex2_lvl3_shdcd208    <= not ex2_lvl3_shdcd208_b  ;
+         ex2_lvl3_shdcd224    <= not ex2_lvl3_shdcd224_b  ;
+         ex2_lvl3_shdcd240    <= not ex2_lvl3_shdcd240_b  ;
+
+
+
+
+    ex2_ctl_lat:  entity tri.tri_inv_nlats(tri_inv_nlats) generic map (width=> 15, btr => "NLI0001_X2_A12TH",  expand_type => expand_type,  needs_sreset => 0  ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK             => alg_ex2_lclk               ,
+        D1CLK            => alg_ex2_d1clk              ,
+        D2CLK            => alg_ex2_d2clk              ,
+        SCANIN           => ex2_ctl_si                 ,                    
+        SCANOUT          => ex2_ctl_so                 ,                      
+         D(0)             => ex1_b_zero                ,
+         D(1)             => f_fmt_ex1_prod_zero       ,
+         D(2)             => ex1_sel_byp_nonflip_lze   ,
+         D(3)             => ex1_sel_byp_nonflip       ,
+         D(4)             => f_pic_ex1_sh_unf_do       ,
+         D(5)             => f_pic_ex1_sh_unf_ig_b     ,  
+         D(6)             => f_pic_ex1_sh_ovf_ig_b     ,   
+         D(7)             => ex1_effsub_alg            ,
+         D(8)             => ex1_negate                ,
+         D(9)             => ex1_b_sign                ,
+         D(10)            => ex1_to_integer            ,
+         D(11)            => ex1_from_integer          ,
+         D(12)            => f_pic_ex1_rnd_to_int      ,
+         D(13)            => ex1_integer_op            ,
+         D(14)            => ex1_word_from             ,
+         QB(0)            => ex2_b_zero_l2_b           ,
+         QB(1)            => ex2_prod_zero_b           ,
+         QB(2)            => ex2_byp_nonflip_lze_b     ,
+         QB(3)            => ex2_sel_byp_nonflip_b     ,
+         QB(4)            => ex2_sh_unf_do_b           ,
+         QB(5)            => ex2_sh_unf_en_b           ,
+         QB(6)            => ex2_sh_ovf_en_b           ,
+         QB(7)            => ex2_effsub_alg_b          ,
+         QB(8)            => ex2_negate_b              ,
+         QB(9)            => ex2_b_sign_b              ,
+         QB(10)           => ex2_to_integer_b          ,
+         QB(11)           => ex2_from_integer_b        ,
+         QB(12)           => ex2_rnd_to_int_b          ,
+         QB(13)           => ex2_integer_op_b          ,
+         QB(14)           => ex2_word_from_b          );
+
+
+         ex2_b_zero             <= not ex2_b_zero_l2_b           ;
+         ex2_prod_zero          <= not ex2_prod_zero_b           ;
+         ex2_byp_nonflip_lze    <= not ex2_byp_nonflip_lze_b     ;
+         ex2_sel_byp_nonflip    <= not ex2_sel_byp_nonflip_b     ;
+         ex2_sh_unf_do          <= not ex2_sh_unf_do_b           ;
+         ex2_sh_unf_en          <= not ex2_sh_unf_en_b           ;
+         ex2_sh_ovf_en          <= not ex2_sh_ovf_en_b           ;
+         ex2_effsub_alg         <= not ex2_effsub_alg_b          ;
+         ex2_negate             <= not ex2_negate_b              ;
+         ex2_b_sign             <= not ex2_b_sign_b              ;
+         ex2_to_integer         <= not ex2_to_integer_b          ;
+         ex2_from_integer       <= not ex2_from_integer_b        ;
+         ex2_rnd_to_int         <= not ex2_rnd_to_int_b          ;
+         ex2_integer_op         <= not ex2_integer_op_b          ;
+         ex2_word_from          <= not ex2_word_from_b           ;
+
+
+
+
+
+
+            ex2_xthrm_6_ns_b <= not( ex2_bsha(6) and ex2_sel_special_b );
+            ex2_xthrm_7_ns_b <= not( ex2_bsha(7) and ex2_sel_special_b );
+            ex2_xthrm_8_b    <= not( ex2_bsha(8) );
+            ex2_xthrm_8a9_b  <= not( ex2_bsha(8) and ex2_bsha(9) );
+            ex2_xthrm_8o9_b  <= not( ex2_bsha(8) or  ex2_bsha(9) );
+
+            ex2_xthrm7o8a9   <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8a9_b );
+            ex2_xthrm7o8     <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8_b   );
+            ex2_xthrm7o8o9   <= not( ex2_xthrm_7_ns_b and ex2_xthrm_8o9_b );
+            ex2_xthrm7a8a9   <= not( ex2_xthrm_7_ns_b or  ex2_xthrm_8a9_b );
+            ex2_xthrm_6_ns   <= not( ex2_xthrm_6_ns_b );
+
+            ex2_ge176_b      <= not( ex2_xthrm_6_ns and ex2_xthrm7o8a9 );
+            ex2_ge160_b      <= not( ex2_xthrm_6_ns and ex2_xthrm7o8   );
+            ex2_ge144_b      <= not( ex2_xthrm_6_ns and ex2_xthrm7o8o9 );
+            ex2_ge128_b      <= not( ex2_xthrm_6_ns                    );
+            ex2_ge112_b      <= not( ex2_xthrm_6_ns or  ex2_xthrm7a8a9 );
+
+            ex2_sticky_en16_x(0) <= not ex2_ge176_b ;
+            ex2_sticky_en16_x(1) <= not ex2_ge160_b ;
+            ex2_sticky_en16_x(2) <= not ex2_ge144_b ;
+            ex2_sticky_en16_x(3) <= not ex2_ge128_b ;
+            ex2_sticky_en16_x(4) <= not ex2_ge112_b ;
+
+
+
+
+
+
+ ex2_b_zero_b <= not ex2_b_zero ;
+
+
+     f_alg_ex2_byp_nonflip   <=     ex2_byp_nonflip_lze ;
+     f_alg_ex2_sel_byp       <=     ex2_sel_byp      ;
+     f_alg_ex2_effsub_eac_b  <= not ex2_effsub_alg   ;
+     f_alg_ex2_prod_z        <=     ex2_prod_zero    ;
+     f_alg_ex2_sh_unf        <=     ex2_sh_unf       ;
+     f_alg_ex2_sh_ovf        <=     ex2_ovf_pz       ;
+
+
+
+
+
+
+   or16: entity work.fuq_alg_or16(fuq_alg_or16) generic map (expand_type => expand_type) port map (
+         ex2_sh_lvl2(0 to 67)      => ex2_sh_lvl2(0 to 67)      ,
+         ex2_sticky_or16(0 to 4)   => ex2_sticky_or16(0 to 4)  );
+
+
+   sh16: entity work.fuq_alg_sh16(fuq_alg_sh16) generic map (expand_type => expand_type) port map (
+         ex2_lvl3_shdcd000        => ex2_lvl3_shdcd000       ,
+         ex2_lvl3_shdcd016        => ex2_lvl3_shdcd016       ,
+         ex2_lvl3_shdcd032        => ex2_lvl3_shdcd032       ,
+         ex2_lvl3_shdcd048        => ex2_lvl3_shdcd048       ,
+         ex2_lvl3_shdcd064        => ex2_lvl3_shdcd064       ,
+         ex2_lvl3_shdcd080        => ex2_lvl3_shdcd080       ,
+         ex2_lvl3_shdcd096        => ex2_lvl3_shdcd096       ,
+         ex2_lvl3_shdcd112        => ex2_lvl3_shdcd112       ,
+         ex2_lvl3_shdcd128        => ex2_lvl3_shdcd128       ,
+         ex2_lvl3_shdcd144        => ex2_lvl3_shdcd144       ,
+         ex2_lvl3_shdcd160        => ex2_lvl3_shdcd160       ,
+         ex2_lvl3_shdcd192        => ex2_lvl3_shdcd192       ,
+         ex2_lvl3_shdcd208        => ex2_lvl3_shdcd208       ,
+         ex2_lvl3_shdcd224        => ex2_lvl3_shdcd224       ,
+         ex2_lvl3_shdcd240        => ex2_lvl3_shdcd240       ,
+         ex2_sel_special          => ex2_sel_special         ,
+         ex2_sh_lvl2(0 to 67)     => ex2_sh_lvl2(0 to 67)    ,
+         ex2_sh16_162             => ex2_sh16_162            ,
+         ex2_sh16_163             => ex2_sh16_163            ,
+         ex2_sh_lvl3(0 to 162)    => ex2_sh_lvl3(0 to 162)  );
+
+
+
+    ex2_ovf_pz     <= ex2_prod_zero or (ex2_sh_ovf and ex2_sh_ovf_en and not ex2_b_zero);
+    ex2_sel_byp    <= ex2_sel_byp_nonflip or ex2_ovf_pz          ;
+    ex2_all1_y     <= ex2_negate and ex2_ovf_pz ;
+    ex2_all1_x     <= ex2_negate and ex2_unf_bz ;
+    ex2_sh_unf     <= ex2_sh_unf_do or ( ex2_sh_unf_en and ex2_sh_unf_x and not ex2_prod_zero);                     
+    ex2_unf_bz     <= ex2_b_zero    or   ex2_sh_unf ;
+
+
+
+
+    ex2_byp_sel_byp_pos <=     
+               ( ex2_sel_byp_nonflip                                                              ) or
+               ( ex2_ovf_pz          and not ex2_integer_op and not ex2_negate and not ex2_unf_bz ) or 
+               ( ex2_ovf_pz          and not ex2_integer_op and ex2_all1_x                        );
+
+    ex2_byp_sel_byp_neg <= not ex2_sel_byp_nonflip and 
+                               ex2_ovf_pz          and not ex2_integer_op and      ex2_negate ;
+
+    ex2_byp_sel_pos     <=
+               ( not ex2_sel_byp         and not ex2_integer_op and not ex2_negate and not ex2_unf_bz ) or 
+               ( not ex2_sel_byp         and not ex2_integer_op and ex2_all1_x                        );
+    ex2_byp_sel_neg     <=
+               ( not ex2_sel_byp         and not ex2_integer_op and     ex2_negate                    );
+
+
+    ex2_prd_sel_pos_hi    <= ex2_prd_sel_pos_lo and not ex2_integer_op ;
+    ex2_prd_sel_neg_hi    <= ex2_prd_sel_neg_lo and not ex2_integer_op ;
+
+    ex2_prd_sel_pos_lohi  <= ex2_prd_sel_pos_lo and not ex2_word_from ;
+    ex2_prd_sel_neg_lohi  <= ex2_prd_sel_neg_lo and not ex2_word_from ;
+
+
+    ex2_prd_sel_pos_lo  <=
+               ( not ex2_sel_byp_nonflip and not ex2_ovf_pz and not ex2_unf_bz and not ex2_negate ) or  
+               ( not ex2_sel_byp_nonflip and ex2_all1_x                                           ) or 
+               ( not ex2_sel_byp_nonflip and ex2_all1_y                                           ) ; 
+    ex2_prd_sel_neg_lo  <=
+               ( not ex2_sel_byp_nonflip and                                           ex2_negate ) ;
+
+
+
+   bymx: entity work.fuq_alg_bypmux(fuq_alg_bypmux) generic map (expand_type => expand_type) port map (
+      ex2_byp_sel_byp_neg           => ex2_byp_sel_byp_neg             ,
+      ex2_byp_sel_byp_pos           => ex2_byp_sel_byp_pos             ,
+      ex2_byp_sel_neg               => ex2_byp_sel_neg                 ,
+      ex2_byp_sel_pos               => ex2_byp_sel_pos                 ,
+      ex2_prd_sel_neg_hi            => ex2_prd_sel_neg_hi              ,
+      ex2_prd_sel_neg_lo            => ex2_prd_sel_neg_lo              ,
+      ex2_prd_sel_neg_lohi          => ex2_prd_sel_neg_lohi            ,
+      ex2_prd_sel_pos_hi            => ex2_prd_sel_pos_hi              ,
+      ex2_prd_sel_pos_lo            => ex2_prd_sel_pos_lo              ,
+      ex2_prd_sel_pos_lohi          => ex2_prd_sel_pos_lohi            ,
+      ex2_sh_lvl3(0 to 162)         => ex2_sh_lvl3(0 to 162)           ,
+      f_fmt_ex2_pass_frac(0 to 52)  => f_fmt_ex2_pass_frac(0 to 52)    ,
+      f_alg_ex2_res(0 to 162)       => f_alg_ex2_res(0 to 162)        );
+
+
+
+ ex2_frmneg          <= ex2_from_integer and   ex2_negate; 
+ ex2_toneg           <= (ex2_to_integer and not ex2_rnd_to_int and     ex2_b_sign) ; 
+ ex2_topos           <= (ex2_to_integer and not ex2_rnd_to_int and not ex2_b_sign) or      ex2_rnd_to_int; 
+ ex2_frmneg_o_toneg  <= ex2_frmneg or ex2_toneg;
+ ex2_frmneg_o_topos  <= ex2_frmneg or ex2_topos;
+
+ ex2_math_gate_x     <= not ex2_sel_byp_nonflip and ex2_b_zero_b and  not ex2_ovf_pz      ;
+ ex2_toint_gate_x    <= ex2_to_integer          and ex2_b_zero_b                          ;
+ ex2_toint_gt_nr_x   <= ex2_to_integer          and ex2_b_zero_b and f_pic_ex2_rnd_nr     ;
+ ex2_toint_gt_ok_x   <= ex2_to_integer          and ex2_b_zero_b and f_pic_ex2_rnd_inf_ok ;
+
+ ex2_math_gate_g     <= not ex2_sel_byp_nonflip and  not ex2_ovf_pz and ex2_b_zero_b and (ex2_prd_sel_pos_lo or ex2_prd_sel_neg_lo);
+ ex2_toint_gate_g    <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b;
+ ex2_toint_gt_nr_g   <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b and f_pic_ex2_rnd_nr     ;
+ ex2_toint_gt_ok_g   <= ex2_to_integer and not ex2_ovf_pz and not ex2_sh_unf and ex2_b_zero_b and f_pic_ex2_rnd_inf_ok ;
+
+    ex2_bsha_pos <= not ex2_bsha_neg ;
+
+    ex2_sticky_eac_x <= 
+         ( (ex2_sh_unf or ex2_sticky_en16_x(0)) and  ex2_sticky_or16(0)  and ex2_bsha_pos  ) or  
+         ( (ex2_sh_unf or ex2_sticky_en16_x(1)) and  ex2_sticky_or16(1)  and ex2_bsha_pos  ) or  
+         ( (ex2_sh_unf or ex2_sticky_en16_x(2)) and  ex2_sticky_or16(2)  and ex2_bsha_pos  ) or  
+         ( (ex2_sh_unf or ex2_sticky_en16_x(3)) and  ex2_sticky_or16(3)  and ex2_bsha_pos  ) or  
+         ( (ex2_sh_unf or ex2_sticky_en16_x(4)) and  ex2_sticky_or16(4)  and ex2_bsha_pos  ) ;
+
+    
+ ex2_sticky_math     <= ex2_sticky_eac_x and ex2_math_gate_x ;
+ ex2_sticky_toint    <= ex2_sticky_eac_x and ex2_toint_gate_x;
+ ex2_sticky_toint_nr <= ex2_sticky_eac_x and ex2_toint_gt_nr_x;
+ ex2_sticky_toint_ok <= ex2_sticky_eac_x and ex2_toint_gt_ok_x ;
+
+ ex2_lsb_toint_nr    <= (ex2_sh16_162 or ex2_rnd_to_int)       and ex2_toint_gt_nr_g ;
+
+ ex2_g_math          <= ex2_sh16_163     and ex2_math_gate_g ;
+ ex2_g_toint         <= ex2_sh16_163     and ex2_toint_gate_g; 
+ ex2_g_toint_nr      <= ex2_sh16_163     and ex2_toint_gt_nr_g ;
+ ex2_g_toint_ok      <= ex2_sh16_163     and ex2_toint_gt_ok_g ;
+
+
+
+
+
+  ex3_ctl_lat:  tri_rlmreg_p generic map (width=> 11, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(3)  ,
+        mpw1_b           => mpw1_b(3)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd          ,
+        gd               => gnd          ,
+        nclk             => nclk         , 
+        thold_b          => thold_0_b    ,
+        sg               => sg_0         , 
+        act              => ex2_act      , 
+        scout            => ex3_ctl_so   ,                      
+        scin             => ex3_ctl_si   ,                    
+         din(0)          => ex2_sticky_math     , 
+         din(1)          => ex2_sticky_toint    ,
+         din(2)          => ex2_sticky_toint_nr ,
+         din(3)          => ex2_sticky_toint_ok ,
+         din(4)          => ex2_frmneg_o_toneg  ,
+         din(5)          => ex2_frmneg_o_topos  ,
+         din(6)          => ex2_lsb_toint_nr    ,
+         din(7)          => ex2_g_math          ,
+         din(8)          => ex2_g_toint         ,
+         din(9)          => ex2_g_toint_nr      ,
+         din(10)         => ex2_g_toint_ok      ,
+         dout(0)         => ex3_sticky_math     , 
+         dout(1)         => ex3_sticky_toint    ,
+         dout(2)         => ex3_sticky_toint_nr ,
+         dout(3)         => ex3_sticky_toint_ok ,
+         dout(4)         => ex3_frmneg_o_toneg  ,
+         dout(5)         => ex3_frmneg_o_topos  ,
+         dout(6)         => ex3_lsb_toint_nr    ,
+         dout(7)         => ex3_g_math          ,
+         dout(8)         => ex3_g_toint         ,
+         dout(9)         => ex3_g_toint_nr      ,
+         dout(10)        => ex3_g_toint_ok     ); 
+
+
+   f_alg_ex3_sticky        <= ex3_sticky_math  or ex3_g_math  ;
+   f_alg_ex3_int_fi        <= ex3_sticky_toint or ex3_g_toint ;
+
+   ex3_int_fr_nr1_b        <= not( ex3_g_toint_nr and ex3_sticky_toint_nr );
+   ex3_int_fr_nr2_b        <= not( ex3_g_toint_nr and ex3_lsb_toint_nr    );
+   ex3_int_fr_ok_b         <= not( ex3_g_toint_ok or  ex3_sticky_toint_ok );
+   ex3_int_fr              <= not( ex3_int_fr_nr1_b and ex3_int_fr_nr2_b and ex3_int_fr_ok_b );
+   f_alg_ex3_int_fr        <= ex3_int_fr     ;
+
+   ex3_sel_p1_0_b          <= not( not ex3_int_fr and ex3_frmneg_o_toneg);
+   ex3_sel_p1_1_b          <= not(     ex3_int_fr and ex3_frmneg_o_topos);
+   f_alg_ex3_frc_sel_p1    <= not(ex3_sel_p1_0_b and ex3_sel_p1_1_b ) ;
+
+
+
+  ex1_ctl_si      (0 to 4)   <=   ex1_ctl_so      (1 to 4)   & f_alg_si  ;
+  ex2_shd_si      (0 to 67)  <=   ex2_shd_so  (1 to 67)      & ex1_ctl_so      (0) ;
+  ex2_shc_si      (0 to 24)  <=   ex2_shc_so  (1 to 24)      & ex2_shd_so      (0) ;
+  ex2_ctl_si      (0 to 14)  <=   ex2_ctl_so      (1 to 14)  & ex2_shc_so      (0) ;
+  ex3_ctl_si      (0 to 10)  <=   ex3_ctl_so      (1 to 10)  & ex2_ctl_so      (0) ;
+  act_si          (0 to 4)   <=   act_so          (1 to 4)   & ex3_ctl_so      (0) ;
+  f_alg_so                   <=     act_so          (0) ;
+
+
+end; 
+
+
+
+   
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_add.vhdl

@@ -0,0 +1,670 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+ library clib ;
+
+entity fuq_alg_add is
+generic(       expand_type               : integer := 2  ); 
+port(
+
+    vdd              : inout power_logic;                  
+    gnd              : inout power_logic;                  
+
+       f_byp_alg_ex1_b_expo      :in  std_ulogic_vector(1 to 13);
+       f_byp_alg_ex1_a_expo      :in  std_ulogic_vector(1 to 13);
+       f_byp_alg_ex1_c_expo      :in  std_ulogic_vector(1 to 13);
+
+       ex1_sel_special_b         :in  std_ulogic ;
+
+       ex1_bsha_6_o              :out std_ulogic ;
+       ex1_bsha_7_o              :out std_ulogic ;
+       ex1_bsha_8_o              :out std_ulogic ;
+       ex1_bsha_9_o              :out std_ulogic ;
+
+       ex1_bsha_neg_o            :out std_ulogic ;
+       ex1_sh_ovf                :out std_ulogic ;
+       ex1_sh_unf_x              :out std_ulogic ;
+
+
+       ex1_lvl1_shdcd000_b       :out std_ulogic ;
+       ex1_lvl1_shdcd001_b       :out std_ulogic ;
+       ex1_lvl1_shdcd002_b       :out std_ulogic ;
+       ex1_lvl1_shdcd003_b       :out std_ulogic ;
+
+       ex1_lvl2_shdcd000         :out std_ulogic ;
+       ex1_lvl2_shdcd004         :out std_ulogic ;
+       ex1_lvl2_shdcd008         :out std_ulogic ;
+       ex1_lvl2_shdcd012         :out std_ulogic ;
+
+       ex1_lvl3_shdcd000         :out std_ulogic ;
+       ex1_lvl3_shdcd016         :out std_ulogic ;
+       ex1_lvl3_shdcd032         :out std_ulogic ;
+       ex1_lvl3_shdcd048         :out std_ulogic ;
+       ex1_lvl3_shdcd064         :out std_ulogic ;
+       ex1_lvl3_shdcd080         :out std_ulogic ;
+       ex1_lvl3_shdcd096         :out std_ulogic ;
+       ex1_lvl3_shdcd112         :out std_ulogic ;
+       ex1_lvl3_shdcd128         :out std_ulogic ;
+       ex1_lvl3_shdcd144         :out std_ulogic ;
+       ex1_lvl3_shdcd160         :out std_ulogic ;
+       ex1_lvl3_shdcd176         :out std_ulogic ;
+       ex1_lvl3_shdcd192         :out std_ulogic ;
+       ex1_lvl3_shdcd208         :out std_ulogic ;
+       ex1_lvl3_shdcd224         :out std_ulogic ;
+       ex1_lvl3_shdcd240         :out std_ulogic  
+); 
+
+
+
+end fuq_alg_add; 
+
+architecture fuq_alg_add of fuq_alg_add is
+
+  constant tiup :std_ulogic := '1';
+  constant tidn :std_ulogic := '0';
+  signal ex1_bsha_sim_c :std_ulogic_vector(2 to 14); 
+  signal ex1_bsha_sim_p :std_ulogic_vector(1 to 13);
+  signal ex1_bsha_sim_g :std_ulogic_vector(2 to 13);
+  signal ex1_bsha_sim   :std_ulogic_vector(1 to 13);
+
+  signal ex1_b_expo_b :std_ulogic_vector(1 to 13);
+  signal ex1_a_expo_b :std_ulogic_vector(2 to 13);
+  signal ex1_c_expo_b :std_ulogic_vector(2 to 13);
+  signal ex1_bsha_neg :std_ulogic;
+  signal ex1_sh_ovf_b  :std_ulogic;
+  signal ex1_alg_sx             :std_ulogic_vector(1 to 13)   ;
+  signal ex1_alg_cx             :std_ulogic_vector(0 to 12)   ;
+  signal ex1_alg_add_p          :std_ulogic_vector(1 to 12)   ;
+  signal ex1_alg_add_g_b        :std_ulogic_vector(2 to 12)   ;
+  signal ex1_alg_add_t_b        :std_ulogic_vector(2 to 11)   ;
+
+  signal ex1_bsha_6_b   :std_ulogic;
+  signal ex1_bsha_7_b   :std_ulogic;
+  signal ex1_bsha_8_b   :std_ulogic;
+  signal ex1_bsha_9_b   :std_ulogic;
+  signal ex1_67_dcd00_b :std_ulogic;
+  signal ex1_67_dcd01_b :std_ulogic;
+  signal ex1_67_dcd10_b :std_ulogic;
+  signal ex1_67_dcd11_b :std_ulogic;
+  signal ex1_89_dcd00_b :std_ulogic;
+  signal ex1_89_dcd01_b :std_ulogic;
+  signal ex1_89_dcd10_b :std_ulogic;
+  signal ex1_89_dcd11_b :std_ulogic;
+
+  signal ex1_lv2_0pg0_b      :std_ulogic;
+  signal ex1_lv2_0pg1_b      :std_ulogic;
+  signal ex1_lv2_0pk0_b      :std_ulogic;
+  signal ex1_lv2_0pk1_b      :std_ulogic;
+  signal ex1_lv2_0pp0_b      :std_ulogic;
+  signal ex1_lv2_0pp1_b      :std_ulogic;
+  signal ex1_lv2_1pg0_b      :std_ulogic;
+  signal ex1_lv2_1pg1_b      :std_ulogic;
+  signal ex1_lv2_1pk0_b      :std_ulogic;
+  signal ex1_lv2_1pk1_b      :std_ulogic;
+  signal ex1_lv2_1pp0_b      :std_ulogic;
+  signal ex1_lv2_1pp1_b      :std_ulogic;
+  signal ex1_lv2_shdcd000    :std_ulogic;
+  signal ex1_lv2_shdcd004    :std_ulogic;
+  signal ex1_lv2_shdcd008    :std_ulogic;
+  signal ex1_lv2_shdcd012    :std_ulogic;
+  signal ex1_lvl2_shdcd000_b :std_ulogic;
+  signal ex1_lvl2_shdcd004_b :std_ulogic;
+  signal ex1_lvl2_shdcd008_b :std_ulogic;
+  signal ex1_lvl2_shdcd012_b :std_ulogic;
+
+  signal  ex1_alg_add_c_b :std_ulogic_vector(7 to 10);
+  signal  ex1_g02_12         :std_ulogic;
+  signal  ex1_g02_12_b       :std_ulogic;
+  signal  ex1_bsha_13_b      :std_ulogic;
+  signal  ex1_bsha_13        :std_ulogic;
+  signal  ex1_bsha_12_b      :std_ulogic;
+  signal  ex1_bsha_12        :std_ulogic;
+  signal  ex1_lv2_ci11n_en_b :std_ulogic;
+  signal  ex1_lv2_ci11p_en_b :std_ulogic;
+  signal  ex1_lv2_ci11n_en   :std_ulogic;
+  signal  ex1_lv2_ci11p_en   :std_ulogic;
+  signal  ex1_g02_10         :std_ulogic;
+  signal  ex1_t02_10         :std_ulogic;
+  signal  ex1_g04_10_b       :std_ulogic;
+  signal  ex1_lv2_g11_x      :std_ulogic;
+  signal  ex1_lv2_g11_b      :std_ulogic;
+  signal  ex1_lv2_g11        :std_ulogic;
+  signal  ex1_lv2_k11_b      :std_ulogic;
+  signal  ex1_lv2_k11        :std_ulogic;
+  signal  ex1_lv2_p11_b      :std_ulogic;
+  signal  ex1_lv2_p11        :std_ulogic;
+  signal  ex1_lv2_p10_b      :std_ulogic;
+  signal  ex1_lv2_p10        :std_ulogic;
+  signal  ex1_g04_10  :std_ulogic;
+  signal  ex1_g02_6   :std_ulogic;
+  signal  ex1_g02_7   :std_ulogic;
+  signal  ex1_g02_8   :std_ulogic;
+  signal  ex1_g02_9   :std_ulogic;
+  signal  ex1_t02_6   :std_ulogic;
+  signal  ex1_t02_7   :std_ulogic;
+  signal  ex1_t02_8   :std_ulogic;
+  signal  ex1_t02_9   :std_ulogic;
+  signal  ex1_g04_6_b :std_ulogic;
+  signal  ex1_g04_7_b :std_ulogic;
+  signal  ex1_g04_8_b :std_ulogic;
+  signal  ex1_g04_9_b :std_ulogic;
+  signal  ex1_t04_6_b :std_ulogic;
+  signal  ex1_t04_7_b :std_ulogic;
+  signal  ex1_t04_8_b :std_ulogic;
+  signal  ex1_t04_9_b :std_ulogic;
+  signal  ex1_g08_6   :std_ulogic;
+  signal  ex1_g04_7   :std_ulogic;
+  signal  ex1_g04_8   :std_ulogic;
+  signal  ex1_g04_9   :std_ulogic;
+  signal  ex1_t04_7   :std_ulogic;
+  signal  ex1_t04_8   :std_ulogic;
+  signal  ex1_t04_9   :std_ulogic;
+  signal  ex1_bsha_6    :std_ulogic;
+  signal  ex1_bsha_7    :std_ulogic;
+  signal  ex1_bsha_8    :std_ulogic;
+  signal  ex1_bsha_9    :std_ulogic;
+  signal  ex1_g02_4    :std_ulogic;
+  signal  ex1_g02_2    :std_ulogic;
+  signal  ex1_t02_4    :std_ulogic;
+  signal  ex1_t02_2    :std_ulogic;
+  signal  ex1_g04_2_b  :std_ulogic;
+  signal  ex1_t04_2_b  :std_ulogic;
+  signal  ex1_ones_2t3_b :std_ulogic;
+  signal  ex1_ones_4t5_b :std_ulogic;
+  signal  ex1_ones_2t5   :std_ulogic;
+  signal  ex1_ones_2t5_b :std_ulogic;
+  signal  ex1_zero_2_b   :std_ulogic;
+  signal  ex1_zero_3_b   :std_ulogic;
+  signal  ex1_zero_4_b   :std_ulogic;
+  signal  ex1_zero_5     :std_ulogic;
+  signal  ex1_zero_5_b   :std_ulogic;
+  signal  ex1_zero_2t3   :std_ulogic;
+  signal  ex1_zero_4t5   :std_ulogic;
+  signal  ex1_zero_2t5_b :std_ulogic;
+  signal  pos_if_pco6   :std_ulogic;
+  signal  pos_if_nco6   :std_ulogic;
+  signal  pos_if_pco6_b :std_ulogic;
+  signal  pos_if_nco6_b :std_ulogic;
+  signal  unf_if_nco6_b :std_ulogic;
+  signal  unf_if_pco6_b :std_ulogic;
+  signal  ex1_g08_6_b   :std_ulogic;
+  signal  ex1_bsha_pos  :std_ulogic;
+  signal  ex1_bsha_6_i  :std_ulogic;
+  signal  ex1_bsha_7_i  :std_ulogic;
+  signal  ex1_bsha_8_i  :std_ulogic;
+  signal  ex1_bsha_9_i  :std_ulogic;
+  signal ex1_ack_s :std_ulogic_vector(1 to 13);
+  signal ex1_ack_c :std_ulogic_vector(1 to 12);
+
+
+
+
+
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+begin
+
+
+
+    ex1_bsha_sim_p(1 to 12) <= ex1_alg_sx(1 to 12) xor ex1_alg_cx(1 to 12);
+    ex1_bsha_sim_p(     13) <= ex1_alg_sx(     13) ;
+    ex1_bsha_sim_g(2 to 12) <= ex1_alg_sx(2 to 12) and ex1_alg_cx(2 to 12);
+    ex1_bsha_sim_g(13)      <= tidn;
+    ex1_bsha_sim  (1 to 13) <= ex1_bsha_sim_p(1 to 13) xor ex1_bsha_sim_c(2 to 14);
+
+    ex1_bsha_sim_c(14) <= tidn;
+    ex1_bsha_sim_c(13) <= ex1_bsha_sim_g(13) or (ex1_bsha_sim_p(13) and ex1_bsha_sim_c(14) );
+    ex1_bsha_sim_c(12) <= ex1_bsha_sim_g(12) or (ex1_bsha_sim_p(12) and ex1_bsha_sim_c(13) );
+    ex1_bsha_sim_c(11) <= ex1_bsha_sim_g(11) or (ex1_bsha_sim_p(11) and ex1_bsha_sim_c(12) );
+    ex1_bsha_sim_c(10) <= ex1_bsha_sim_g(10) or (ex1_bsha_sim_p(10) and ex1_bsha_sim_c(11) );
+    ex1_bsha_sim_c( 9) <= ex1_bsha_sim_g( 9) or (ex1_bsha_sim_p( 9) and ex1_bsha_sim_c(10) );
+    ex1_bsha_sim_c( 8) <= ex1_bsha_sim_g( 8) or (ex1_bsha_sim_p( 8) and ex1_bsha_sim_c( 9) );
+    ex1_bsha_sim_c( 7) <= ex1_bsha_sim_g( 7) or (ex1_bsha_sim_p( 7) and ex1_bsha_sim_c( 8) );
+    ex1_bsha_sim_c( 6) <= ex1_bsha_sim_g( 6) or (ex1_bsha_sim_p( 6) and ex1_bsha_sim_c( 7) );
+    ex1_bsha_sim_c( 5) <= ex1_bsha_sim_g( 5) or (ex1_bsha_sim_p( 5) and ex1_bsha_sim_c( 6) );
+    ex1_bsha_sim_c( 4) <= ex1_bsha_sim_g( 4) or (ex1_bsha_sim_p( 4) and ex1_bsha_sim_c( 5) );
+    ex1_bsha_sim_c( 3) <= ex1_bsha_sim_g( 3) or (ex1_bsha_sim_p( 3) and ex1_bsha_sim_c( 4) );
+    ex1_bsha_sim_c( 2) <= ex1_bsha_sim_g( 2) or (ex1_bsha_sim_p( 2) and ex1_bsha_sim_c( 3) );
+
+
+
+
+ a32_inv: ex1_a_expo_b(2 to 13) <= not f_byp_alg_ex1_a_expo(2 to 13);
+ c32_inv: ex1_c_expo_b(2 to 13) <= not f_byp_alg_ex1_c_expo(2 to 13);
+ b32_inv: ex1_b_expo_b(1 to 13) <= not f_byp_alg_ex1_b_expo(1 to 13); 
+
+sx01:  ex1_ack_s( 1) <= not( f_byp_alg_ex1_a_expo( 1) xor  f_byp_alg_ex1_c_expo( 1) ); 
+sx02:  ex1_ack_s( 2) <= not( f_byp_alg_ex1_a_expo( 2) xor  f_byp_alg_ex1_c_expo( 2) ); 
+sx03:  ex1_ack_s( 3) <= not( f_byp_alg_ex1_a_expo( 3) xor  f_byp_alg_ex1_c_expo( 3) ); 
+sx04:  ex1_ack_s( 4) <=    ( f_byp_alg_ex1_a_expo( 4) xor  f_byp_alg_ex1_c_expo( 4) ); 
+sx05:  ex1_ack_s( 5) <=    ( f_byp_alg_ex1_a_expo( 5) xor  f_byp_alg_ex1_c_expo( 5) ); 
+sx06:  ex1_ack_s( 6) <=    ( f_byp_alg_ex1_a_expo( 6) xor  f_byp_alg_ex1_c_expo( 6) ); 
+sx07:  ex1_ack_s( 7) <=    ( f_byp_alg_ex1_a_expo( 7) xor  f_byp_alg_ex1_c_expo( 7) ); 
+sx08:  ex1_ack_s( 8) <= not( f_byp_alg_ex1_a_expo( 8) xor  f_byp_alg_ex1_c_expo( 8) ); 
+sx09:  ex1_ack_s( 9) <= not( f_byp_alg_ex1_a_expo( 9) xor  f_byp_alg_ex1_c_expo( 9) ); 
+sx10:  ex1_ack_s(10) <= not( f_byp_alg_ex1_a_expo(10) xor  f_byp_alg_ex1_c_expo(10) ); 
+sx11:  ex1_ack_s(11) <=    ( f_byp_alg_ex1_a_expo(11) xor  f_byp_alg_ex1_c_expo(11) ); 
+sx12:  ex1_ack_s(12) <= not( f_byp_alg_ex1_a_expo(12) xor  f_byp_alg_ex1_c_expo(12) ); 
+sx13:  ex1_ack_s(13) <=    ( f_byp_alg_ex1_a_expo(13) xor  f_byp_alg_ex1_c_expo(13) ); 
+
+
+
+ cx01: ex1_ack_c( 1) <= not( ex1_a_expo_b( 2) and  ex1_c_expo_b( 2) ); 
+ cx02: ex1_ack_c( 2) <= not( ex1_a_expo_b( 3) and  ex1_c_expo_b( 3) ); 
+ cx03: ex1_ack_c( 3) <= not( ex1_a_expo_b( 4) or   ex1_c_expo_b( 4) ); 
+ cx04: ex1_ack_c( 4) <= not( ex1_a_expo_b( 5) or   ex1_c_expo_b( 5) ); 
+ cx05: ex1_ack_c( 5) <= not( ex1_a_expo_b( 6) or   ex1_c_expo_b( 6) ); 
+ cx06: ex1_ack_c( 6) <= not( ex1_a_expo_b( 7) or   ex1_c_expo_b( 7) ); 
+ cx07: ex1_ack_c( 7) <= not( ex1_a_expo_b( 8) and  ex1_c_expo_b( 8) ); 
+ cx08: ex1_ack_c( 8) <= not( ex1_a_expo_b( 9) and  ex1_c_expo_b( 9) ); 
+ cx09: ex1_ack_c( 9) <= not( ex1_a_expo_b(10) and  ex1_c_expo_b(10) ); 
+ cx10: ex1_ack_c(10) <= not( ex1_a_expo_b(11) or   ex1_c_expo_b(11) ); 
+ cx11: ex1_ack_c(11) <= not( ex1_a_expo_b(12) and  ex1_c_expo_b(12) ); 
+ cx12: ex1_ack_c(12) <= not( ex1_a_expo_b(13) or   ex1_c_expo_b(13) ); 
+
+
+ 
+  
+
+
+sha32_01: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(1)   ,
+        b                =>            ex1_ack_s(1)   ,
+        c                =>            ex1_ack_c(1)   ,
+        sum              =>           ex1_alg_sx(1)   ,
+        car              =>           ex1_alg_cx(0)  );
+sha32_02: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(2)   ,
+        b                =>            ex1_ack_s(2)   ,
+        c                =>            ex1_ack_c(2)   ,
+        sum              =>           ex1_alg_sx(2)   ,
+        car              =>           ex1_alg_cx(1)  );
+sha32_03: entity clib.c_prism_csa32  port map(
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(3)   ,
+        b                =>            ex1_ack_s(3)   ,
+        c                =>            ex1_ack_c(3)   ,
+        sum              =>           ex1_alg_sx(3)   ,
+        car              =>           ex1_alg_cx(2)  );
+sha32_04: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(4)   ,
+        b                =>            ex1_ack_s(4)   ,
+        c                =>            ex1_ack_c(4)   ,
+        sum              =>           ex1_alg_sx(4)   ,
+        car              =>           ex1_alg_cx(3)  );
+sha32_05: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(5)   ,
+        b                =>            ex1_ack_s(5)   ,
+        c                =>            ex1_ack_c(5)   ,
+        sum              =>           ex1_alg_sx(5)   ,
+        car              =>           ex1_alg_cx(4)  );
+sha32_06: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(6)   ,
+        b                =>            ex1_ack_s(6)   ,
+        c                =>            ex1_ack_c(6)   ,
+        sum              =>           ex1_alg_sx(6)   ,
+        car              =>           ex1_alg_cx(5)  );
+sha32_07: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(7)   ,
+        b                =>            ex1_ack_s(7)   ,
+        c                =>            ex1_ack_c(7)   ,
+        sum              =>           ex1_alg_sx(7)   ,
+        car              =>           ex1_alg_cx(6)  );
+sha32_08: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(8)   ,
+        b                =>            ex1_ack_s(8)   ,
+        c                =>            ex1_ack_c(8)   ,
+        sum              =>           ex1_alg_sx(8)   ,
+        car              =>           ex1_alg_cx(7)  );
+sha32_09: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(9)   ,
+        b                =>            ex1_ack_s(9)   ,
+        c                =>            ex1_ack_c(9)   ,
+        sum              =>           ex1_alg_sx(9)   ,
+        car              =>           ex1_alg_cx(8)  );
+sha32_10: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(10)  ,
+        b                =>            ex1_ack_s(10)  ,
+        c                =>            ex1_ack_c(10)  ,
+        sum              =>           ex1_alg_sx(10)  ,
+        car              =>           ex1_alg_cx(9)  );
+sha32_11: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(11)  ,
+        b                =>            ex1_ack_s(11)  ,
+        c                =>            ex1_ack_c(11)  ,
+        sum              =>           ex1_alg_sx(11)  ,
+        car              =>           ex1_alg_cx(10) );
+sha32_12: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(12)  ,
+        b                =>            ex1_ack_s(12)  ,
+        c                =>            ex1_ack_c(12)  ,
+        sum              =>           ex1_alg_sx(12)  ,
+        car              =>           ex1_alg_cx(11) );
+sha32_13: entity clib.c_prism_csa32  port map( 
+        vd               => vdd,
+        gd               => gnd,
+        a                =>         ex1_b_expo_b(13)  ,
+        b                =>            ex1_ack_s(13)  ,
+        c                =>            tidn           ,
+        sum              =>           ex1_alg_sx(13)  ,
+        car              =>           ex1_alg_cx(12) );
+
+
+
+p1_01: ex1_alg_add_p( 1)   <= ex1_alg_sx( 1) xor ex1_alg_cx( 1);
+p1_02: ex1_alg_add_p( 2)   <= ex1_alg_sx( 2) xor ex1_alg_cx( 2);
+p1_03: ex1_alg_add_p( 3)   <= ex1_alg_sx( 3) xor ex1_alg_cx( 3);
+p1_04: ex1_alg_add_p( 4)   <= ex1_alg_sx( 4) xor ex1_alg_cx( 4);
+p1_05: ex1_alg_add_p( 5)   <= ex1_alg_sx( 5) xor ex1_alg_cx( 5);
+p1_06: ex1_alg_add_p( 6)   <= ex1_alg_sx( 6) xor ex1_alg_cx( 6);
+p1_07: ex1_alg_add_p( 7)   <= ex1_alg_sx( 7) xor ex1_alg_cx( 7);
+p1_08: ex1_alg_add_p( 8)   <= ex1_alg_sx( 8) xor ex1_alg_cx( 8);
+p1_09: ex1_alg_add_p( 9)   <= ex1_alg_sx( 9) xor ex1_alg_cx( 9);
+p1_10: ex1_alg_add_p(10)   <= ex1_alg_sx(10) xor ex1_alg_cx(10);
+p1_11: ex1_alg_add_p(11)   <= ex1_alg_sx(11) xor ex1_alg_cx(11);
+p1_12: ex1_alg_add_p(12)   <= ex1_alg_sx(12) xor ex1_alg_cx(12);
+
+
+g1_02:  ex1_alg_add_g_b( 2) <= not( ex1_alg_sx( 2) and ex1_alg_cx( 2) );
+g1_03:  ex1_alg_add_g_b( 3) <= not( ex1_alg_sx( 3) and ex1_alg_cx( 3) );
+g1_04:  ex1_alg_add_g_b( 4) <= not( ex1_alg_sx( 4) and ex1_alg_cx( 4) );
+g1_05:  ex1_alg_add_g_b( 5) <= not( ex1_alg_sx( 5) and ex1_alg_cx( 5) );
+g1_06:  ex1_alg_add_g_b( 6) <= not( ex1_alg_sx( 6) and ex1_alg_cx( 6) );
+g1_07:  ex1_alg_add_g_b( 7) <= not( ex1_alg_sx( 7) and ex1_alg_cx( 7) );
+g1_08:  ex1_alg_add_g_b( 8) <= not( ex1_alg_sx( 8) and ex1_alg_cx( 8) );
+g1_09:  ex1_alg_add_g_b( 9) <= not( ex1_alg_sx( 9) and ex1_alg_cx( 9) );
+g1_10:  ex1_alg_add_g_b(10) <= not( ex1_alg_sx(10) and ex1_alg_cx(10) );
+g1_11:  ex1_alg_add_g_b(11) <= not( ex1_alg_sx(11) and ex1_alg_cx(11) );
+g1_12:  ex1_alg_add_g_b(12) <= not( ex1_alg_sx(12) and ex1_alg_cx(12) );
+
+t1_02:  ex1_alg_add_t_b( 2) <= not( ex1_alg_sx( 2) or  ex1_alg_cx( 2) );
+t1_03:  ex1_alg_add_t_b( 3) <= not( ex1_alg_sx( 3) or  ex1_alg_cx( 3) );
+t1_04:  ex1_alg_add_t_b( 4) <= not( ex1_alg_sx( 4) or  ex1_alg_cx( 4) );
+t1_05:  ex1_alg_add_t_b( 5) <= not( ex1_alg_sx( 5) or  ex1_alg_cx( 5) );
+t1_06:  ex1_alg_add_t_b( 6) <= not( ex1_alg_sx( 6) or  ex1_alg_cx( 6) );
+t1_07:  ex1_alg_add_t_b( 7) <= not( ex1_alg_sx( 7) or  ex1_alg_cx( 7) );
+t1_08:  ex1_alg_add_t_b( 8) <= not( ex1_alg_sx( 8) or  ex1_alg_cx( 8) );
+t1_09:  ex1_alg_add_t_b( 9) <= not( ex1_alg_sx( 9) or  ex1_alg_cx( 9) );
+t1_10:  ex1_alg_add_t_b(10) <= not( ex1_alg_sx(10) or  ex1_alg_cx(10) );
+t1_11:  ex1_alg_add_t_b(11) <= not( ex1_alg_sx(11) or  ex1_alg_cx(11) );
+
+
+g2_12:   ex1_g02_12         <= not ex1_alg_add_g_b(12);  
+g2_12b:  ex1_g02_12_b       <= not ex1_g02_12 ;          
+
+res_13b: ex1_bsha_13_b      <= not ex1_alg_sx(13);       
+res_13:  ex1_bsha_13        <= not ex1_bsha_13_b ;       
+res_12b: ex1_bsha_12_b      <= not ex1_alg_add_p(12);
+res_12:  ex1_bsha_12        <= not ex1_bsha_12_b ;       
+
+ci11nb:  ex1_lv2_ci11n_en_b <= not( ex1_sel_special_b and ex1_g02_12_b  );
+ci11pb:  ex1_lv2_ci11p_en_b <= not( ex1_sel_special_b and ex1_g02_12    );
+ci11n:   ex1_lv2_ci11n_en   <= not( ex1_lv2_ci11n_en_b  ); 
+ci11p:   ex1_lv2_ci11p_en   <= not( ex1_lv2_ci11p_en_b  ); 
+
+
+g2_10: ex1_g02_10         <= not( ex1_alg_add_g_b(10) and (ex1_alg_add_t_b(10) or  ex1_alg_add_g_b(11)) );
+t2_10: ex1_t02_10         <= not(                          ex1_alg_add_t_b(10) or  ex1_alg_add_t_b(11)  );
+g4_10: ex1_g04_10_b       <= not( ex1_g02_10          or  (ex1_t02_10          and ex1_g02_12         ) );
+
+g11x:  ex1_lv2_g11_x      <= not( ex1_alg_add_g_b(11) ); 
+g11b:  ex1_lv2_g11_b      <= not( ex1_lv2_g11_x       ); 
+g11:   ex1_lv2_g11        <= not( ex1_lv2_g11_b       ); 
+k11x:  ex1_lv2_k11_b      <= not( ex1_alg_add_t_b(11) );
+k11:   ex1_lv2_k11        <= not( ex1_lv2_k11_b       ); 
+p11b:  ex1_lv2_p11_b      <= not( ex1_alg_add_p(11)   ); 
+p11:   ex1_lv2_p11        <= not( ex1_lv2_p11_b       ); 
+p10b:  ex1_lv2_p10_b      <= not( ex1_alg_add_p(10)   ); 
+p10:   ex1_lv2_p10        <= not( ex1_lv2_p10_b       ); 
+      
+
+g4x_10: ex1_g04_10  <= not ex1_g04_10_b ; 
+
+g2_06: ex1_g02_6   <= not( ex1_alg_add_g_b(6) and (ex1_alg_add_t_b(6) or  ex1_alg_add_g_b(7)) );
+g2_07: ex1_g02_7   <= not( ex1_alg_add_g_b(7) and (ex1_alg_add_t_b(7) or  ex1_alg_add_g_b(8)) );
+g2_08: ex1_g02_8   <= not( ex1_alg_add_g_b(8) and (ex1_alg_add_t_b(8) or  ex1_alg_add_g_b(9)) );
+g2_09: ex1_g02_9   <= not( ex1_alg_add_g_b(9)                                                 );
+t2_06: ex1_t02_6   <= not(                         ex1_alg_add_t_b(6) or  ex1_alg_add_t_b(7)  );
+t2_07: ex1_t02_7   <= not(                         ex1_alg_add_t_b(7) or  ex1_alg_add_t_b(8)  );
+t2_08: ex1_t02_8   <= not(                         ex1_alg_add_t_b(8) or  ex1_alg_add_t_b(9)  );
+t2_09: ex1_t02_9   <= not(                         ex1_alg_add_t_b(9)                         );
+
+g4_06b: ex1_g04_6_b <= not( ex1_g02_6          or  (ex1_t02_6          and ex1_g02_8         ) );
+g4_07b: ex1_g04_7_b <= not( ex1_g02_7          or  (ex1_t02_7          and ex1_g02_9         ) );
+g4_08b: ex1_g04_8_b <= not( ex1_g02_8                                                          );
+g4_09b: ex1_g04_9_b <= not( ex1_g02_9                                                          );
+t4_06b: ex1_t04_6_b <= not(                         ex1_t02_6          and ex1_t02_8           );
+t4_07b: ex1_t04_7_b <= not(                         ex1_t02_7          and ex1_t02_9           );
+t4_08b: ex1_t04_8_b <= not(                                                ex1_t02_8           );
+t4_09b: ex1_t04_9_b <= not(                                                ex1_t02_9           );
+
+g8_06:  ex1_g08_6   <= not( ex1_g04_6_b        and (ex1_t04_6_b        or  ex1_g04_10_b      ) );
+g4_07:  ex1_g04_7   <= not( ex1_g04_7_b );
+g4_08:  ex1_g04_8   <= not( ex1_g04_8_b );
+g4_09:  ex1_g04_9   <= not( ex1_g04_9_b );
+t4_07:  ex1_t04_7   <= not( ex1_t04_7_b );
+t4_08:  ex1_t04_8   <= not( ex1_t04_8_b );
+t4_09:  ex1_t04_9   <= not( ex1_t04_9_b );
+     
+c07:   ex1_alg_add_c_b(7)  <= not( ex1_g04_7 or (ex1_t04_7 and ex1_g04_10) );
+c08:   ex1_alg_add_c_b(8)  <= not( ex1_g04_8 or (ex1_t04_8 and ex1_g04_10) );
+c09:   ex1_alg_add_c_b(9)  <= not( ex1_g04_9 or (ex1_t04_9 and ex1_g04_10) );
+c10:   ex1_alg_add_c_b(10) <= not(                             ex1_g04_10 ); 
+
+res_6: ex1_bsha_6  <= not( ex1_alg_add_p(6) xor ex1_alg_add_c_b(7)  );
+res_7: ex1_bsha_7  <= not( ex1_alg_add_p(7) xor ex1_alg_add_c_b(8)  );
+res_8: ex1_bsha_8  <= not( ex1_alg_add_p(8) xor ex1_alg_add_c_b(9)  );
+res_9: ex1_bsha_9  <= not( ex1_alg_add_p(9) xor ex1_alg_add_c_b(10) );
+
+
+res_6i:  ex1_bsha_6_i  <= not ex1_bsha_6 ;
+res_7i:  ex1_bsha_7_i  <= not ex1_bsha_7 ;
+res_8i:  ex1_bsha_8_i  <= not ex1_bsha_8 ;
+res_9i:  ex1_bsha_9_i  <= not ex1_bsha_9 ;
+
+res_6o:  ex1_bsha_6_o  <= not ex1_bsha_6_i ;
+res_7o:  ex1_bsha_7_o  <= not ex1_bsha_7_i ;
+res_8o:  ex1_bsha_8_o  <= not ex1_bsha_8_i ;
+res_9o:  ex1_bsha_9_o  <= not ex1_bsha_9_i ;
+    
+
+g2_02: ex1_g02_2    <= not( ex1_alg_add_g_b(2) and (ex1_alg_add_t_b(2) or  ex1_alg_add_g_b(3)) ); 
+g2_04: ex1_g02_4    <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or  ex1_alg_add_g_b(5)) ); 
+
+t2_02: ex1_t02_2    <= not(                        (ex1_alg_add_t_b(2) or  ex1_alg_add_t_b(3)) ); 
+t2_04: ex1_t02_4    <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or  ex1_alg_add_t_b(5)) ); 
+
+g4_02: ex1_g04_2_b  <= not( ex1_g02_2          or  (ex1_t02_2          and ex1_g02_4         ) ); 
+t4_02: ex1_t04_2_b  <= not( ex1_g02_2          or  (ex1_t02_2          and ex1_t02_4         ) ); 
+
+
+ones23:    ex1_ones_2t3_b <= not( ex1_alg_add_p(2) and ex1_alg_add_p(3) );
+ones45:    ex1_ones_4t5_b <= not( ex1_alg_add_p(4) and ex1_alg_add_p(5) );
+ones25:    ex1_ones_2t5   <= not( ex1_ones_2t3_b   or  ex1_ones_4t5_b   );
+ones25_b:  ex1_ones_2t5_b <= not( ex1_ones_2t5 );
+
+z2b:       ex1_zero_2_b   <= not( ex1_alg_add_p(2) xor ex1_alg_add_t_b(3)  );
+z3b:       ex1_zero_3_b   <= not( ex1_alg_add_p(3) xor ex1_alg_add_t_b(4)  );
+z4b:       ex1_zero_4_b   <= not( ex1_alg_add_p(4) xor ex1_alg_add_t_b(5)  );
+z5:        ex1_zero_5     <= not( ex1_alg_add_p(5)                         );
+z5b:       ex1_zero_5_b   <= not( ex1_zero_5                               );
+z23:       ex1_zero_2t3   <= not( ex1_zero_2_b     or  ex1_zero_3_b        );
+z45:       ex1_zero_4t5   <= not( ex1_zero_4_b     or  ex1_zero_5_b        );
+z25b:      ex1_zero_2t5_b <= not( ex1_zero_2t3     and ex1_zero_4t5        );
+
+
+pco6:   pos_if_pco6   <=     ( ex1_alg_add_p(1) xor ex1_t04_2_b );
+nco6:   pos_if_nco6   <=     ( ex1_alg_add_p(1) xor ex1_g04_2_b );
+pco6b:  pos_if_pco6_b <= not pos_if_pco6 ;
+nco6b:  pos_if_nco6_b <= not pos_if_nco6 ;
+
+unifnc: unf_if_nco6_b <= not( pos_if_nco6 and  ex1_zero_2t5_b );
+unifpc: unf_if_pco6_b <= not( pos_if_pco6 and  ex1_ones_2t5_b );
+
+g8_06b: ex1_g08_6_b     <= not ex1_g08_6 ;
+shap:   ex1_bsha_pos    <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );
+shovb:   ex1_sh_ovf_b   <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );
+shun:   ex1_sh_unf_x    <= not( (unf_if_pco6_b and ex1_g08_6) or (unf_if_nco6_b and ex1_g08_6_b) ); 
+shan:   ex1_bsha_neg    <= not( ex1_bsha_pos );
+shan2:  ex1_bsha_neg_o  <= not( ex1_bsha_pos );
+shov:   ex1_sh_ovf      <= not( ex1_sh_ovf_b );
+
+
+
+d1_0:  ex1_lvl1_shdcd000_b <= not(  ex1_bsha_12_b and  ex1_bsha_13_b );
+d1_1:  ex1_lvl1_shdcd001_b <= not(  ex1_bsha_12_b and  ex1_bsha_13   );
+d1_2:  ex1_lvl1_shdcd002_b <= not(  ex1_bsha_12   and  ex1_bsha_13_b );
+d1_3:  ex1_lvl1_shdcd003_b <= not(  ex1_bsha_12   and  ex1_bsha_13   );
+
+
+d2_0pg0: ex1_lv2_0pg0_b <= not( ex1_lv2_p10_b and  ex1_lv2_g11 and  ex1_lv2_ci11n_en );
+d2_0pg1: ex1_lv2_0pg1_b <= not( ex1_lv2_p10_b and  ex1_lv2_g11 and  ex1_lv2_ci11p_en );
+d2_0pk0: ex1_lv2_0pk0_b <= not( ex1_lv2_p10_b and  ex1_lv2_k11 and  ex1_lv2_ci11n_en );
+d2_0pk1: ex1_lv2_0pk1_b <= not( ex1_lv2_p10_b and  ex1_lv2_k11 and  ex1_lv2_ci11p_en );
+d2_0pp0: ex1_lv2_0pp0_b <= not( ex1_lv2_p10_b and  ex1_lv2_p11 and  ex1_lv2_ci11n_en );
+d2_0pp1: ex1_lv2_0pp1_b <= not( ex1_lv2_p10_b and  ex1_lv2_p11 and  ex1_lv2_ci11p_en );
+d2_1pg0: ex1_lv2_1pg0_b <= not( ex1_lv2_p10   and  ex1_lv2_g11 and  ex1_lv2_ci11n_en );
+d2_1pg1: ex1_lv2_1pg1_b <= not( ex1_lv2_p10   and  ex1_lv2_g11 and  ex1_lv2_ci11p_en );
+d2_1pk0: ex1_lv2_1pk0_b <= not( ex1_lv2_p10   and  ex1_lv2_k11 and  ex1_lv2_ci11n_en );
+d2_1pk1: ex1_lv2_1pk1_b <= not( ex1_lv2_p10   and  ex1_lv2_k11 and  ex1_lv2_ci11p_en );
+d2_1pp0: ex1_lv2_1pp0_b <= not( ex1_lv2_p10   and  ex1_lv2_p11 and  ex1_lv2_ci11n_en );
+d2_1pp1: ex1_lv2_1pp1_b <= not( ex1_lv2_p10   and  ex1_lv2_p11 and  ex1_lv2_ci11p_en );
+      
+d2_0:  ex1_lv2_shdcd000 <= not( ex1_lv2_0pk0_b and ex1_lv2_1pg0_b and ex1_lv2_1pp1_b );
+d2_1:  ex1_lv2_shdcd004 <= not( ex1_lv2_0pp0_b and ex1_lv2_0pk1_b and ex1_lv2_1pg1_b );
+d2_2:  ex1_lv2_shdcd008 <= not( ex1_lv2_0pg0_b and ex1_lv2_1pk0_b and ex1_lv2_0pp1_b );
+d2_3:  ex1_lv2_shdcd012 <= not( ex1_lv2_1pp0_b and ex1_lv2_0pg1_b and ex1_lv2_1pk1_b );
+       
+i2_0:  ex1_lvl2_shdcd000_b <= not ex1_lv2_shdcd000;
+i2_1:  ex1_lvl2_shdcd004_b <= not ex1_lv2_shdcd004;
+i2_2:  ex1_lvl2_shdcd008_b <= not ex1_lv2_shdcd008;
+i2_3:  ex1_lvl2_shdcd012_b <= not ex1_lv2_shdcd012;
+       
+ii2_0: ex1_lvl2_shdcd000 <= not ex1_lvl2_shdcd000_b;
+ii2_1: ex1_lvl2_shdcd004 <= not ex1_lvl2_shdcd004_b;
+ii2_2: ex1_lvl2_shdcd008 <= not ex1_lvl2_shdcd008_b;
+ii2_3: ex1_lvl2_shdcd012 <= not ex1_lvl2_shdcd012_b;
+
+       
+
+
+i3_6:  ex1_bsha_6_b <= not ex1_bsha_6 ;
+i3_7:  ex1_bsha_7_b <= not ex1_bsha_7 ;
+i3_8:  ex1_bsha_8_b <= not ex1_bsha_8 ;
+i3_9:  ex1_bsha_9_b <= not ex1_bsha_9 ;
+
+d67_0: ex1_67_dcd00_b <= not( ex1_bsha_6_b and ex1_bsha_7_b                  );
+d67_1: ex1_67_dcd01_b <= not( ex1_bsha_6_b and ex1_bsha_7                    );
+d67_2: ex1_67_dcd10_b <= not( ex1_bsha_6   and ex1_bsha_7_b                  );
+d67_3: ex1_67_dcd11_b <= not( ex1_bsha_6   and ex1_bsha_7   and ex1_bsha_neg );
+
+d89_0: ex1_89_dcd00_b <= not( ex1_bsha_8_b and ex1_bsha_9_b and ex1_sel_special_b );
+d89_1: ex1_89_dcd01_b <= not( ex1_bsha_8_b and ex1_bsha_9   and ex1_sel_special_b );
+d89_2: ex1_89_dcd10_b <= not( ex1_bsha_8   and ex1_bsha_9_b and ex1_sel_special_b );
+d89_3: ex1_89_dcd11_b <= not( ex1_bsha_8   and ex1_bsha_9   and ex1_sel_special_b );
+
+d3_00: ex1_lvl3_shdcd000 <= not(  ex1_67_dcd00_b or ex1_89_dcd00_b );
+d3_01: ex1_lvl3_shdcd016 <= not(  ex1_67_dcd00_b or ex1_89_dcd01_b );
+d3_02: ex1_lvl3_shdcd032 <= not(  ex1_67_dcd00_b or ex1_89_dcd10_b );
+d3_03: ex1_lvl3_shdcd048 <= not(  ex1_67_dcd00_b or ex1_89_dcd11_b );
+d3_04: ex1_lvl3_shdcd064 <= not(  ex1_67_dcd01_b or ex1_89_dcd00_b );
+d3_05: ex1_lvl3_shdcd080 <= not(  ex1_67_dcd01_b or ex1_89_dcd01_b );
+d3_06: ex1_lvl3_shdcd096 <= not(  ex1_67_dcd01_b or ex1_89_dcd10_b );
+d3_07: ex1_lvl3_shdcd112 <= not(  ex1_67_dcd01_b or ex1_89_dcd11_b );
+d3_08: ex1_lvl3_shdcd128 <= not(  ex1_67_dcd10_b or ex1_89_dcd00_b );
+d3_09: ex1_lvl3_shdcd144 <= not(  ex1_67_dcd10_b or ex1_89_dcd01_b );
+d3_10: ex1_lvl3_shdcd160 <= not(  ex1_67_dcd10_b or ex1_89_dcd10_b );
+d3_11: ex1_lvl3_shdcd176 <= not(  ex1_67_dcd10_b or ex1_89_dcd11_b );
+d3_12: ex1_lvl3_shdcd192 <= not(  ex1_67_dcd11_b or ex1_89_dcd00_b );
+d3_13: ex1_lvl3_shdcd208 <= not(  ex1_67_dcd11_b or ex1_89_dcd01_b );
+d3_14: ex1_lvl3_shdcd224 <= not(  ex1_67_dcd11_b or ex1_89_dcd10_b );
+d3_15: ex1_lvl3_shdcd240 <= not(  ex1_67_dcd11_b or ex1_89_dcd11_b );
+
+
+end; 
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_bypmux.vhdl

@@ -0,0 +1,111 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+ 
+entity fuq_alg_bypmux is
+generic(       expand_type               : integer := 2  ); 
+port(
+      ex2_byp_sel_byp_neg      :in  std_ulogic;
+      ex2_byp_sel_byp_pos      :in  std_ulogic;
+      ex2_byp_sel_neg          :in  std_ulogic;
+      ex2_byp_sel_pos          :in  std_ulogic;
+      ex2_prd_sel_neg_hi       :in  std_ulogic;
+      ex2_prd_sel_neg_lo       :in  std_ulogic;
+      ex2_prd_sel_neg_lohi     :in  std_ulogic;
+      ex2_prd_sel_pos_hi       :in  std_ulogic;
+      ex2_prd_sel_pos_lo       :in  std_ulogic;
+      ex2_prd_sel_pos_lohi     :in  std_ulogic;
+
+      ex2_sh_lvl3              :in  std_ulogic_vector(0 to 162);
+      f_fmt_ex2_pass_frac      :in  std_ulogic_vector(0 to 52);
+
+      f_alg_ex2_res            :out std_ulogic_vector(0 to 162)
+);
+
+
+
+end fuq_alg_bypmux; 
+
+architecture fuq_alg_bypmux of fuq_alg_bypmux is
+
+    constant tiup : std_ulogic := '1';
+    constant tidn : std_ulogic := '0';
+
+    signal m0_b, m1_b            :std_ulogic_vector(0 to 162);
+    signal ex2_sh_lvl3_b         :std_ulogic_vector(0 to 162);
+    signal f_fmt_ex2_pass_frac_b :std_ulogic_vector(0 to 52);
+
+
+
+begin
+
+
+
+
+i0:  ex2_sh_lvl3_b(0 to 162)        <= not( ex2_sh_lvl3(0 to 162)       );
+i1:  f_fmt_ex2_pass_frac_b(0 to 52) <= not( f_fmt_ex2_pass_frac(0 to 52) );
+
+
+m0_000:  m0_b(0 to 52)   <= not( ( (0 to 52=> ex2_byp_sel_pos)         and ex2_sh_lvl3          (0 to 52) ) or
+                                 ( (0 to 52=> ex2_byp_sel_neg)         and ex2_sh_lvl3_b        (0 to 52) ) );
+
+m1_000:  m1_b(0 to 52)   <= not( ( (0 to 52=> ex2_byp_sel_byp_pos)     and f_fmt_ex2_pass_frac  (0 to 52) ) or
+                                 ( (0 to 52=> ex2_byp_sel_byp_neg)     and f_fmt_ex2_pass_frac_b(0 to 52) ) );
+
+m0_053:  m0_b(53 to 98)    <= not( (53 to 98=> ex2_prd_sel_pos_hi)     and ex2_sh_lvl3  (53 to 98) );
+m1_053:  m1_b(53 to 98)    <= not( (53 to 98=> ex2_prd_sel_neg_hi)     and ex2_sh_lvl3_b(53 to 98) );
+
+
+m0_099:  m0_b(99 to 130)   <= not( (99 to 130=> ex2_prd_sel_pos_lohi)  and ex2_sh_lvl3  (99 to 130) );
+m1_099:  m1_b(99 to 130)   <= not( (99 to 130=> ex2_prd_sel_neg_lohi)  and ex2_sh_lvl3_b(99 to 130) );
+
+
+m0_131:  m0_b(131 to 162)   <= not( (131 to 162=> ex2_prd_sel_pos_lo)  and ex2_sh_lvl3  (131 to 162) );
+m1_131:  m1_b(131 to 162)   <= not( (131 to 162=> ex2_prd_sel_neg_lo)  and ex2_sh_lvl3_b(131 to 162) );
+
+
+mx: f_alg_ex2_res(0 to 162) <= not( m0_b(0 to 162) and m1_b(0 to 162 ) );
+
+
+
+end; 
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_or16.vhdl

@@ -0,0 +1,182 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+ 
+entity fuq_alg_or16 is
+generic(       expand_type               : integer := 2  ); 
+port(
+      ex2_sh_lvl2              :in   std_ulogic_vector(0 to 67) ;
+      ex2_sticky_or16          :out  std_ulogic_vector(0 to 4)  
+);
+
+
+
+end fuq_alg_or16; 
+
+architecture fuq_alg_or16 of fuq_alg_or16 is
+
+  constant tiup : std_ulogic := '1';
+  constant tidn : std_ulogic := '0';
+  signal ex2_g1o2_b :std_ulogic_vector(0 to 7);
+  signal ex2_g2o2_b :std_ulogic_vector(0 to 7);
+  signal ex2_g3o2_b :std_ulogic_vector(0 to 7);
+  signal ex2_g4o2_b :std_ulogic_vector(0 to 7);
+  signal ex2_g1o4   :std_ulogic_vector(0 to 3);
+  signal ex2_g2o4   :std_ulogic_vector(0 to 3);
+  signal ex2_g3o4   :std_ulogic_vector(0 to 3);
+  signal ex2_g4o4   :std_ulogic_vector(0 to 3);
+  signal ex2_g0o8_b :std_ulogic_vector(0 to 1);
+  signal ex2_g1o8_b :std_ulogic_vector(0 to 1);
+  signal ex2_g2o8_b :std_ulogic_vector(0 to 1);
+  signal ex2_g3o8_b :std_ulogic_vector(0 to 1);
+  signal ex2_g4o8_b :std_ulogic_vector(0 to 1);
+  signal ex2_o16, ex2_o16_b :std_ulogic_vector(0 to 4);
+
+    
+
+
+
+
+
+
+
+
+
+begin
+
+
+
+g1o2_0:  ex2_g1o2_b(0) <= not( ex2_sh_lvl2( 4) or ex2_sh_lvl2( 5) );
+g1o2_1:  ex2_g1o2_b(1) <= not( ex2_sh_lvl2( 6) or ex2_sh_lvl2( 7) );
+g1o2_2:  ex2_g1o2_b(2) <= not( ex2_sh_lvl2( 8) or ex2_sh_lvl2( 9) );
+g1o2_3:  ex2_g1o2_b(3) <= not( ex2_sh_lvl2(10) or ex2_sh_lvl2(11) );
+g1o2_4:  ex2_g1o2_b(4) <= not( ex2_sh_lvl2(12) or ex2_sh_lvl2(13) );
+g1o2_5:  ex2_g1o2_b(5) <= not( ex2_sh_lvl2(14) or ex2_sh_lvl2(15) );
+g1o2_6:  ex2_g1o2_b(6) <= not( ex2_sh_lvl2(16) or ex2_sh_lvl2(17) );
+g1o2_7:  ex2_g1o2_b(7) <= not( ex2_sh_lvl2(18) or ex2_sh_lvl2(19) );
+
+g2o2_0:  ex2_g2o2_b(0) <= not( ex2_sh_lvl2(20) or ex2_sh_lvl2(21) );
+g2o2_1:  ex2_g2o2_b(1) <= not( ex2_sh_lvl2(22) or ex2_sh_lvl2(23) );
+g2o2_2:  ex2_g2o2_b(2) <= not( ex2_sh_lvl2(24) or ex2_sh_lvl2(25) );
+g2o2_3:  ex2_g2o2_b(3) <= not( ex2_sh_lvl2(26) or ex2_sh_lvl2(27) );
+g2o2_4:  ex2_g2o2_b(4) <= not( ex2_sh_lvl2(28) or ex2_sh_lvl2(29) );
+g2o2_5:  ex2_g2o2_b(5) <= not( ex2_sh_lvl2(30) or ex2_sh_lvl2(31) );
+g2o2_6:  ex2_g2o2_b(6) <= not( ex2_sh_lvl2(32) or ex2_sh_lvl2(33) );
+g2o2_7:  ex2_g2o2_b(7) <= not( ex2_sh_lvl2(34) or ex2_sh_lvl2(35) );
+
+g3o2_0:  ex2_g3o2_b(0) <= not( ex2_sh_lvl2(36) or ex2_sh_lvl2(37) );
+g3o2_1:  ex2_g3o2_b(1) <= not( ex2_sh_lvl2(38) or ex2_sh_lvl2(39) );
+g3o2_2:  ex2_g3o2_b(2) <= not( ex2_sh_lvl2(40) or ex2_sh_lvl2(41) );
+g3o2_3:  ex2_g3o2_b(3) <= not( ex2_sh_lvl2(42) or ex2_sh_lvl2(43) );
+g3o2_4:  ex2_g3o2_b(4) <= not( ex2_sh_lvl2(44) or ex2_sh_lvl2(45) );
+g3o2_5:  ex2_g3o2_b(5) <= not( ex2_sh_lvl2(46) or ex2_sh_lvl2(47) );
+g3o2_6:  ex2_g3o2_b(6) <= not( ex2_sh_lvl2(48) or ex2_sh_lvl2(49) );
+g3o2_7:  ex2_g3o2_b(7) <= not( ex2_sh_lvl2(50) or ex2_sh_lvl2(51) );
+
+g4o2_0:  ex2_g4o2_b(0) <= not( ex2_sh_lvl2(52) or ex2_sh_lvl2(53) );
+g4o2_1:  ex2_g4o2_b(1) <= not( ex2_sh_lvl2(54) or ex2_sh_lvl2(55) );
+g4o2_2:  ex2_g4o2_b(2) <= not( ex2_sh_lvl2(56) or ex2_sh_lvl2(57) );
+g4o2_3:  ex2_g4o2_b(3) <= not( ex2_sh_lvl2(58) or ex2_sh_lvl2(59) );
+g4o2_4:  ex2_g4o2_b(4) <= not( ex2_sh_lvl2(60) or ex2_sh_lvl2(61) );
+g4o2_5:  ex2_g4o2_b(5) <= not( ex2_sh_lvl2(62) or ex2_sh_lvl2(63) );
+g4o2_6:  ex2_g4o2_b(6) <= not( ex2_sh_lvl2(64) or ex2_sh_lvl2(65) );
+g4o2_7:  ex2_g4o2_b(7) <= not( ex2_sh_lvl2(66) or ex2_sh_lvl2(67) );
+
+
+g1o4_0: ex2_g1o4(0) <= not(ex2_g1o2_b(0) and ex2_g1o2_b(1) );
+g1o4_1: ex2_g1o4(1) <= not(ex2_g1o2_b(2) and ex2_g1o2_b(3) );
+g1o4_2: ex2_g1o4(2) <= not(ex2_g1o2_b(4) and ex2_g1o2_b(5) );
+g1o4_3: ex2_g1o4(3) <= not(ex2_g1o2_b(6) and ex2_g1o2_b(7) );
+
+g2o4_0: ex2_g2o4(0) <= not(ex2_g2o2_b(0) and ex2_g2o2_b(1) );
+g2o4_1: ex2_g2o4(1) <= not(ex2_g2o2_b(2) and ex2_g2o2_b(3) );
+g2o4_2: ex2_g2o4(2) <= not(ex2_g2o2_b(4) and ex2_g2o2_b(5) );
+g2o4_3: ex2_g2o4(3) <= not(ex2_g2o2_b(6) and ex2_g2o2_b(7) );
+
+g3o4_0: ex2_g3o4(0) <= not(ex2_g3o2_b(0) and ex2_g3o2_b(1) );
+g3o4_1: ex2_g3o4(1) <= not(ex2_g3o2_b(2) and ex2_g3o2_b(3) );
+g3o4_2: ex2_g3o4(2) <= not(ex2_g3o2_b(4) and ex2_g3o2_b(5) );
+g3o4_3: ex2_g3o4(3) <= not(ex2_g3o2_b(6) and ex2_g3o2_b(7) );
+
+g4o4_0: ex2_g4o4(0) <= not(ex2_g4o2_b(0) and ex2_g4o2_b(1) );
+g4o4_1: ex2_g4o4(1) <= not(ex2_g4o2_b(2) and ex2_g4o2_b(3) );
+g4o4_2: ex2_g4o4(2) <= not(ex2_g4o2_b(4) and ex2_g4o2_b(5) );
+g4o4_3: ex2_g4o4(3) <= not(ex2_g4o2_b(6) and ex2_g4o2_b(7) );
+
+
+g0o8_0:  ex2_g0o8_b(0) <= not( ex2_sh_lvl2( 0) or ex2_sh_lvl2( 1) );
+g0o8_1:  ex2_g0o8_b(1) <= not( ex2_sh_lvl2( 2) or ex2_sh_lvl2( 3) );
+
+g1o8_0: ex2_g1o8_b(0) <= not( ex2_g1o4(0) or ex2_g1o4(1) ); 
+g1o8_1: ex2_g1o8_b(1) <= not( ex2_g1o4(2) or ex2_g1o4(3) ); 
+
+g2o8_0: ex2_g2o8_b(0) <= not( ex2_g2o4(0) or ex2_g2o4(1) ); 
+g2o8_1: ex2_g2o8_b(1) <= not( ex2_g2o4(2) or ex2_g2o4(3) ); 
+
+g3o8_0: ex2_g3o8_b(0) <= not( ex2_g3o4(0) or ex2_g3o4(1) ); 
+g3o8_1: ex2_g3o8_b(1) <= not( ex2_g3o4(2) or ex2_g3o4(3) ); 
+
+g4o8_0: ex2_g4o8_b(0) <= not( ex2_g4o4(0) or ex2_g4o4(1) ); 
+g4o8_1: ex2_g4o8_b(1) <= not( ex2_g4o4(2) or ex2_g4o4(3) ); 
+
+
+g0o16: ex2_o16(0) <= not(ex2_g0o8_b(0) and ex2_g0o8_b(1) );
+g1o16: ex2_o16(1) <= not(ex2_g1o8_b(0) and ex2_g1o8_b(1) );
+g2o16: ex2_o16(2) <= not(ex2_g2o8_b(0) and ex2_g2o8_b(1) );
+g3o16: ex2_o16(3) <= not(ex2_g3o8_b(0) and ex2_g3o8_b(1) );
+g4o16: ex2_o16(4) <= not(ex2_g4o8_b(0) and ex2_g4o8_b(1) );
+
+
+g0o16i: ex2_o16_b(0) <= not( ex2_o16(0) );
+g1o16i: ex2_o16_b(1) <= not( ex2_o16(1) );
+g2o16i: ex2_o16_b(2) <= not( ex2_o16(2) );
+g3o16i: ex2_o16_b(3) <= not( ex2_o16(3) );
+g4o16i: ex2_o16_b(4) <= not( ex2_o16(4) );
+
+
+g0o16ii: ex2_sticky_or16(0) <= not( ex2_o16_b(0) );
+g1o16ii: ex2_sticky_or16(1) <= not( ex2_o16_b(1) );
+g2o16ii: ex2_sticky_or16(2) <= not( ex2_o16_b(2) );
+g3o16ii: ex2_sticky_or16(3) <= not( ex2_o16_b(3) );
+g4o16ii: ex2_sticky_or16(4) <= not( ex2_o16_b(4) );
+
+end; 
+                  
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh16.vhdl

@@ -0,0 +1,976 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+ 
+entity fuq_alg_sh16 is
+generic(       expand_type               : integer := 2  ); 
+port(
+      ex2_lvl3_shdcd000        :in   std_ulogic;
+      ex2_lvl3_shdcd016        :in   std_ulogic;
+      ex2_lvl3_shdcd032        :in   std_ulogic;
+      ex2_lvl3_shdcd048        :in   std_ulogic;
+      ex2_lvl3_shdcd064        :in   std_ulogic;
+      ex2_lvl3_shdcd080        :in   std_ulogic;
+      ex2_lvl3_shdcd096        :in   std_ulogic;
+      ex2_lvl3_shdcd112        :in   std_ulogic;
+      ex2_lvl3_shdcd128        :in   std_ulogic;
+      ex2_lvl3_shdcd144        :in   std_ulogic;
+      ex2_lvl3_shdcd160        :in   std_ulogic;
+      ex2_lvl3_shdcd192        :in   std_ulogic;
+      ex2_lvl3_shdcd208        :in   std_ulogic;
+      ex2_lvl3_shdcd224        :in   std_ulogic;
+      ex2_lvl3_shdcd240        :in   std_ulogic;
+      ex2_sel_special          :in   std_ulogic;
+
+      ex2_sh_lvl2              :in   std_ulogic_vector(0 to 67) ;
+
+      ex2_sh16_162             :out std_ulogic ;
+      ex2_sh16_163             :out std_ulogic ;
+      ex2_sh_lvl3              :out std_ulogic_vector(0 to 162)  
+);
+
+
+
+end fuq_alg_sh16; 
+
+architecture fuq_alg_sh16 of fuq_alg_sh16 is
+
+    constant tiup : std_ulogic := '1';
+    constant tidn : std_ulogic := '0';
+
+    signal ex2_sh16_r1_b, ex2_sh16_r2_b, ex2_sh16_r3_b : std_ulogic_vector(0 to 162);
+    signal ex2_special :std_ulogic_vector(99 to 162);
+
+    
+ signal cpx_spc_b :std_ulogic;
+ signal cpx_000_b :std_ulogic;
+ signal cpx_016_b :std_ulogic;
+ signal cpx_032_b :std_ulogic;
+ signal cpx_048_b :std_ulogic;
+ signal cpx_064_b :std_ulogic;
+ signal cpx_080_b :std_ulogic;
+ signal cpx_096_b :std_ulogic;
+ signal cpx_112_b :std_ulogic;
+ signal cpx_128_b :std_ulogic;
+ signal cpx_144_b :std_ulogic;
+ signal cpx_160_b :std_ulogic;
+ signal cpx_192_b :std_ulogic;
+ signal cpx_208_b :std_ulogic;
+ signal cpx_224_b :std_ulogic;
+ signal cpx_240_b :std_ulogic;
+ signal cp1_spc   :std_ulogic;
+ signal cp1_000   :std_ulogic;
+ signal cp1_016   :std_ulogic;
+ signal cp1_032   :std_ulogic;
+ signal cp1_048   :std_ulogic;
+ signal cp1_064   :std_ulogic;
+ signal cp1_080   :std_ulogic;
+ signal cp1_096   :std_ulogic;
+ signal cp1_112   :std_ulogic;
+ signal cp1_128   :std_ulogic;
+ signal cp1_144   :std_ulogic;
+ signal cp1_160   :std_ulogic;
+ signal cp1_192   :std_ulogic;
+ signal cp1_208   :std_ulogic;
+ signal cp1_224   :std_ulogic;
+ signal cp1_240   :std_ulogic;
+ signal cp2_spc   :std_ulogic;
+ signal cp2_000   :std_ulogic;
+ signal cp2_016   :std_ulogic;
+ signal cp2_032   :std_ulogic;
+ signal cp2_048   :std_ulogic;
+ signal cp2_064   :std_ulogic;
+ signal cp2_080   :std_ulogic;
+ signal cp2_096   :std_ulogic;
+ signal cp2_112   :std_ulogic;
+ signal cp2_128   :std_ulogic;
+ signal cp2_144   :std_ulogic;
+ signal cp2_208   :std_ulogic;
+ signal cp2_224   :std_ulogic;
+ signal cp2_240   :std_ulogic;
+ signal cp3_spc   :std_ulogic;
+ signal cp3_000   :std_ulogic;
+ signal cp3_016   :std_ulogic;
+ signal cp3_032   :std_ulogic;
+ signal cp3_048   :std_ulogic;
+ signal cp3_064   :std_ulogic;
+ signal cp3_080   :std_ulogic;
+ signal cp3_096   :std_ulogic;
+ signal cp3_112   :std_ulogic;
+ signal cp3_128   :std_ulogic;
+ signal cp3_224   :std_ulogic;
+ signal cp3_240   :std_ulogic;
+ signal cp4_spc   :std_ulogic;
+ signal cp4_000   :std_ulogic;
+ signal cp4_016   :std_ulogic;
+ signal cp4_032   :std_ulogic;
+ signal cp4_048   :std_ulogic;
+ signal cp4_064   :std_ulogic;
+ signal cp4_080   :std_ulogic;
+ signal cp4_096   :std_ulogic;
+ signal cp4_112   :std_ulogic;
+ signal cp4_240   :std_ulogic;
+ signal cp5_spc   :std_ulogic;
+ signal cp5_000   :std_ulogic;
+ signal cp5_016   :std_ulogic;
+ signal cp5_032   :std_ulogic;
+ signal cp5_048   :std_ulogic;
+ signal cp5_064   :std_ulogic;
+ signal cp5_080   :std_ulogic;
+ signal cp5_096   :std_ulogic;
+signal ex2_sh16_r1_162_b, ex2_sh16_r2_162_b, ex2_sh16_r3_162_b :std_ulogic;
+signal ex2_sh16_r1_163_b, ex2_sh16_r2_163_b, ex2_sh16_r3_163_b :std_ulogic;
+
+
+     
+
+
+
+
+
+
+begin
+
+
+
+
+
+     ex2_special(99 to 162) <= ex2_sh_lvl2(0 to 63); 
+
+
+
+
+
+cxspcb: cpx_spc_b <= not ex2_sel_special    ;
+cx000b: cpx_000_b <= not ex2_lvl3_shdcd000 ;
+cx016b: cpx_016_b <= not ex2_lvl3_shdcd016  ;
+cx032b: cpx_032_b <= not ex2_lvl3_shdcd032  ;
+cx048b: cpx_048_b <= not ex2_lvl3_shdcd048  ;
+cx064b: cpx_064_b <= not ex2_lvl3_shdcd064  ;
+cx080b: cpx_080_b <= not ex2_lvl3_shdcd080  ;
+cx096b: cpx_096_b <= not ex2_lvl3_shdcd096  ;
+cx112b: cpx_112_b <= not ex2_lvl3_shdcd112  ;
+cx128b: cpx_128_b <= not ex2_lvl3_shdcd128  ;
+cx144b: cpx_144_b <= not ex2_lvl3_shdcd144  ;
+cx160b: cpx_160_b <= not ex2_lvl3_shdcd160  ;
+cx192b: cpx_192_b <= not ex2_lvl3_shdcd192  ;
+cx208b: cpx_208_b <= not ex2_lvl3_shdcd208  ;
+cx224b: cpx_224_b <= not ex2_lvl3_shdcd224  ;
+cx240b: cpx_240_b <= not ex2_lvl3_shdcd240  ;
+
+
+c1_spc: cp1_spc <= not cpx_spc_b ;
+c1_000: cp1_000 <= not cpx_000_b ;
+c1_016: cp1_016 <= not cpx_016_b ;
+c1_032: cp1_032 <= not cpx_032_b ;
+c1_048: cp1_048 <= not cpx_048_b ;
+c1_064: cp1_064 <= not cpx_064_b ;
+c1_080: cp1_080 <= not cpx_080_b ;
+c1_096: cp1_096 <= not cpx_096_b ;
+c1_112: cp1_112 <= not cpx_112_b ;
+c1_128: cp1_128 <= not cpx_128_b ;
+c1_144: cp1_144 <= not cpx_144_b ;
+c1_160: cp1_160 <= not cpx_160_b ;
+c1_192: cp1_192 <= not cpx_192_b ;
+c1_208: cp1_208 <= not cpx_208_b ;
+c1_224: cp1_224 <= not cpx_224_b ;
+c1_240: cp1_240 <= not cpx_240_b ;
+
+c2_spc: cp2_spc <= not cpx_spc_b ;
+c2_000: cp2_000 <= not cpx_000_b ;
+c2_016: cp2_016 <= not cpx_016_b ;
+c2_032: cp2_032 <= not cpx_032_b ;
+c2_048: cp2_048 <= not cpx_048_b ;
+c2_064: cp2_064 <= not cpx_064_b ;
+c2_080: cp2_080 <= not cpx_080_b ;
+c2_096: cp2_096 <= not cpx_096_b ;
+c2_112: cp2_112 <= not cpx_112_b ;
+c2_128: cp2_128 <= not cpx_128_b ;
+c2_144: cp2_144 <= not cpx_144_b ;
+c2_208: cp2_208 <= not cpx_208_b ;
+c2_224: cp2_224 <= not cpx_224_b ;
+c2_240: cp2_240 <= not cpx_240_b ;
+
+c3_spc: cp3_spc <= not cpx_spc_b ;
+c3_000: cp3_000 <= not cpx_000_b ;
+c3_016: cp3_016 <= not cpx_016_b ;
+c3_032: cp3_032 <= not cpx_032_b ;
+c3_048: cp3_048 <= not cpx_048_b ;
+c3_064: cp3_064 <= not cpx_064_b ;
+c3_080: cp3_080 <= not cpx_080_b ;
+c3_096: cp3_096 <= not cpx_096_b ;
+c3_112: cp3_112 <= not cpx_112_b ;
+c3_128: cp3_128 <= not cpx_128_b ;
+c3_224: cp3_224 <= not cpx_224_b ;
+c3_240: cp3_240 <= not cpx_240_b ;
+
+c4_spc: cp4_spc <= not cpx_spc_b ;
+c4_000: cp4_000 <= not cpx_000_b ;
+c4_016: cp4_016 <= not cpx_016_b ;
+c4_032: cp4_032 <= not cpx_032_b ;
+c4_048: cp4_048 <= not cpx_048_b ;
+c4_064: cp4_064 <= not cpx_064_b ;
+c4_080: cp4_080 <= not cpx_080_b ;
+c4_096: cp4_096 <= not cpx_096_b ;
+c4_112: cp4_112 <= not cpx_112_b ;
+c4_240: cp4_240 <= not cpx_240_b ;
+
+c5_spc: cp5_spc <= not cpx_spc_b ;
+c5_000: cp5_000 <= not cpx_000_b ;
+c5_016: cp5_016 <= not cpx_016_b ;
+c5_032: cp5_032 <= not cpx_032_b ;
+c5_048: cp5_048 <= not cpx_048_b ;
+c5_064: cp5_064 <= not cpx_064_b ;
+c5_080: cp5_080 <= not cpx_080_b ;
+c5_096: cp5_096 <= not cpx_096_b ;
+
+
+
+
+
+r1_000:   ex2_sh16_r1_b(0)     <= not( (cp1_192    and ex2_sh_lvl2(64)     ) or (cp1_208    and ex2_sh_lvl2(48)     ) );
+r1_001:   ex2_sh16_r1_b(1)     <= not( (cp1_192    and ex2_sh_lvl2(65)     ) or (cp1_208    and ex2_sh_lvl2(49)     ) );
+r1_002:   ex2_sh16_r1_b(2)     <= not( (cp1_192    and ex2_sh_lvl2(66)     ) or (cp1_208    and ex2_sh_lvl2(50)     ) );
+r1_003:   ex2_sh16_r1_b(3)     <= not( (cp1_192    and ex2_sh_lvl2(67)     ) or (cp1_208    and ex2_sh_lvl2(51)     ) );
+r1_004:   ex2_sh16_r1_b(4)     <= not(  cp1_208    and ex2_sh_lvl2(52)       );
+r1_005:   ex2_sh16_r1_b(5)     <= not(  cp1_208    and ex2_sh_lvl2(53)       );
+r1_006:   ex2_sh16_r1_b(6)     <= not(  cp1_208    and ex2_sh_lvl2(54)       );
+r1_007:   ex2_sh16_r1_b(7)     <= not(  cp1_208    and ex2_sh_lvl2(55)       );
+r1_008:   ex2_sh16_r1_b(8)     <= not(  cp1_208    and ex2_sh_lvl2(56)       );
+r1_009:   ex2_sh16_r1_b(9)     <= not(  cp1_208    and ex2_sh_lvl2(57)       );
+r1_010:   ex2_sh16_r1_b(10)    <= not(  cp1_208    and ex2_sh_lvl2(58)       );
+r1_011:   ex2_sh16_r1_b(11)    <= not(  cp1_208    and ex2_sh_lvl2(59)       );
+r1_012:   ex2_sh16_r1_b(12)    <= not(  cp1_208    and ex2_sh_lvl2(60)       );
+r1_013:   ex2_sh16_r1_b(13)    <= not(  cp1_208    and ex2_sh_lvl2(61)       );
+r1_014:   ex2_sh16_r1_b(14)    <= not(  cp1_208    and ex2_sh_lvl2(62)       );
+r1_015:   ex2_sh16_r1_b(15)    <= not(  cp1_208    and ex2_sh_lvl2(63)       );
+
+r1_016:   ex2_sh16_r1_b(16)    <= not( (cp2_208    and ex2_sh_lvl2(64)     ) or (cp2_224    and ex2_sh_lvl2(48)     ) );
+r1_017:   ex2_sh16_r1_b(17)    <= not( (cp2_208    and ex2_sh_lvl2(65)     ) or (cp2_224    and ex2_sh_lvl2(49)     ) );
+r1_018:   ex2_sh16_r1_b(18)    <= not( (cp2_208    and ex2_sh_lvl2(66)     ) or (cp2_224    and ex2_sh_lvl2(50)     ) );
+r1_019:   ex2_sh16_r1_b(19)    <= not( (cp2_208    and ex2_sh_lvl2(67)     ) or (cp2_224    and ex2_sh_lvl2(51)     ) );
+r1_020:   ex2_sh16_r1_b(20)    <= not(  cp2_224    and ex2_sh_lvl2(52)       );
+r1_021:   ex2_sh16_r1_b(21)    <= not(  cp2_224    and ex2_sh_lvl2(53)       );
+r1_022:   ex2_sh16_r1_b(22)    <= not(  cp2_224    and ex2_sh_lvl2(54)       );
+r1_023:   ex2_sh16_r1_b(23)    <= not(  cp2_224    and ex2_sh_lvl2(55)       );
+r1_024:   ex2_sh16_r1_b(24)    <= not(  cp2_224    and ex2_sh_lvl2(56)       );
+r1_025:   ex2_sh16_r1_b(25)    <= not(  cp2_224    and ex2_sh_lvl2(57)       );
+r1_026:   ex2_sh16_r1_b(26)    <= not(  cp2_224    and ex2_sh_lvl2(58)       );
+r1_027:   ex2_sh16_r1_b(27)    <= not(  cp2_224    and ex2_sh_lvl2(59)       );
+r1_028:   ex2_sh16_r1_b(28)    <= not(  cp2_224    and ex2_sh_lvl2(60)       );
+r1_029:   ex2_sh16_r1_b(29)    <= not(  cp2_224    and ex2_sh_lvl2(61)       );
+r1_030:   ex2_sh16_r1_b(30)    <= not(  cp2_224    and ex2_sh_lvl2(62)       );
+r1_031:   ex2_sh16_r1_b(31)    <= not(  cp2_224    and ex2_sh_lvl2(63)       );
+
+r1_032:   ex2_sh16_r1_b(32)    <= not( (cp3_224    and ex2_sh_lvl2(64)     ) or (cp3_240    and ex2_sh_lvl2(48)     ) );
+r1_033:   ex2_sh16_r1_b(33)    <= not( (cp3_224    and ex2_sh_lvl2(65)     ) or (cp3_240    and ex2_sh_lvl2(49)     ) );
+r1_034:   ex2_sh16_r1_b(34)    <= not( (cp3_224    and ex2_sh_lvl2(66)     ) or (cp3_240    and ex2_sh_lvl2(50)     ) );
+r1_035:   ex2_sh16_r1_b(35)    <= not( (cp3_224    and ex2_sh_lvl2(67)     ) or (cp3_240    and ex2_sh_lvl2(51)     ) );
+r1_036:   ex2_sh16_r1_b(36)    <= not(  cp3_240    and ex2_sh_lvl2(52)       );
+r1_037:   ex2_sh16_r1_b(37)    <= not(  cp3_240    and ex2_sh_lvl2(53)       );
+r1_038:   ex2_sh16_r1_b(38)    <= not(  cp3_240    and ex2_sh_lvl2(54)       );
+r1_039:   ex2_sh16_r1_b(39)    <= not(  cp3_240    and ex2_sh_lvl2(55)       );
+r1_040:   ex2_sh16_r1_b(40)    <= not(  cp3_240    and ex2_sh_lvl2(56)       );
+r1_041:   ex2_sh16_r1_b(41)    <= not(  cp3_240    and ex2_sh_lvl2(57)       );
+r1_042:   ex2_sh16_r1_b(42)    <= not(  cp3_240    and ex2_sh_lvl2(58)       );
+r1_043:   ex2_sh16_r1_b(43)    <= not(  cp3_240    and ex2_sh_lvl2(59)       );
+r1_044:   ex2_sh16_r1_b(44)    <= not(  cp3_240    and ex2_sh_lvl2(60)       );
+r1_045:   ex2_sh16_r1_b(45)    <= not(  cp3_240    and ex2_sh_lvl2(61)       );
+r1_046:   ex2_sh16_r1_b(46)    <= not(  cp3_240    and ex2_sh_lvl2(62)       );   
+r1_047:   ex2_sh16_r1_b(47)    <= not(  cp3_240    and ex2_sh_lvl2(63)       );
+
+r1_048:   ex2_sh16_r1_b(48)    <= not( (cp4_240    and ex2_sh_lvl2(64)     ) or (cp4_000    and ex2_sh_lvl2(48)     ) );
+r1_049:   ex2_sh16_r1_b(49)    <= not( (cp4_240    and ex2_sh_lvl2(65)     ) or (cp4_000    and ex2_sh_lvl2(49)     ) );
+r1_050:   ex2_sh16_r1_b(50)    <= not( (cp4_240    and ex2_sh_lvl2(66)     ) or (cp4_000    and ex2_sh_lvl2(50)     ) );
+r1_051:   ex2_sh16_r1_b(51)    <= not( (cp4_240    and ex2_sh_lvl2(67)     ) or (cp4_000    and ex2_sh_lvl2(51)     ) );
+r1_052:   ex2_sh16_r1_b(52)    <= not(  cp4_000    and ex2_sh_lvl2(52)       );
+r1_053:   ex2_sh16_r1_b(53)    <= not(  cp4_000    and ex2_sh_lvl2(53)       );
+r1_054:   ex2_sh16_r1_b(54)    <= not(  cp4_000    and ex2_sh_lvl2(54)       );
+r1_055:   ex2_sh16_r1_b(55)    <= not(  cp4_000    and ex2_sh_lvl2(55)       );
+r1_056:   ex2_sh16_r1_b(56)    <= not(  cp4_000    and ex2_sh_lvl2(56)       );
+r1_057:   ex2_sh16_r1_b(57)    <= not(  cp4_000    and ex2_sh_lvl2(57)       );
+r1_058:   ex2_sh16_r1_b(58)    <= not(  cp4_000    and ex2_sh_lvl2(58)       );  
+r1_059:   ex2_sh16_r1_b(59)    <= not(  cp4_000    and ex2_sh_lvl2(59)       );
+r1_060:   ex2_sh16_r1_b(60)    <= not(  cp4_000    and ex2_sh_lvl2(60)       );
+r1_061:   ex2_sh16_r1_b(61)    <= not(  cp4_000    and ex2_sh_lvl2(61)       );
+r1_062:   ex2_sh16_r1_b(62)    <= not(  cp4_000    and ex2_sh_lvl2(62)       );
+r1_063:   ex2_sh16_r1_b(63)    <= not(  cp4_000    and ex2_sh_lvl2(63)       );
+
+r1_064:   ex2_sh16_r1_b(64)    <= not( (cp5_000    and ex2_sh_lvl2(64)     ) or (cp4_016    and ex2_sh_lvl2(48)     ) );
+r1_065:   ex2_sh16_r1_b(65)    <= not( (cp5_000    and ex2_sh_lvl2(65)     ) or (cp4_016    and ex2_sh_lvl2(49)     ) );
+r1_066:   ex2_sh16_r1_b(66)    <= not( (cp5_000    and ex2_sh_lvl2(66)     ) or (cp4_016    and ex2_sh_lvl2(50)     ) );
+r1_067:   ex2_sh16_r1_b(67)    <= not( (cp5_000    and ex2_sh_lvl2(67)     ) or (cp4_016    and ex2_sh_lvl2(51)     ) );
+r1_068:   ex2_sh16_r1_b(68)    <= not(  cp4_016    and ex2_sh_lvl2(52)       );
+r1_069:   ex2_sh16_r1_b(69)    <= not(  cp4_016    and ex2_sh_lvl2(53)       );
+r1_070:   ex2_sh16_r1_b(70)    <= not(  cp4_016    and ex2_sh_lvl2(54)       );
+r1_071:   ex2_sh16_r1_b(71)    <= not(  cp4_016    and ex2_sh_lvl2(55)       );
+r1_072:   ex2_sh16_r1_b(72)    <= not(  cp4_016    and ex2_sh_lvl2(56)       );
+r1_073:   ex2_sh16_r1_b(73)    <= not(  cp4_016    and ex2_sh_lvl2(57)       );
+r1_074:   ex2_sh16_r1_b(74)    <= not(  cp4_016    and ex2_sh_lvl2(58)       );
+r1_075:   ex2_sh16_r1_b(75)    <= not(  cp4_016    and ex2_sh_lvl2(59)       );
+r1_076:   ex2_sh16_r1_b(76)    <= not(  cp4_016    and ex2_sh_lvl2(60)       );
+r1_077:   ex2_sh16_r1_b(77)    <= not(  cp4_016    and ex2_sh_lvl2(61)       );
+r1_078:   ex2_sh16_r1_b(78)    <= not(  cp4_016    and ex2_sh_lvl2(62)       );
+r1_079:   ex2_sh16_r1_b(79)    <= not(  cp4_016    and ex2_sh_lvl2(63)       );
+
+r1_080:   ex2_sh16_r1_b(80)    <= not( (cp5_016    and ex2_sh_lvl2(64)     ) or (cp4_032    and ex2_sh_lvl2(48)     ) );
+r1_081:   ex2_sh16_r1_b(81)    <= not( (cp5_016    and ex2_sh_lvl2(65)     ) or (cp4_032    and ex2_sh_lvl2(49)     ) );
+r1_082:   ex2_sh16_r1_b(82)    <= not( (cp5_016    and ex2_sh_lvl2(66)     ) or (cp4_032    and ex2_sh_lvl2(50)     ) );
+r1_083:   ex2_sh16_r1_b(83)    <= not( (cp5_016    and ex2_sh_lvl2(67)     ) or (cp4_032    and ex2_sh_lvl2(51)     ) );
+r1_084:   ex2_sh16_r1_b(84)    <= not(  cp4_032    and ex2_sh_lvl2(52)       );
+r1_085:   ex2_sh16_r1_b(85)    <= not(  cp4_032    and ex2_sh_lvl2(53)       );
+r1_086:   ex2_sh16_r1_b(86)    <= not(  cp4_032    and ex2_sh_lvl2(54)       );
+r1_087:   ex2_sh16_r1_b(87)    <= not(  cp4_032    and ex2_sh_lvl2(55)       );
+r1_088:   ex2_sh16_r1_b(88)    <= not(  cp4_032    and ex2_sh_lvl2(56)       );
+r1_089:   ex2_sh16_r1_b(89)    <= not(  cp4_032    and ex2_sh_lvl2(57)       );
+r1_090:   ex2_sh16_r1_b(90)    <= not(  cp4_032    and ex2_sh_lvl2(58)       );
+r1_091:   ex2_sh16_r1_b(91)    <= not(  cp4_032    and ex2_sh_lvl2(59)       );
+r1_092:   ex2_sh16_r1_b(92)    <= not(  cp4_032    and ex2_sh_lvl2(60)       );
+r1_093:   ex2_sh16_r1_b(93)    <= not(  cp4_032    and ex2_sh_lvl2(61)       );
+r1_094:   ex2_sh16_r1_b(94)    <= not(  cp4_032    and ex2_sh_lvl2(62)       );
+r1_095:   ex2_sh16_r1_b(95)    <= not(  cp4_032    and ex2_sh_lvl2(63)       );
+
+r1_096:   ex2_sh16_r1_b(96)    <= not( (cp5_032    and ex2_sh_lvl2(64)     ) or (cp4_048    and ex2_sh_lvl2(48)     ) );
+r1_097:   ex2_sh16_r1_b(97)    <= not( (cp5_032    and ex2_sh_lvl2(65)     ) or (cp4_048    and ex2_sh_lvl2(49)     ) );
+r1_098:   ex2_sh16_r1_b(98)    <= not( (cp5_032    and ex2_sh_lvl2(66)     ) or (cp4_048    and ex2_sh_lvl2(50)     ) );
+r1_099:   ex2_sh16_r1_b(99)    <= not( (cp5_032    and ex2_sh_lvl2(67)     ) or (cp4_048    and ex2_sh_lvl2(51)     ) );
+r1_100:   ex2_sh16_r1_b(100)   <= not(  cp4_048    and ex2_sh_lvl2(52)       );
+r1_101:   ex2_sh16_r1_b(101)   <= not(  cp4_048    and ex2_sh_lvl2(53)       );
+r1_102:   ex2_sh16_r1_b(102)   <= not(  cp4_048    and ex2_sh_lvl2(54)       );
+r1_103:   ex2_sh16_r1_b(103)   <= not(  cp4_048    and ex2_sh_lvl2(55)       );
+r1_104:   ex2_sh16_r1_b(104)   <= not(  cp4_048    and ex2_sh_lvl2(56)       );
+r1_105:   ex2_sh16_r1_b(105)   <= not(  cp4_048    and ex2_sh_lvl2(57)       );
+r1_106:   ex2_sh16_r1_b(106)   <= not(  cp4_048    and ex2_sh_lvl2(58)       );
+r1_107:   ex2_sh16_r1_b(107)   <= not(  cp4_048    and ex2_sh_lvl2(59)       );
+r1_108:   ex2_sh16_r1_b(108)   <= not(  cp4_048    and ex2_sh_lvl2(60)       );
+r1_109:   ex2_sh16_r1_b(109)   <= not(  cp4_048    and ex2_sh_lvl2(61)       );
+r1_110:   ex2_sh16_r1_b(110)   <= not(  cp4_048    and ex2_sh_lvl2(62)       );
+r1_111:   ex2_sh16_r1_b(111)   <= not(  cp4_048    and ex2_sh_lvl2(63)       );
+
+r1_112:   ex2_sh16_r1_b(112)   <= not( (cp5_048    and ex2_sh_lvl2(64)     ) or (cp4_064    and ex2_sh_lvl2(48)     ) );
+r1_113:   ex2_sh16_r1_b(113)   <= not( (cp5_048    and ex2_sh_lvl2(65)     ) or (cp4_064    and ex2_sh_lvl2(49)     ) );
+r1_114:   ex2_sh16_r1_b(114)   <= not( (cp5_048    and ex2_sh_lvl2(66)     ) or (cp4_064    and ex2_sh_lvl2(50)     ) );
+r1_115:   ex2_sh16_r1_b(115)   <= not( (cp5_048    and ex2_sh_lvl2(67)     ) or (cp4_064    and ex2_sh_lvl2(51)     ) );
+r1_116:   ex2_sh16_r1_b(116)   <= not(  cp4_064    and ex2_sh_lvl2(52)       );
+r1_117:   ex2_sh16_r1_b(117)   <= not(  cp4_064    and ex2_sh_lvl2(53)       );
+r1_118:   ex2_sh16_r1_b(118)   <= not(  cp4_064    and ex2_sh_lvl2(54)       );
+r1_119:   ex2_sh16_r1_b(119)   <= not(  cp4_064    and ex2_sh_lvl2(55)       );
+r1_120:   ex2_sh16_r1_b(120)   <= not(  cp4_064    and ex2_sh_lvl2(56)       );
+r1_121:   ex2_sh16_r1_b(121)   <= not(  cp4_064    and ex2_sh_lvl2(57)       );
+r1_122:   ex2_sh16_r1_b(122)   <= not(  cp4_064    and ex2_sh_lvl2(58)       );
+r1_123:   ex2_sh16_r1_b(123)   <= not(  cp4_064    and ex2_sh_lvl2(59)       );
+r1_124:   ex2_sh16_r1_b(124)   <= not(  cp4_064    and ex2_sh_lvl2(60)       );
+r1_125:   ex2_sh16_r1_b(125)   <= not(  cp4_064    and ex2_sh_lvl2(61)       );
+r1_126:   ex2_sh16_r1_b(126)   <= not(  cp4_064    and ex2_sh_lvl2(62)       );
+r1_127:   ex2_sh16_r1_b(127)   <= not(  cp4_064    and ex2_sh_lvl2(63)       );      
+
+r1_128:   ex2_sh16_r1_b(128)   <= not( (cp5_064    and ex2_sh_lvl2(64)     ) or (cp4_080    and ex2_sh_lvl2(48)     ) );
+r1_129:   ex2_sh16_r1_b(129)   <= not( (cp5_064    and ex2_sh_lvl2(65)     ) or (cp4_080    and ex2_sh_lvl2(49)     ) );
+r1_130:   ex2_sh16_r1_b(130)   <= not( (cp5_064    and ex2_sh_lvl2(66)     ) or (cp4_080    and ex2_sh_lvl2(50)     ) );
+r1_131:   ex2_sh16_r1_b(131)   <= not( (cp5_064    and ex2_sh_lvl2(67)     ) or (cp4_080    and ex2_sh_lvl2(51)     ) );
+r1_132:   ex2_sh16_r1_b(132)   <= not(  cp4_080    and ex2_sh_lvl2(52)       );
+r1_133:   ex2_sh16_r1_b(133)   <= not(  cp4_080    and ex2_sh_lvl2(53)       );
+r1_134:   ex2_sh16_r1_b(134)   <= not(  cp4_080    and ex2_sh_lvl2(54)       );
+r1_135:   ex2_sh16_r1_b(135)   <= not(  cp4_080    and ex2_sh_lvl2(55)       );
+r1_136:   ex2_sh16_r1_b(136)   <= not(  cp4_080    and ex2_sh_lvl2(56)       );
+r1_137:   ex2_sh16_r1_b(137)   <= not(  cp4_080    and ex2_sh_lvl2(57)       );
+r1_138:   ex2_sh16_r1_b(138)   <= not(  cp4_080    and ex2_sh_lvl2(58)       );
+r1_139:   ex2_sh16_r1_b(139)   <= not(  cp4_080    and ex2_sh_lvl2(59)       );
+r1_140:   ex2_sh16_r1_b(140)   <= not(  cp4_080    and ex2_sh_lvl2(60)       );
+r1_141:   ex2_sh16_r1_b(141)   <= not(  cp4_080    and ex2_sh_lvl2(61)       );
+r1_142:   ex2_sh16_r1_b(142)   <= not(  cp4_080    and ex2_sh_lvl2(62)       );
+r1_143:   ex2_sh16_r1_b(143)   <= not(  cp4_080    and ex2_sh_lvl2(63)       );
+
+r1_144:   ex2_sh16_r1_b(144)   <= not( (cp5_080    and ex2_sh_lvl2(64)     ) or (cp4_096    and ex2_sh_lvl2(48)     ) );
+r1_145:   ex2_sh16_r1_b(145)   <= not( (cp5_080    and ex2_sh_lvl2(65)     ) or (cp4_096    and ex2_sh_lvl2(49)     ) );
+r1_146:   ex2_sh16_r1_b(146)   <= not( (cp5_080    and ex2_sh_lvl2(66)     ) or (cp4_096    and ex2_sh_lvl2(50)     ) );
+r1_147:   ex2_sh16_r1_b(147)   <= not( (cp5_080    and ex2_sh_lvl2(67)     ) or (cp4_096    and ex2_sh_lvl2(51)     ) );
+r1_148:   ex2_sh16_r1_b(148)   <= not(  cp4_096    and ex2_sh_lvl2(52)       );
+r1_149:   ex2_sh16_r1_b(149)   <= not(  cp4_096    and ex2_sh_lvl2(53)       );
+r1_150:   ex2_sh16_r1_b(150)   <= not(  cp4_096    and ex2_sh_lvl2(54)       );
+r1_151:   ex2_sh16_r1_b(151)   <= not(  cp4_096    and ex2_sh_lvl2(55)       );
+r1_152:   ex2_sh16_r1_b(152)   <= not(  cp4_096    and ex2_sh_lvl2(56)       );
+r1_153:   ex2_sh16_r1_b(153)   <= not(  cp4_096    and ex2_sh_lvl2(57)       );
+r1_154:   ex2_sh16_r1_b(154)   <= not(  cp4_096    and ex2_sh_lvl2(58)       );
+r1_155:   ex2_sh16_r1_b(155)   <= not(  cp4_096    and ex2_sh_lvl2(59)       );
+r1_156:   ex2_sh16_r1_b(156)   <= not(  cp4_096    and ex2_sh_lvl2(60)       );
+r1_157:   ex2_sh16_r1_b(157)   <= not(  cp4_096    and ex2_sh_lvl2(61)       );
+r1_158:   ex2_sh16_r1_b(158)   <= not(  cp4_096    and ex2_sh_lvl2(62)       );
+r1_159:   ex2_sh16_r1_b(159)   <= not(  cp4_096    and ex2_sh_lvl2(63)       );
+
+r1_160:   ex2_sh16_r1_b(160)   <= not( (cp5_096    and ex2_sh_lvl2(64)     ) or (cp4_112    and ex2_sh_lvl2(48)     ) );
+r1_161:   ex2_sh16_r1_b(161)   <= not( (cp5_096    and ex2_sh_lvl2(65)     ) or (cp4_112    and ex2_sh_lvl2(49)     ) );
+r1_162:   ex2_sh16_r1_b(162)   <= not( (cp5_096    and ex2_sh_lvl2(66)     ) or (cp4_112    and ex2_sh_lvl2(50)     ) );
+
+r2_000:   ex2_sh16_r2_b(0)     <= not( (cp1_224    and ex2_sh_lvl2(32)     ) or (cp1_240    and ex2_sh_lvl2(16)     ) );
+r2_001:   ex2_sh16_r2_b(1)     <= not( (cp1_224    and ex2_sh_lvl2(33)     ) or (cp1_240    and ex2_sh_lvl2(17)     ) );
+r2_002:   ex2_sh16_r2_b(2)     <= not( (cp1_224    and ex2_sh_lvl2(34)     ) or (cp1_240    and ex2_sh_lvl2(18)     ) );
+r2_003:   ex2_sh16_r2_b(3)     <= not( (cp1_224    and ex2_sh_lvl2(35)     ) or (cp1_240    and ex2_sh_lvl2(19)     ) );
+r2_004:   ex2_sh16_r2_b(4)     <= not( (cp1_224    and ex2_sh_lvl2(36)     ) or (cp1_240    and ex2_sh_lvl2(20)     ) );
+r2_005:   ex2_sh16_r2_b(5)     <= not( (cp1_224    and ex2_sh_lvl2(37)     ) or (cp1_240    and ex2_sh_lvl2(21)     ) );
+r2_006:   ex2_sh16_r2_b(6)     <= not( (cp1_224    and ex2_sh_lvl2(38)     ) or (cp1_240    and ex2_sh_lvl2(22)     ) );
+r2_007:   ex2_sh16_r2_b(7)     <= not( (cp1_224    and ex2_sh_lvl2(39)     ) or (cp1_240    and ex2_sh_lvl2(23)     ) );
+r2_008:   ex2_sh16_r2_b(8)     <= not( (cp1_224    and ex2_sh_lvl2(40)     ) or (cp1_240    and ex2_sh_lvl2(24)     ) );
+r2_009:   ex2_sh16_r2_b(9)     <= not( (cp1_224    and ex2_sh_lvl2(41)     ) or (cp1_240    and ex2_sh_lvl2(25)     ) );
+r2_010:   ex2_sh16_r2_b(10)    <= not( (cp1_224    and ex2_sh_lvl2(42)     ) or (cp1_240    and ex2_sh_lvl2(26)     ) );
+r2_011:   ex2_sh16_r2_b(11)    <= not( (cp1_224    and ex2_sh_lvl2(43)     ) or (cp1_240    and ex2_sh_lvl2(27)     ) );
+r2_012:   ex2_sh16_r2_b(12)    <= not( (cp1_224    and ex2_sh_lvl2(44)     ) or (cp1_240    and ex2_sh_lvl2(28)     ) );
+r2_013:   ex2_sh16_r2_b(13)    <= not( (cp1_224    and ex2_sh_lvl2(45)     ) or (cp1_240    and ex2_sh_lvl2(29)     ) );
+r2_014:   ex2_sh16_r2_b(14)    <= not( (cp1_224    and ex2_sh_lvl2(46)     ) or (cp1_240    and ex2_sh_lvl2(30)     ) );
+r2_015:   ex2_sh16_r2_b(15)    <= not( (cp1_224    and ex2_sh_lvl2(47)     ) or (cp1_240    and ex2_sh_lvl2(31)     ) );
+
+r2_016:   ex2_sh16_r2_b(16)    <= not( (cp2_240    and ex2_sh_lvl2(32)     ) or (cp2_000    and ex2_sh_lvl2(16)     ) );
+r2_017:   ex2_sh16_r2_b(17)    <= not( (cp2_240    and ex2_sh_lvl2(33)     ) or (cp2_000    and ex2_sh_lvl2(17)     ) );
+r2_018:   ex2_sh16_r2_b(18)    <= not( (cp2_240    and ex2_sh_lvl2(34)     ) or (cp2_000    and ex2_sh_lvl2(18)     ) );
+r2_019:   ex2_sh16_r2_b(19)    <= not( (cp2_240    and ex2_sh_lvl2(35)     ) or (cp2_000    and ex2_sh_lvl2(19)     ) );
+r2_020:   ex2_sh16_r2_b(20)    <= not( (cp2_240    and ex2_sh_lvl2(36)     ) or (cp2_000    and ex2_sh_lvl2(20)     ) );
+r2_021:   ex2_sh16_r2_b(21)    <= not( (cp2_240    and ex2_sh_lvl2(37)     ) or (cp2_000    and ex2_sh_lvl2(21)     ) );
+r2_022:   ex2_sh16_r2_b(22)    <= not( (cp2_240    and ex2_sh_lvl2(38)     ) or (cp2_000    and ex2_sh_lvl2(22)     ) );
+r2_023:   ex2_sh16_r2_b(23)    <= not( (cp2_240    and ex2_sh_lvl2(39)     ) or (cp2_000    and ex2_sh_lvl2(23)     ) );
+r2_024:   ex2_sh16_r2_b(24)    <= not( (cp2_240    and ex2_sh_lvl2(40)     ) or (cp2_000    and ex2_sh_lvl2(24)     ) );
+r2_025:   ex2_sh16_r2_b(25)    <= not( (cp2_240    and ex2_sh_lvl2(41)     ) or (cp2_000    and ex2_sh_lvl2(25)     ) );
+r2_026:   ex2_sh16_r2_b(26)    <= not( (cp2_240    and ex2_sh_lvl2(42)     ) or (cp2_000    and ex2_sh_lvl2(26)     ) );
+r2_027:   ex2_sh16_r2_b(27)    <= not( (cp2_240    and ex2_sh_lvl2(43)     ) or (cp2_000    and ex2_sh_lvl2(27)     ) );
+r2_028:   ex2_sh16_r2_b(28)    <= not( (cp2_240    and ex2_sh_lvl2(44)     ) or (cp2_000    and ex2_sh_lvl2(28)     ) );
+r2_029:   ex2_sh16_r2_b(29)    <= not( (cp2_240    and ex2_sh_lvl2(45)     ) or (cp2_000    and ex2_sh_lvl2(29)     ) );
+r2_030:   ex2_sh16_r2_b(30)    <= not( (cp2_240    and ex2_sh_lvl2(46)     ) or (cp2_000    and ex2_sh_lvl2(30)     ) );
+r2_031:   ex2_sh16_r2_b(31)    <= not( (cp2_240    and ex2_sh_lvl2(47)     ) or (cp2_000    and ex2_sh_lvl2(31)     ) );
+
+r2_032:   ex2_sh16_r2_b(32)    <= not( (cp3_000    and ex2_sh_lvl2(32)     ) or (cp2_016    and ex2_sh_lvl2(16)     ) );
+r2_033:   ex2_sh16_r2_b(33)    <= not( (cp3_000    and ex2_sh_lvl2(33)     ) or (cp2_016    and ex2_sh_lvl2(17)     ) );
+r2_034:   ex2_sh16_r2_b(34)    <= not( (cp3_000    and ex2_sh_lvl2(34)     ) or (cp2_016    and ex2_sh_lvl2(18)     ) );
+r2_035:   ex2_sh16_r2_b(35)    <= not( (cp3_000    and ex2_sh_lvl2(35)     ) or (cp2_016    and ex2_sh_lvl2(19)     ) );
+r2_036:   ex2_sh16_r2_b(36)    <= not( (cp3_000    and ex2_sh_lvl2(36)     ) or (cp2_016    and ex2_sh_lvl2(20)     ) );
+r2_037:   ex2_sh16_r2_b(37)    <= not( (cp3_000    and ex2_sh_lvl2(37)     ) or (cp2_016    and ex2_sh_lvl2(21)     ) );
+r2_038:   ex2_sh16_r2_b(38)    <= not( (cp3_000    and ex2_sh_lvl2(38)     ) or (cp2_016    and ex2_sh_lvl2(22)     ) );
+r2_039:   ex2_sh16_r2_b(39)    <= not( (cp3_000    and ex2_sh_lvl2(39)     ) or (cp2_016    and ex2_sh_lvl2(23)     ) );
+r2_040:   ex2_sh16_r2_b(40)    <= not( (cp3_000    and ex2_sh_lvl2(40)     ) or (cp2_016    and ex2_sh_lvl2(24)     ) );
+r2_041:   ex2_sh16_r2_b(41)    <= not( (cp3_000    and ex2_sh_lvl2(41)     ) or (cp2_016    and ex2_sh_lvl2(25)     ) );
+r2_042:   ex2_sh16_r2_b(42)    <= not( (cp3_000    and ex2_sh_lvl2(42)     ) or (cp2_016    and ex2_sh_lvl2(26)     ) );
+r2_043:   ex2_sh16_r2_b(43)    <= not( (cp3_000    and ex2_sh_lvl2(43)     ) or (cp2_016    and ex2_sh_lvl2(27)     ) );
+r2_044:   ex2_sh16_r2_b(44)    <= not( (cp3_000    and ex2_sh_lvl2(44)     ) or (cp2_016    and ex2_sh_lvl2(28)     ) );
+r2_045:   ex2_sh16_r2_b(45)    <= not( (cp3_000    and ex2_sh_lvl2(45)     ) or (cp2_016    and ex2_sh_lvl2(29)     ) );
+r2_046:   ex2_sh16_r2_b(46)    <= not( (cp3_000    and ex2_sh_lvl2(46)     ) or (cp2_016    and ex2_sh_lvl2(30)     ) );
+r2_047:   ex2_sh16_r2_b(47)    <= not( (cp3_000    and ex2_sh_lvl2(47)     ) or (cp2_016    and ex2_sh_lvl2(31)     ) );
+
+r2_048:   ex2_sh16_r2_b(48)    <= not( (cp3_016    and ex2_sh_lvl2(32)     ) or (cp2_032    and ex2_sh_lvl2(16)     ) );
+r2_049:   ex2_sh16_r2_b(49)    <= not( (cp3_016    and ex2_sh_lvl2(33)     ) or (cp2_032    and ex2_sh_lvl2(17)     ) );
+r2_050:   ex2_sh16_r2_b(50)    <= not( (cp3_016    and ex2_sh_lvl2(34)     ) or (cp2_032    and ex2_sh_lvl2(18)     ) );
+r2_051:   ex2_sh16_r2_b(51)    <= not( (cp3_016    and ex2_sh_lvl2(35)     ) or (cp2_032    and ex2_sh_lvl2(19)     ) );
+r2_052:   ex2_sh16_r2_b(52)    <= not( (cp3_016    and ex2_sh_lvl2(36)     ) or (cp2_032    and ex2_sh_lvl2(20)     ) );
+r2_053:   ex2_sh16_r2_b(53)    <= not( (cp3_016    and ex2_sh_lvl2(37)     ) or (cp2_032    and ex2_sh_lvl2(21)     ) );
+r2_054:   ex2_sh16_r2_b(54)    <= not( (cp3_016    and ex2_sh_lvl2(38)     ) or (cp2_032    and ex2_sh_lvl2(22)     ) );
+r2_055:   ex2_sh16_r2_b(55)    <= not( (cp3_016    and ex2_sh_lvl2(39)     ) or (cp2_032    and ex2_sh_lvl2(23)     ) );
+r2_056:   ex2_sh16_r2_b(56)    <= not( (cp3_016    and ex2_sh_lvl2(40)     ) or (cp2_032    and ex2_sh_lvl2(24)     ) );
+r2_057:   ex2_sh16_r2_b(57)    <= not( (cp3_016    and ex2_sh_lvl2(41)     ) or (cp2_032    and ex2_sh_lvl2(25)     ) );
+r2_058:   ex2_sh16_r2_b(58)    <= not( (cp3_016    and ex2_sh_lvl2(42)     ) or (cp2_032    and ex2_sh_lvl2(26)     ) );
+r2_059:   ex2_sh16_r2_b(59)    <= not( (cp3_016    and ex2_sh_lvl2(43)     ) or (cp2_032    and ex2_sh_lvl2(27)     ) );
+r2_060:   ex2_sh16_r2_b(60)    <= not( (cp3_016    and ex2_sh_lvl2(44)     ) or (cp2_032    and ex2_sh_lvl2(28)     ) );
+r2_061:   ex2_sh16_r2_b(61)    <= not( (cp3_016    and ex2_sh_lvl2(45)     ) or (cp2_032    and ex2_sh_lvl2(29)     ) );
+r2_062:   ex2_sh16_r2_b(62)    <= not( (cp3_016    and ex2_sh_lvl2(46)     ) or (cp2_032    and ex2_sh_lvl2(30)     ) );
+r2_063:   ex2_sh16_r2_b(63)    <= not( (cp3_016    and ex2_sh_lvl2(47)     ) or (cp2_032    and ex2_sh_lvl2(31)     ) );
+
+r2_064:   ex2_sh16_r2_b(64)    <= not( (cp3_032    and ex2_sh_lvl2(32)     ) or (cp2_048    and ex2_sh_lvl2(16)     ) );
+r2_065:   ex2_sh16_r2_b(65)    <= not( (cp3_032    and ex2_sh_lvl2(33)     ) or (cp2_048    and ex2_sh_lvl2(17)     ) );
+r2_066:   ex2_sh16_r2_b(66)    <= not( (cp3_032    and ex2_sh_lvl2(34)     ) or (cp2_048    and ex2_sh_lvl2(18)     ) );
+r2_067:   ex2_sh16_r2_b(67)    <= not( (cp3_032    and ex2_sh_lvl2(35)     ) or (cp2_048    and ex2_sh_lvl2(19)     ) );
+r2_068:   ex2_sh16_r2_b(68)    <= not( (cp3_032    and ex2_sh_lvl2(36)     ) or (cp2_048    and ex2_sh_lvl2(20)     ) );
+r2_069:   ex2_sh16_r2_b(69)    <= not( (cp3_032    and ex2_sh_lvl2(37)     ) or (cp2_048    and ex2_sh_lvl2(21)     ) );
+r2_070:   ex2_sh16_r2_b(70)    <= not( (cp3_032    and ex2_sh_lvl2(38)     ) or (cp2_048    and ex2_sh_lvl2(22)     ) );
+r2_071:   ex2_sh16_r2_b(71)    <= not( (cp3_032    and ex2_sh_lvl2(39)     ) or (cp2_048    and ex2_sh_lvl2(23)     ) );
+r2_072:   ex2_sh16_r2_b(72)    <= not( (cp3_032    and ex2_sh_lvl2(40)     ) or (cp2_048    and ex2_sh_lvl2(24)     ) );
+r2_073:   ex2_sh16_r2_b(73)    <= not( (cp3_032    and ex2_sh_lvl2(41)     ) or (cp2_048    and ex2_sh_lvl2(25)     ) );
+r2_074:   ex2_sh16_r2_b(74)    <= not( (cp3_032    and ex2_sh_lvl2(42)     ) or (cp2_048    and ex2_sh_lvl2(26)     ) );
+r2_075:   ex2_sh16_r2_b(75)    <= not( (cp3_032    and ex2_sh_lvl2(43)     ) or (cp2_048    and ex2_sh_lvl2(27)     ) );
+r2_076:   ex2_sh16_r2_b(76)    <= not( (cp3_032    and ex2_sh_lvl2(44)     ) or (cp2_048    and ex2_sh_lvl2(28)     ) );
+r2_077:   ex2_sh16_r2_b(77)    <= not( (cp3_032    and ex2_sh_lvl2(45)     ) or (cp2_048    and ex2_sh_lvl2(29)     ) );
+r2_078:   ex2_sh16_r2_b(78)    <= not( (cp3_032    and ex2_sh_lvl2(46)     ) or (cp2_048    and ex2_sh_lvl2(30)     ) );
+r2_079:   ex2_sh16_r2_b(79)    <= not( (cp3_032    and ex2_sh_lvl2(47)     ) or (cp2_048    and ex2_sh_lvl2(31)     ) );
+
+r2_080:   ex2_sh16_r2_b(80)    <= not( (cp3_048    and ex2_sh_lvl2(32)     ) or (cp2_064    and ex2_sh_lvl2(16)     ) );
+r2_081:   ex2_sh16_r2_b(81)    <= not( (cp3_048    and ex2_sh_lvl2(33)     ) or (cp2_064    and ex2_sh_lvl2(17)     ) );
+r2_082:   ex2_sh16_r2_b(82)    <= not( (cp3_048    and ex2_sh_lvl2(34)     ) or (cp2_064    and ex2_sh_lvl2(18)     ) );
+r2_083:   ex2_sh16_r2_b(83)    <= not( (cp3_048    and ex2_sh_lvl2(35)     ) or (cp2_064    and ex2_sh_lvl2(19)     ) );
+r2_084:   ex2_sh16_r2_b(84)    <= not( (cp3_048    and ex2_sh_lvl2(36)     ) or (cp2_064    and ex2_sh_lvl2(20)     ) );
+r2_085:   ex2_sh16_r2_b(85)    <= not( (cp3_048    and ex2_sh_lvl2(37)     ) or (cp2_064    and ex2_sh_lvl2(21)     ) );
+r2_086:   ex2_sh16_r2_b(86)    <= not( (cp3_048    and ex2_sh_lvl2(38)     ) or (cp2_064    and ex2_sh_lvl2(22)     ) );
+r2_087:   ex2_sh16_r2_b(87)    <= not( (cp3_048    and ex2_sh_lvl2(39)     ) or (cp2_064    and ex2_sh_lvl2(23)     ) );
+r2_088:   ex2_sh16_r2_b(88)    <= not( (cp3_048    and ex2_sh_lvl2(40)     ) or (cp2_064    and ex2_sh_lvl2(24)     ) );
+r2_089:   ex2_sh16_r2_b(89)    <= not( (cp3_048    and ex2_sh_lvl2(41)     ) or (cp2_064    and ex2_sh_lvl2(25)     ) );
+r2_090:   ex2_sh16_r2_b(90)    <= not( (cp3_048    and ex2_sh_lvl2(42)     ) or (cp2_064    and ex2_sh_lvl2(26)     ) );
+r2_091:   ex2_sh16_r2_b(91)    <= not( (cp3_048    and ex2_sh_lvl2(43)     ) or (cp2_064    and ex2_sh_lvl2(27)     ) );
+r2_092:   ex2_sh16_r2_b(92)    <= not( (cp3_048    and ex2_sh_lvl2(44)     ) or (cp2_064    and ex2_sh_lvl2(28)     ) );
+r2_093:   ex2_sh16_r2_b(93)    <= not( (cp3_048    and ex2_sh_lvl2(45)     ) or (cp2_064    and ex2_sh_lvl2(29)     ) );
+r2_094:   ex2_sh16_r2_b(94)    <= not( (cp3_048    and ex2_sh_lvl2(46)     ) or (cp2_064    and ex2_sh_lvl2(30)     ) );
+r2_095:   ex2_sh16_r2_b(95)    <= not( (cp3_048    and ex2_sh_lvl2(47)     ) or (cp2_064    and ex2_sh_lvl2(31)     ) );
+
+r2_096:   ex2_sh16_r2_b(96)    <= not( (cp3_064    and ex2_sh_lvl2(32)     ) or (cp2_080    and ex2_sh_lvl2(16)     ) );
+r2_097:   ex2_sh16_r2_b(97)    <= not( (cp3_064    and ex2_sh_lvl2(33)     ) or (cp2_080    and ex2_sh_lvl2(17)     ) );
+r2_098:   ex2_sh16_r2_b(98)    <= not( (cp3_064    and ex2_sh_lvl2(34)     ) or (cp2_080    and ex2_sh_lvl2(18)     ) );
+r2_099:   ex2_sh16_r2_b(99)    <= not( (cp3_064    and ex2_sh_lvl2(35)     ) or (cp2_080    and ex2_sh_lvl2(19)     ) );
+r2_100:   ex2_sh16_r2_b(100)   <= not( (cp3_064    and ex2_sh_lvl2(36)     ) or (cp2_080    and ex2_sh_lvl2(20)     ) );
+r2_101:   ex2_sh16_r2_b(101)   <= not( (cp3_064    and ex2_sh_lvl2(37)     ) or (cp2_080    and ex2_sh_lvl2(21)     ) );
+r2_102:   ex2_sh16_r2_b(102)   <= not( (cp3_064    and ex2_sh_lvl2(38)     ) or (cp2_080    and ex2_sh_lvl2(22)     ) );
+r2_103:   ex2_sh16_r2_b(103)   <= not( (cp3_064    and ex2_sh_lvl2(39)     ) or (cp2_080    and ex2_sh_lvl2(23)     ) );
+r2_104:   ex2_sh16_r2_b(104)   <= not( (cp3_064    and ex2_sh_lvl2(40)     ) or (cp2_080    and ex2_sh_lvl2(24)     ) );
+r2_105:   ex2_sh16_r2_b(105)   <= not( (cp3_064    and ex2_sh_lvl2(41)     ) or (cp2_080    and ex2_sh_lvl2(25)     ) );
+r2_106:   ex2_sh16_r2_b(106)   <= not( (cp3_064    and ex2_sh_lvl2(42)     ) or (cp2_080    and ex2_sh_lvl2(26)     ) );
+r2_107:   ex2_sh16_r2_b(107)   <= not( (cp3_064    and ex2_sh_lvl2(43)     ) or (cp2_080    and ex2_sh_lvl2(27)     ) );
+r2_108:   ex2_sh16_r2_b(108)   <= not( (cp3_064    and ex2_sh_lvl2(44)     ) or (cp2_080    and ex2_sh_lvl2(28)     ) );
+r2_109:   ex2_sh16_r2_b(109)   <= not( (cp3_064    and ex2_sh_lvl2(45)     ) or (cp2_080    and ex2_sh_lvl2(29)     ) );
+r2_110:   ex2_sh16_r2_b(110)   <= not( (cp3_064    and ex2_sh_lvl2(46)     ) or (cp2_080    and ex2_sh_lvl2(30)     ) );
+r2_111:   ex2_sh16_r2_b(111)   <= not( (cp3_064    and ex2_sh_lvl2(47)     ) or (cp2_080    and ex2_sh_lvl2(31)     ) );
+
+r2_112:   ex2_sh16_r2_b(112)   <= not( (cp3_080    and ex2_sh_lvl2(32)     ) or (cp2_096    and ex2_sh_lvl2(16)     ) );
+r2_113:   ex2_sh16_r2_b(113)   <= not( (cp3_080    and ex2_sh_lvl2(33)     ) or (cp2_096    and ex2_sh_lvl2(17)     ) );
+r2_114:   ex2_sh16_r2_b(114)   <= not( (cp3_080    and ex2_sh_lvl2(34)     ) or (cp2_096    and ex2_sh_lvl2(18)     ) );
+r2_115:   ex2_sh16_r2_b(115)   <= not( (cp3_080    and ex2_sh_lvl2(35)     ) or (cp2_096    and ex2_sh_lvl2(19)     ) );
+r2_116:   ex2_sh16_r2_b(116)   <= not( (cp3_080    and ex2_sh_lvl2(36)     ) or (cp2_096    and ex2_sh_lvl2(20)     ) );
+r2_117:   ex2_sh16_r2_b(117)   <= not( (cp3_080    and ex2_sh_lvl2(37)     ) or (cp2_096    and ex2_sh_lvl2(21)     ) );
+r2_118:   ex2_sh16_r2_b(118)   <= not( (cp3_080    and ex2_sh_lvl2(38)     ) or (cp2_096    and ex2_sh_lvl2(22)     ) );
+r2_119:   ex2_sh16_r2_b(119)   <= not( (cp3_080    and ex2_sh_lvl2(39)     ) or (cp2_096    and ex2_sh_lvl2(23)     ) );
+r2_120:   ex2_sh16_r2_b(120)   <= not( (cp3_080    and ex2_sh_lvl2(40)     ) or (cp2_096    and ex2_sh_lvl2(24)     ) );
+r2_121:   ex2_sh16_r2_b(121)   <= not( (cp3_080    and ex2_sh_lvl2(41)     ) or (cp2_096    and ex2_sh_lvl2(25)     ) );
+r2_122:   ex2_sh16_r2_b(122)   <= not( (cp3_080    and ex2_sh_lvl2(42)     ) or (cp2_096    and ex2_sh_lvl2(26)     ) );
+r2_123:   ex2_sh16_r2_b(123)   <= not( (cp3_080    and ex2_sh_lvl2(43)     ) or (cp2_096    and ex2_sh_lvl2(27)     ) );
+r2_124:   ex2_sh16_r2_b(124)   <= not( (cp3_080    and ex2_sh_lvl2(44)     ) or (cp2_096    and ex2_sh_lvl2(28)     ) );
+r2_125:   ex2_sh16_r2_b(125)   <= not( (cp3_080    and ex2_sh_lvl2(45)     ) or (cp2_096    and ex2_sh_lvl2(29)     ) );
+r2_126:   ex2_sh16_r2_b(126)   <= not( (cp3_080    and ex2_sh_lvl2(46)     ) or (cp2_096    and ex2_sh_lvl2(30)     ) );
+r2_127:   ex2_sh16_r2_b(127)   <= not( (cp3_080    and ex2_sh_lvl2(47)     ) or (cp2_096    and ex2_sh_lvl2(31)     ) );
+
+r2_128:   ex2_sh16_r2_b(128)   <= not( (cp3_096    and ex2_sh_lvl2(32)     ) or (cp2_112    and ex2_sh_lvl2(16)     ) );
+r2_129:   ex2_sh16_r2_b(129)   <= not( (cp3_096    and ex2_sh_lvl2(33)     ) or (cp2_112    and ex2_sh_lvl2(17)     ) );
+r2_130:   ex2_sh16_r2_b(130)   <= not( (cp3_096    and ex2_sh_lvl2(34)     ) or (cp2_112    and ex2_sh_lvl2(18)     ) );
+r2_131:   ex2_sh16_r2_b(131)   <= not( (cp3_096    and ex2_sh_lvl2(35)     ) or (cp2_112    and ex2_sh_lvl2(19)     ) );
+r2_132:   ex2_sh16_r2_b(132)   <= not( (cp3_096    and ex2_sh_lvl2(36)     ) or (cp2_112    and ex2_sh_lvl2(20)     ) );
+r2_133:   ex2_sh16_r2_b(133)   <= not( (cp3_096    and ex2_sh_lvl2(37)     ) or (cp2_112    and ex2_sh_lvl2(21)     ) );
+r2_134:   ex2_sh16_r2_b(134)   <= not( (cp3_096    and ex2_sh_lvl2(38)     ) or (cp2_112    and ex2_sh_lvl2(22)     ) );
+r2_135:   ex2_sh16_r2_b(135)   <= not( (cp3_096    and ex2_sh_lvl2(39)     ) or (cp2_112    and ex2_sh_lvl2(23)     ) );
+r2_136:   ex2_sh16_r2_b(136)   <= not( (cp3_096    and ex2_sh_lvl2(40)     ) or (cp2_112    and ex2_sh_lvl2(24)     ) );
+r2_137:   ex2_sh16_r2_b(137)   <= not( (cp3_096    and ex2_sh_lvl2(41)     ) or (cp2_112    and ex2_sh_lvl2(25)     ) );
+r2_138:   ex2_sh16_r2_b(138)   <= not( (cp3_096    and ex2_sh_lvl2(42)     ) or (cp2_112    and ex2_sh_lvl2(26)     ) );
+r2_139:   ex2_sh16_r2_b(139)   <= not( (cp3_096    and ex2_sh_lvl2(43)     ) or (cp2_112    and ex2_sh_lvl2(27)     ) );
+r2_140:   ex2_sh16_r2_b(140)   <= not( (cp3_096    and ex2_sh_lvl2(44)     ) or (cp2_112    and ex2_sh_lvl2(28)     ) );
+r2_141:   ex2_sh16_r2_b(141)   <= not( (cp3_096    and ex2_sh_lvl2(45)     ) or (cp2_112    and ex2_sh_lvl2(29)     ) );
+r2_142:   ex2_sh16_r2_b(142)   <= not( (cp3_096    and ex2_sh_lvl2(46)     ) or (cp2_112    and ex2_sh_lvl2(30)     ) );
+r2_143:   ex2_sh16_r2_b(143)   <= not( (cp3_096    and ex2_sh_lvl2(47)     ) or (cp2_112    and ex2_sh_lvl2(31)     ) );
+
+r2_144:   ex2_sh16_r2_b(144)   <= not( (cp3_112    and ex2_sh_lvl2(32)     ) or (cp2_128    and ex2_sh_lvl2(16)     ) );
+r2_145:   ex2_sh16_r2_b(145)   <= not( (cp3_112    and ex2_sh_lvl2(33)     ) or (cp2_128    and ex2_sh_lvl2(17)     ) );
+r2_146:   ex2_sh16_r2_b(146)   <= not( (cp3_112    and ex2_sh_lvl2(34)     ) or (cp2_128    and ex2_sh_lvl2(18)     ) );
+r2_147:   ex2_sh16_r2_b(147)   <= not( (cp3_112    and ex2_sh_lvl2(35)     ) or (cp2_128    and ex2_sh_lvl2(19)     ) );
+r2_148:   ex2_sh16_r2_b(148)   <= not( (cp3_112    and ex2_sh_lvl2(36)     ) or (cp2_128    and ex2_sh_lvl2(20)     ) );
+r2_149:   ex2_sh16_r2_b(149)   <= not( (cp3_112    and ex2_sh_lvl2(37)     ) or (cp2_128    and ex2_sh_lvl2(21)     ) );
+r2_150:   ex2_sh16_r2_b(150)   <= not( (cp3_112    and ex2_sh_lvl2(38)     ) or (cp2_128    and ex2_sh_lvl2(22)     ) );
+r2_151:   ex2_sh16_r2_b(151)   <= not( (cp3_112    and ex2_sh_lvl2(39)     ) or (cp2_128    and ex2_sh_lvl2(23)     ) );
+r2_152:   ex2_sh16_r2_b(152)   <= not( (cp3_112    and ex2_sh_lvl2(40)     ) or (cp2_128    and ex2_sh_lvl2(24)     ) );
+r2_153:   ex2_sh16_r2_b(153)   <= not( (cp3_112    and ex2_sh_lvl2(41)     ) or (cp2_128    and ex2_sh_lvl2(25)     ) );
+r2_154:   ex2_sh16_r2_b(154)   <= not( (cp3_112    and ex2_sh_lvl2(42)     ) or (cp2_128    and ex2_sh_lvl2(26)     ) );
+r2_155:   ex2_sh16_r2_b(155)   <= not( (cp3_112    and ex2_sh_lvl2(43)     ) or (cp2_128    and ex2_sh_lvl2(27)     ) );
+r2_156:   ex2_sh16_r2_b(156)   <= not( (cp3_112    and ex2_sh_lvl2(44)     ) or (cp2_128    and ex2_sh_lvl2(28)     ) );
+r2_157:   ex2_sh16_r2_b(157)   <= not( (cp3_112    and ex2_sh_lvl2(45)     ) or (cp2_128    and ex2_sh_lvl2(29)     ) );
+r2_158:   ex2_sh16_r2_b(158)   <= not( (cp3_112    and ex2_sh_lvl2(46)     ) or (cp2_128    and ex2_sh_lvl2(30)     ) );
+r2_159:   ex2_sh16_r2_b(159)   <= not( (cp3_112    and ex2_sh_lvl2(47)     ) or (cp2_128    and ex2_sh_lvl2(31)     ) );
+
+r2_160:   ex2_sh16_r2_b(160)   <= not( (cp3_128    and ex2_sh_lvl2(32)     ) or (cp2_144    and ex2_sh_lvl2(16)     ) );
+r2_161:   ex2_sh16_r2_b(161)   <= not( (cp3_128    and ex2_sh_lvl2(33)     ) or (cp2_144    and ex2_sh_lvl2(17)     ) );
+r2_162:   ex2_sh16_r2_b(162)   <= not( (cp3_128    and ex2_sh_lvl2(34)     ) or (cp2_144    and ex2_sh_lvl2(18)     ) );
+
+r3_000:   ex2_sh16_r3_b(0)     <= not(  cp1_000    and ex2_sh_lvl2(0)        );
+r3_001:   ex2_sh16_r3_b(1)     <= not(  cp1_000    and ex2_sh_lvl2(1)        );
+r3_002:   ex2_sh16_r3_b(2)     <= not(  cp1_000    and ex2_sh_lvl2(2)        );
+r3_003:   ex2_sh16_r3_b(3)     <= not(  cp1_000    and ex2_sh_lvl2(3)        );
+r3_004:   ex2_sh16_r3_b(4)     <= not(  cp1_000    and ex2_sh_lvl2(4)        );
+r3_005:   ex2_sh16_r3_b(5)     <= not(  cp1_000    and ex2_sh_lvl2(5)        );
+r3_006:   ex2_sh16_r3_b(6)     <= not(  cp1_000    and ex2_sh_lvl2(6)        );
+r3_007:   ex2_sh16_r3_b(7)     <= not(  cp1_000    and ex2_sh_lvl2(7)        );
+r3_008:   ex2_sh16_r3_b(8)     <= not(  cp1_000    and ex2_sh_lvl2(8)        );
+r3_009:   ex2_sh16_r3_b(9)     <= not(  cp1_000    and ex2_sh_lvl2(9)        );
+r3_010:   ex2_sh16_r3_b(10)    <= not(  cp1_000    and ex2_sh_lvl2(10)       );
+r3_011:   ex2_sh16_r3_b(11)    <= not(  cp1_000    and ex2_sh_lvl2(11)       );
+r3_012:   ex2_sh16_r3_b(12)    <= not(  cp1_000    and ex2_sh_lvl2(12)       );
+r3_013:   ex2_sh16_r3_b(13)    <= not(  cp1_000    and ex2_sh_lvl2(13)       );
+r3_014:   ex2_sh16_r3_b(14)    <= not(  cp1_000    and ex2_sh_lvl2(14)       );
+r3_015:   ex2_sh16_r3_b(15)    <= not(  cp1_000    and ex2_sh_lvl2(15)       );
+
+r3_016:   ex2_sh16_r3_b(16)    <= not(  cp1_016    and ex2_sh_lvl2(0)        );
+r3_017:   ex2_sh16_r3_b(17)    <= not(  cp1_016    and ex2_sh_lvl2(1)        );
+r3_018:   ex2_sh16_r3_b(18)    <= not(  cp1_016    and ex2_sh_lvl2(2)        );
+r3_019:   ex2_sh16_r3_b(19)    <= not(  cp1_016    and ex2_sh_lvl2(3)        );
+r3_020:   ex2_sh16_r3_b(20)    <= not(  cp1_016    and ex2_sh_lvl2(4)        );
+r3_021:   ex2_sh16_r3_b(21)    <= not(  cp1_016    and ex2_sh_lvl2(5)        );
+r3_022:   ex2_sh16_r3_b(22)    <= not(  cp1_016    and ex2_sh_lvl2(6)        );
+r3_023:   ex2_sh16_r3_b(23)    <= not(  cp1_016    and ex2_sh_lvl2(7)        );
+r3_024:   ex2_sh16_r3_b(24)    <= not(  cp1_016    and ex2_sh_lvl2(8)        );
+r3_025:   ex2_sh16_r3_b(25)    <= not(  cp1_016    and ex2_sh_lvl2(9)        );
+r3_026:   ex2_sh16_r3_b(26)    <= not(  cp1_016    and ex2_sh_lvl2(10)       );
+r3_027:   ex2_sh16_r3_b(27)    <= not(  cp1_016    and ex2_sh_lvl2(11)       );
+r3_028:   ex2_sh16_r3_b(28)    <= not(  cp1_016    and ex2_sh_lvl2(12)       );
+r3_029:   ex2_sh16_r3_b(29)    <= not(  cp1_016    and ex2_sh_lvl2(13)       );
+r3_030:   ex2_sh16_r3_b(30)    <= not(  cp1_016    and ex2_sh_lvl2(14)       );
+r3_031:   ex2_sh16_r3_b(31)    <= not(  cp1_016    and ex2_sh_lvl2(15)       );
+
+r3_032:   ex2_sh16_r3_b(32)    <= not(  cp1_032    and ex2_sh_lvl2(0)        );
+r3_033:   ex2_sh16_r3_b(33)    <= not(  cp1_032    and ex2_sh_lvl2(1)        );
+r3_034:   ex2_sh16_r3_b(34)    <= not(  cp1_032    and ex2_sh_lvl2(2)        );
+r3_035:   ex2_sh16_r3_b(35)    <= not(  cp1_032    and ex2_sh_lvl2(3)        );
+r3_036:   ex2_sh16_r3_b(36)    <= not(  cp1_032    and ex2_sh_lvl2(4)        );
+r3_037:   ex2_sh16_r3_b(37)    <= not(  cp1_032    and ex2_sh_lvl2(5)        );
+r3_038:   ex2_sh16_r3_b(38)    <= not(  cp1_032    and ex2_sh_lvl2(6)        );
+r3_039:   ex2_sh16_r3_b(39)    <= not(  cp1_032    and ex2_sh_lvl2(7)        );
+r3_040:   ex2_sh16_r3_b(40)    <= not(  cp1_032    and ex2_sh_lvl2(8)        );
+r3_041:   ex2_sh16_r3_b(41)    <= not(  cp1_032    and ex2_sh_lvl2(9)        );
+r3_042:   ex2_sh16_r3_b(42)    <= not(  cp1_032    and ex2_sh_lvl2(10)       );
+r3_043:   ex2_sh16_r3_b(43)    <= not(  cp1_032    and ex2_sh_lvl2(11)       );
+r3_044:   ex2_sh16_r3_b(44)    <= not(  cp1_032    and ex2_sh_lvl2(12)       );
+r3_045:   ex2_sh16_r3_b(45)    <= not(  cp1_032    and ex2_sh_lvl2(13)       );
+r3_046:   ex2_sh16_r3_b(46)    <= not(  cp1_032    and ex2_sh_lvl2(14)       );
+r3_047:   ex2_sh16_r3_b(47)    <= not(  cp1_032    and ex2_sh_lvl2(15)       );
+
+r3_048:   ex2_sh16_r3_b(48)    <= not(  cp1_048    and ex2_sh_lvl2(0)        );
+r3_049:   ex2_sh16_r3_b(49)    <= not(  cp1_048    and ex2_sh_lvl2(1)        );
+r3_050:   ex2_sh16_r3_b(50)    <= not(  cp1_048    and ex2_sh_lvl2(2)        );
+r3_051:   ex2_sh16_r3_b(51)    <= not(  cp1_048    and ex2_sh_lvl2(3)        );
+r3_052:   ex2_sh16_r3_b(52)    <= not(  cp1_048    and ex2_sh_lvl2(4)        );
+r3_053:   ex2_sh16_r3_b(53)    <= not(  cp1_048    and ex2_sh_lvl2(5)        );
+r3_054:   ex2_sh16_r3_b(54)    <= not(  cp1_048    and ex2_sh_lvl2(6)        );
+r3_055:   ex2_sh16_r3_b(55)    <= not(  cp1_048    and ex2_sh_lvl2(7)        );
+r3_056:   ex2_sh16_r3_b(56)    <= not(  cp1_048    and ex2_sh_lvl2(8)        );
+r3_057:   ex2_sh16_r3_b(57)    <= not(  cp1_048    and ex2_sh_lvl2(9)        );
+r3_058:   ex2_sh16_r3_b(58)    <= not(  cp1_048    and ex2_sh_lvl2(10)       );
+r3_059:   ex2_sh16_r3_b(59)    <= not(  cp1_048    and ex2_sh_lvl2(11)       );
+r3_060:   ex2_sh16_r3_b(60)    <= not(  cp1_048    and ex2_sh_lvl2(12)       );
+r3_061:   ex2_sh16_r3_b(61)    <= not(  cp1_048    and ex2_sh_lvl2(13)       );
+r3_062:   ex2_sh16_r3_b(62)    <= not(  cp1_048    and ex2_sh_lvl2(14)       );
+r3_063:   ex2_sh16_r3_b(63)    <= not(  cp1_048    and ex2_sh_lvl2(15)       );
+
+r3_064:   ex2_sh16_r3_b(64)    <= not(  cp1_064    and ex2_sh_lvl2(0)        );
+r3_065:   ex2_sh16_r3_b(65)    <= not(  cp1_064    and ex2_sh_lvl2(1)        );
+r3_066:   ex2_sh16_r3_b(66)    <= not(  cp1_064    and ex2_sh_lvl2(2)        );
+r3_067:   ex2_sh16_r3_b(67)    <= not(  cp1_064    and ex2_sh_lvl2(3)        );
+r3_068:   ex2_sh16_r3_b(68)    <= not(  cp1_064    and ex2_sh_lvl2(4)        );
+r3_069:   ex2_sh16_r3_b(69)    <= not(  cp1_064    and ex2_sh_lvl2(5)        );
+r3_070:   ex2_sh16_r3_b(70)    <= not(  cp1_064    and ex2_sh_lvl2(6)        );
+r3_071:   ex2_sh16_r3_b(71)    <= not(  cp1_064    and ex2_sh_lvl2(7)        );
+r3_072:   ex2_sh16_r3_b(72)    <= not(  cp1_064    and ex2_sh_lvl2(8)        );
+r3_073:   ex2_sh16_r3_b(73)    <= not(  cp1_064    and ex2_sh_lvl2(9)        );
+r3_074:   ex2_sh16_r3_b(74)    <= not(  cp1_064    and ex2_sh_lvl2(10)       );
+r3_075:   ex2_sh16_r3_b(75)    <= not(  cp1_064    and ex2_sh_lvl2(11)       );
+r3_076:   ex2_sh16_r3_b(76)    <= not(  cp1_064    and ex2_sh_lvl2(12)       );
+r3_077:   ex2_sh16_r3_b(77)    <= not(  cp1_064    and ex2_sh_lvl2(13)       );
+r3_078:   ex2_sh16_r3_b(78)    <= not(  cp1_064    and ex2_sh_lvl2(14)       );
+r3_079:   ex2_sh16_r3_b(79)    <= not(  cp1_064    and ex2_sh_lvl2(15)       );
+
+r3_080:   ex2_sh16_r3_b(80)    <= not(  cp1_080    and ex2_sh_lvl2(0)        );
+r3_081:   ex2_sh16_r3_b(81)    <= not(  cp1_080    and ex2_sh_lvl2(1)        );
+r3_082:   ex2_sh16_r3_b(82)    <= not(  cp1_080    and ex2_sh_lvl2(2)        );
+r3_083:   ex2_sh16_r3_b(83)    <= not(  cp1_080    and ex2_sh_lvl2(3)        );
+r3_084:   ex2_sh16_r3_b(84)    <= not(  cp1_080    and ex2_sh_lvl2(4)        );
+r3_085:   ex2_sh16_r3_b(85)    <= not(  cp1_080    and ex2_sh_lvl2(5)        );
+r3_086:   ex2_sh16_r3_b(86)    <= not(  cp1_080    and ex2_sh_lvl2(6)        );
+r3_087:   ex2_sh16_r3_b(87)    <= not(  cp1_080    and ex2_sh_lvl2(7)        );
+r3_088:   ex2_sh16_r3_b(88)    <= not(  cp1_080    and ex2_sh_lvl2(8)        );
+r3_089:   ex2_sh16_r3_b(89)    <= not(  cp1_080    and ex2_sh_lvl2(9)        );
+r3_090:   ex2_sh16_r3_b(90)    <= not(  cp1_080    and ex2_sh_lvl2(10)       );
+r3_091:   ex2_sh16_r3_b(91)    <= not(  cp1_080    and ex2_sh_lvl2(11)       );
+r3_092:   ex2_sh16_r3_b(92)    <= not(  cp1_080    and ex2_sh_lvl2(12)       );
+r3_093:   ex2_sh16_r3_b(93)    <= not(  cp1_080    and ex2_sh_lvl2(13)       );
+r3_094:   ex2_sh16_r3_b(94)    <= not(  cp1_080    and ex2_sh_lvl2(14)       );
+r3_095:   ex2_sh16_r3_b(95)    <= not(  cp1_080    and ex2_sh_lvl2(15)       );
+
+r3_096:   ex2_sh16_r3_b(96)    <= not(  cp1_096    and ex2_sh_lvl2(0)      ) ;
+r3_097:   ex2_sh16_r3_b(97)    <= not(  cp1_096    and ex2_sh_lvl2(1)      ) ;
+r3_098:   ex2_sh16_r3_b(98)    <= not(  cp1_096    and ex2_sh_lvl2(2)      ) ;
+r3_099:   ex2_sh16_r3_b(99)    <= not( (cp1_096    and ex2_sh_lvl2(3)      ) or (cp1_spc      and ex2_special(99)     ) );
+r3_100:   ex2_sh16_r3_b(100)   <= not( (cp1_096    and ex2_sh_lvl2(4)      ) or (cp1_spc      and ex2_special(100)    ) );
+r3_101:   ex2_sh16_r3_b(101)   <= not( (cp1_096    and ex2_sh_lvl2(5)      ) or (cp1_spc      and ex2_special(101)    ) );
+r3_102:   ex2_sh16_r3_b(102)   <= not( (cp1_096    and ex2_sh_lvl2(6)      ) or (cp1_spc      and ex2_special(102)    ) );
+r3_103:   ex2_sh16_r3_b(103)   <= not( (cp1_096    and ex2_sh_lvl2(7)      ) or (cp1_spc      and ex2_special(103)    ) );
+r3_104:   ex2_sh16_r3_b(104)   <= not( (cp1_096    and ex2_sh_lvl2(8)      ) or (cp1_spc      and ex2_special(104)    ) );
+r3_105:   ex2_sh16_r3_b(105)   <= not( (cp1_096    and ex2_sh_lvl2(9)      ) or (cp1_spc      and ex2_special(105)    ) );
+r3_106:   ex2_sh16_r3_b(106)   <= not( (cp1_096    and ex2_sh_lvl2(10)     ) or (cp1_spc      and ex2_special(106)    ) );
+r3_107:   ex2_sh16_r3_b(107)   <= not( (cp1_096    and ex2_sh_lvl2(11)     ) or (cp1_spc      and ex2_special(107)    ) );
+r3_108:   ex2_sh16_r3_b(108)   <= not( (cp1_096    and ex2_sh_lvl2(12)     ) or (cp1_spc      and ex2_special(108)    ) );
+r3_109:   ex2_sh16_r3_b(109)   <= not( (cp1_096    and ex2_sh_lvl2(13)     ) or (cp1_spc      and ex2_special(109)    ) );
+r3_110:   ex2_sh16_r3_b(110)   <= not( (cp1_096    and ex2_sh_lvl2(14)     ) or (cp1_spc      and ex2_special(110)    ) );
+r3_111:   ex2_sh16_r3_b(111)   <= not( (cp1_096    and ex2_sh_lvl2(15)     ) or (cp1_spc      and ex2_special(111)    ) );
+
+r3_112:   ex2_sh16_r3_b(112)   <= not( (cp1_112    and ex2_sh_lvl2(0)      ) or (cp2_spc      and ex2_special(112)    ) );
+r3_113:   ex2_sh16_r3_b(113)   <= not( (cp1_112    and ex2_sh_lvl2(1)      ) or (cp2_spc      and ex2_special(113)    ) );
+r3_114:   ex2_sh16_r3_b(114)   <= not( (cp1_112    and ex2_sh_lvl2(2)      ) or (cp2_spc      and ex2_special(114)    ) );
+r3_115:   ex2_sh16_r3_b(115)   <= not( (cp1_112    and ex2_sh_lvl2(3)      ) or (cp2_spc      and ex2_special(115)    ) );
+r3_116:   ex2_sh16_r3_b(116)   <= not( (cp1_112    and ex2_sh_lvl2(4)      ) or (cp2_spc      and ex2_special(116)    ) );
+r3_117:   ex2_sh16_r3_b(117)   <= not( (cp1_112    and ex2_sh_lvl2(5)      ) or (cp2_spc      and ex2_special(117)    ) );
+r3_118:   ex2_sh16_r3_b(118)   <= not( (cp1_112    and ex2_sh_lvl2(6)      ) or (cp2_spc      and ex2_special(118)    ) );
+r3_119:   ex2_sh16_r3_b(119)   <= not( (cp1_112    and ex2_sh_lvl2(7)      ) or (cp2_spc      and ex2_special(119)    ) );
+r3_120:   ex2_sh16_r3_b(120)   <= not( (cp1_112    and ex2_sh_lvl2(8)      ) or (cp2_spc      and ex2_special(120)    ) );
+r3_121:   ex2_sh16_r3_b(121)   <= not( (cp1_112    and ex2_sh_lvl2(9)      ) or (cp2_spc      and ex2_special(121)    ) );
+r3_122:   ex2_sh16_r3_b(122)   <= not( (cp1_112    and ex2_sh_lvl2(10)     ) or (cp2_spc      and ex2_special(122)    ) );
+r3_123:   ex2_sh16_r3_b(123)   <= not( (cp1_112    and ex2_sh_lvl2(11)     ) or (cp2_spc      and ex2_special(123)    ) );
+r3_124:   ex2_sh16_r3_b(124)   <= not( (cp1_112    and ex2_sh_lvl2(12)     ) or (cp2_spc      and ex2_special(124)    ) );
+r3_125:   ex2_sh16_r3_b(125)   <= not( (cp1_112    and ex2_sh_lvl2(13)     ) or (cp2_spc      and ex2_special(125)    ) );
+r3_126:   ex2_sh16_r3_b(126)   <= not( (cp1_112    and ex2_sh_lvl2(14)     ) or (cp2_spc      and ex2_special(126)    ) );
+r3_127:   ex2_sh16_r3_b(127)   <= not( (cp1_112    and ex2_sh_lvl2(15)     ) or (cp2_spc      and ex2_special(127)    ) );
+
+r3_128:   ex2_sh16_r3_b(128)   <= not( (cp1_128    and ex2_sh_lvl2(0)      ) or (cp3_spc      and ex2_special(128)    ) );
+r3_129:   ex2_sh16_r3_b(129)   <= not( (cp1_128    and ex2_sh_lvl2(1)      ) or (cp3_spc      and ex2_special(129)    ) );
+r3_130:   ex2_sh16_r3_b(130)   <= not( (cp1_128    and ex2_sh_lvl2(2)      ) or (cp3_spc      and ex2_special(130)    ) );
+r3_131:   ex2_sh16_r3_b(131)   <= not( (cp1_128    and ex2_sh_lvl2(3)      ) or (cp3_spc      and ex2_special(131)    ) );
+r3_132:   ex2_sh16_r3_b(132)   <= not( (cp1_128    and ex2_sh_lvl2(4)      ) or (cp3_spc      and ex2_special(132)    ) );
+r3_133:   ex2_sh16_r3_b(133)   <= not( (cp1_128    and ex2_sh_lvl2(5)      ) or (cp3_spc      and ex2_special(133)    ) );
+r3_134:   ex2_sh16_r3_b(134)   <= not( (cp1_128    and ex2_sh_lvl2(6)      ) or (cp3_spc      and ex2_special(134)    ) );
+r3_135:   ex2_sh16_r3_b(135)   <= not( (cp1_128    and ex2_sh_lvl2(7)      ) or (cp3_spc      and ex2_special(135)    ) );
+r3_136:   ex2_sh16_r3_b(136)   <= not( (cp1_128    and ex2_sh_lvl2(8)      ) or (cp3_spc      and ex2_special(136)    ) );
+r3_137:   ex2_sh16_r3_b(137)   <= not( (cp1_128    and ex2_sh_lvl2(9)      ) or (cp3_spc      and ex2_special(137)    ) );
+r3_138:   ex2_sh16_r3_b(138)   <= not( (cp1_128    and ex2_sh_lvl2(10)     ) or (cp3_spc      and ex2_special(138)    ) );
+r3_139:   ex2_sh16_r3_b(139)   <= not( (cp1_128    and ex2_sh_lvl2(11)     ) or (cp3_spc      and ex2_special(139)    ) );
+r3_140:   ex2_sh16_r3_b(140)   <= not( (cp1_128    and ex2_sh_lvl2(12)     ) or (cp3_spc      and ex2_special(140)    ) );
+r3_141:   ex2_sh16_r3_b(141)   <= not( (cp1_128    and ex2_sh_lvl2(13)     ) or (cp3_spc      and ex2_special(141)    ) );
+r3_142:   ex2_sh16_r3_b(142)   <= not( (cp1_128    and ex2_sh_lvl2(14)     ) or (cp3_spc      and ex2_special(142)    ) );
+r3_143:   ex2_sh16_r3_b(143)   <= not( (cp1_128    and ex2_sh_lvl2(15)     ) or (cp3_spc      and ex2_special(143)    ) );
+
+r3_144:   ex2_sh16_r3_b(144)   <= not( (cp1_144    and ex2_sh_lvl2(0)      ) or (cp4_spc      and ex2_special(144)    ) );
+r3_145:   ex2_sh16_r3_b(145)   <= not( (cp1_144    and ex2_sh_lvl2(1)      ) or (cp4_spc      and ex2_special(145)    ) );
+r3_146:   ex2_sh16_r3_b(146)   <= not( (cp1_144    and ex2_sh_lvl2(2)      ) or (cp4_spc      and ex2_special(146)    ) );
+r3_147:   ex2_sh16_r3_b(147)   <= not( (cp1_144    and ex2_sh_lvl2(3)      ) or (cp4_spc      and ex2_special(147)    ) );
+r3_148:   ex2_sh16_r3_b(148)   <= not( (cp1_144    and ex2_sh_lvl2(4)      ) or (cp4_spc      and ex2_special(148)    ) );
+r3_149:   ex2_sh16_r3_b(149)   <= not( (cp1_144    and ex2_sh_lvl2(5)      ) or (cp4_spc      and ex2_special(149)    ) );
+r3_150:   ex2_sh16_r3_b(150)   <= not( (cp1_144    and ex2_sh_lvl2(6)      ) or (cp4_spc      and ex2_special(150)    ) );
+r3_151:   ex2_sh16_r3_b(151)   <= not( (cp1_144    and ex2_sh_lvl2(7)      ) or (cp4_spc      and ex2_special(151)    ) );
+r3_152:   ex2_sh16_r3_b(152)   <= not( (cp1_144    and ex2_sh_lvl2(8)      ) or (cp4_spc      and ex2_special(152)    ) );
+r3_153:   ex2_sh16_r3_b(153)   <= not( (cp1_144    and ex2_sh_lvl2(9)      ) or (cp4_spc      and ex2_special(153)    ) );
+r3_154:   ex2_sh16_r3_b(154)   <= not( (cp1_144    and ex2_sh_lvl2(10)     ) or (cp4_spc      and ex2_special(154)    ) );
+r3_155:   ex2_sh16_r3_b(155)   <= not( (cp1_144    and ex2_sh_lvl2(11)     ) or (cp4_spc      and ex2_special(155)    ) );
+r3_156:   ex2_sh16_r3_b(156)   <= not( (cp1_144    and ex2_sh_lvl2(12)     ) or (cp4_spc      and ex2_special(156)    ) );
+r3_157:   ex2_sh16_r3_b(157)   <= not( (cp1_144    and ex2_sh_lvl2(13)     ) or (cp4_spc      and ex2_special(157)    ) );
+r3_158:   ex2_sh16_r3_b(158)   <= not( (cp1_144    and ex2_sh_lvl2(14)     ) or (cp4_spc      and ex2_special(158)    ) );
+r3_159:   ex2_sh16_r3_b(159)   <= not( (cp1_144    and ex2_sh_lvl2(15)     ) or (cp4_spc      and ex2_special(159)    ) );
+
+r3_160:   ex2_sh16_r3_b(160)   <= not( (cp1_160    and ex2_sh_lvl2(0)      ) or (cp5_spc      and ex2_special(160)    ) );
+r3_161:   ex2_sh16_r3_b(161)   <= not( (cp1_160    and ex2_sh_lvl2(1)      ) or (cp5_spc      and ex2_special(161)    ) );
+r3_162:   ex2_sh16_r3_b(162)   <= not( (cp1_160    and ex2_sh_lvl2(2)      ) or (cp5_spc      and ex2_special(162)    ) );
+
+
+o_000:    ex2_sh_lvl3(0)       <= not( ex2_sh16_r1_b(0)     and ex2_sh16_r2_b(0)     and ex2_sh16_r3_b(0)     );
+o_001:    ex2_sh_lvl3(1)       <= not( ex2_sh16_r1_b(1)     and ex2_sh16_r2_b(1)     and ex2_sh16_r3_b(1)     );
+o_002:    ex2_sh_lvl3(2)       <= not( ex2_sh16_r1_b(2)     and ex2_sh16_r2_b(2)     and ex2_sh16_r3_b(2)     );
+o_003:    ex2_sh_lvl3(3)       <= not( ex2_sh16_r1_b(3)     and ex2_sh16_r2_b(3)     and ex2_sh16_r3_b(3)     );
+o_004:    ex2_sh_lvl3(4)       <= not( ex2_sh16_r1_b(4)     and ex2_sh16_r2_b(4)     and ex2_sh16_r3_b(4)     );
+o_005:    ex2_sh_lvl3(5)       <= not( ex2_sh16_r1_b(5)     and ex2_sh16_r2_b(5)     and ex2_sh16_r3_b(5)     );
+o_006:    ex2_sh_lvl3(6)       <= not( ex2_sh16_r1_b(6)     and ex2_sh16_r2_b(6)     and ex2_sh16_r3_b(6)     );
+o_007:    ex2_sh_lvl3(7)       <= not( ex2_sh16_r1_b(7)     and ex2_sh16_r2_b(7)     and ex2_sh16_r3_b(7)     );
+o_008:    ex2_sh_lvl3(8)       <= not( ex2_sh16_r1_b(8)     and ex2_sh16_r2_b(8)     and ex2_sh16_r3_b(8)     );
+o_009:    ex2_sh_lvl3(9)       <= not( ex2_sh16_r1_b(9)     and ex2_sh16_r2_b(9)     and ex2_sh16_r3_b(9)     );
+o_010:    ex2_sh_lvl3(10)      <= not( ex2_sh16_r1_b(10)    and ex2_sh16_r2_b(10)    and ex2_sh16_r3_b(10)    );
+o_011:    ex2_sh_lvl3(11)      <= not( ex2_sh16_r1_b(11)    and ex2_sh16_r2_b(11)    and ex2_sh16_r3_b(11)    );
+o_012:    ex2_sh_lvl3(12)      <= not( ex2_sh16_r1_b(12)    and ex2_sh16_r2_b(12)    and ex2_sh16_r3_b(12)    );
+o_013:    ex2_sh_lvl3(13)      <= not( ex2_sh16_r1_b(13)    and ex2_sh16_r2_b(13)    and ex2_sh16_r3_b(13)    );
+o_014:    ex2_sh_lvl3(14)      <= not( ex2_sh16_r1_b(14)    and ex2_sh16_r2_b(14)    and ex2_sh16_r3_b(14)    );
+o_015:    ex2_sh_lvl3(15)      <= not( ex2_sh16_r1_b(15)    and ex2_sh16_r2_b(15)    and ex2_sh16_r3_b(15)    );
+o_016:    ex2_sh_lvl3(16)      <= not( ex2_sh16_r1_b(16)    and ex2_sh16_r2_b(16)    and ex2_sh16_r3_b(16)    );
+o_017:    ex2_sh_lvl3(17)      <= not( ex2_sh16_r1_b(17)    and ex2_sh16_r2_b(17)    and ex2_sh16_r3_b(17)    );
+o_018:    ex2_sh_lvl3(18)      <= not( ex2_sh16_r1_b(18)    and ex2_sh16_r2_b(18)    and ex2_sh16_r3_b(18)    );
+o_019:    ex2_sh_lvl3(19)      <= not( ex2_sh16_r1_b(19)    and ex2_sh16_r2_b(19)    and ex2_sh16_r3_b(19)    );
+o_020:    ex2_sh_lvl3(20)      <= not( ex2_sh16_r1_b(20)    and ex2_sh16_r2_b(20)    and ex2_sh16_r3_b(20)    );
+o_021:    ex2_sh_lvl3(21)      <= not( ex2_sh16_r1_b(21)    and ex2_sh16_r2_b(21)    and ex2_sh16_r3_b(21)    );
+o_022:    ex2_sh_lvl3(22)      <= not( ex2_sh16_r1_b(22)    and ex2_sh16_r2_b(22)    and ex2_sh16_r3_b(22)    );
+o_023:    ex2_sh_lvl3(23)      <= not( ex2_sh16_r1_b(23)    and ex2_sh16_r2_b(23)    and ex2_sh16_r3_b(23)    );
+o_024:    ex2_sh_lvl3(24)      <= not( ex2_sh16_r1_b(24)    and ex2_sh16_r2_b(24)    and ex2_sh16_r3_b(24)    );
+o_025:    ex2_sh_lvl3(25)      <= not( ex2_sh16_r1_b(25)    and ex2_sh16_r2_b(25)    and ex2_sh16_r3_b(25)    );
+o_026:    ex2_sh_lvl3(26)      <= not( ex2_sh16_r1_b(26)    and ex2_sh16_r2_b(26)    and ex2_sh16_r3_b(26)    );
+o_027:    ex2_sh_lvl3(27)      <= not( ex2_sh16_r1_b(27)    and ex2_sh16_r2_b(27)    and ex2_sh16_r3_b(27)    );
+o_028:    ex2_sh_lvl3(28)      <= not( ex2_sh16_r1_b(28)    and ex2_sh16_r2_b(28)    and ex2_sh16_r3_b(28)    );
+o_029:    ex2_sh_lvl3(29)      <= not( ex2_sh16_r1_b(29)    and ex2_sh16_r2_b(29)    and ex2_sh16_r3_b(29)    );
+o_030:    ex2_sh_lvl3(30)      <= not( ex2_sh16_r1_b(30)    and ex2_sh16_r2_b(30)    and ex2_sh16_r3_b(30)    );
+o_031:    ex2_sh_lvl3(31)      <= not( ex2_sh16_r1_b(31)    and ex2_sh16_r2_b(31)    and ex2_sh16_r3_b(31)    );
+o_032:    ex2_sh_lvl3(32)      <= not( ex2_sh16_r1_b(32)    and ex2_sh16_r2_b(32)    and ex2_sh16_r3_b(32)    );
+o_033:    ex2_sh_lvl3(33)      <= not( ex2_sh16_r1_b(33)    and ex2_sh16_r2_b(33)    and ex2_sh16_r3_b(33)    );
+o_034:    ex2_sh_lvl3(34)      <= not( ex2_sh16_r1_b(34)    and ex2_sh16_r2_b(34)    and ex2_sh16_r3_b(34)    );
+o_035:    ex2_sh_lvl3(35)      <= not( ex2_sh16_r1_b(35)    and ex2_sh16_r2_b(35)    and ex2_sh16_r3_b(35)    );
+o_036:    ex2_sh_lvl3(36)      <= not( ex2_sh16_r1_b(36)    and ex2_sh16_r2_b(36)    and ex2_sh16_r3_b(36)    );
+o_037:    ex2_sh_lvl3(37)      <= not( ex2_sh16_r1_b(37)    and ex2_sh16_r2_b(37)    and ex2_sh16_r3_b(37)    );
+o_038:    ex2_sh_lvl3(38)      <= not( ex2_sh16_r1_b(38)    and ex2_sh16_r2_b(38)    and ex2_sh16_r3_b(38)    );
+o_039:    ex2_sh_lvl3(39)      <= not( ex2_sh16_r1_b(39)    and ex2_sh16_r2_b(39)    and ex2_sh16_r3_b(39)    );
+o_040:    ex2_sh_lvl3(40)      <= not( ex2_sh16_r1_b(40)    and ex2_sh16_r2_b(40)    and ex2_sh16_r3_b(40)    );
+o_041:    ex2_sh_lvl3(41)      <= not( ex2_sh16_r1_b(41)    and ex2_sh16_r2_b(41)    and ex2_sh16_r3_b(41)    );
+o_042:    ex2_sh_lvl3(42)      <= not( ex2_sh16_r1_b(42)    and ex2_sh16_r2_b(42)    and ex2_sh16_r3_b(42)    );
+o_043:    ex2_sh_lvl3(43)      <= not( ex2_sh16_r1_b(43)    and ex2_sh16_r2_b(43)    and ex2_sh16_r3_b(43)    );
+o_044:    ex2_sh_lvl3(44)      <= not( ex2_sh16_r1_b(44)    and ex2_sh16_r2_b(44)    and ex2_sh16_r3_b(44)    );
+o_045:    ex2_sh_lvl3(45)      <= not( ex2_sh16_r1_b(45)    and ex2_sh16_r2_b(45)    and ex2_sh16_r3_b(45)    );
+o_046:    ex2_sh_lvl3(46)      <= not( ex2_sh16_r1_b(46)    and ex2_sh16_r2_b(46)    and ex2_sh16_r3_b(46)    );
+o_047:    ex2_sh_lvl3(47)      <= not( ex2_sh16_r1_b(47)    and ex2_sh16_r2_b(47)    and ex2_sh16_r3_b(47)    );
+o_048:    ex2_sh_lvl3(48)      <= not( ex2_sh16_r1_b(48)    and ex2_sh16_r2_b(48)    and ex2_sh16_r3_b(48)    );
+o_049:    ex2_sh_lvl3(49)      <= not( ex2_sh16_r1_b(49)    and ex2_sh16_r2_b(49)    and ex2_sh16_r3_b(49)    );
+o_050:    ex2_sh_lvl3(50)      <= not( ex2_sh16_r1_b(50)    and ex2_sh16_r2_b(50)    and ex2_sh16_r3_b(50)    );
+o_051:    ex2_sh_lvl3(51)      <= not( ex2_sh16_r1_b(51)    and ex2_sh16_r2_b(51)    and ex2_sh16_r3_b(51)    );
+o_052:    ex2_sh_lvl3(52)      <= not( ex2_sh16_r1_b(52)    and ex2_sh16_r2_b(52)    and ex2_sh16_r3_b(52)    );
+o_053:    ex2_sh_lvl3(53)      <= not( ex2_sh16_r1_b(53)    and ex2_sh16_r2_b(53)    and ex2_sh16_r3_b(53)    );
+o_054:    ex2_sh_lvl3(54)      <= not( ex2_sh16_r1_b(54)    and ex2_sh16_r2_b(54)    and ex2_sh16_r3_b(54)    );
+o_055:    ex2_sh_lvl3(55)      <= not( ex2_sh16_r1_b(55)    and ex2_sh16_r2_b(55)    and ex2_sh16_r3_b(55)    );
+o_056:    ex2_sh_lvl3(56)      <= not( ex2_sh16_r1_b(56)    and ex2_sh16_r2_b(56)    and ex2_sh16_r3_b(56)    );
+o_057:    ex2_sh_lvl3(57)      <= not( ex2_sh16_r1_b(57)    and ex2_sh16_r2_b(57)    and ex2_sh16_r3_b(57)    );
+o_058:    ex2_sh_lvl3(58)      <= not( ex2_sh16_r1_b(58)    and ex2_sh16_r2_b(58)    and ex2_sh16_r3_b(58)    );
+o_059:    ex2_sh_lvl3(59)      <= not( ex2_sh16_r1_b(59)    and ex2_sh16_r2_b(59)    and ex2_sh16_r3_b(59)    );
+o_060:    ex2_sh_lvl3(60)      <= not( ex2_sh16_r1_b(60)    and ex2_sh16_r2_b(60)    and ex2_sh16_r3_b(60)    );
+o_061:    ex2_sh_lvl3(61)      <= not( ex2_sh16_r1_b(61)    and ex2_sh16_r2_b(61)    and ex2_sh16_r3_b(61)    );
+o_062:    ex2_sh_lvl3(62)      <= not( ex2_sh16_r1_b(62)    and ex2_sh16_r2_b(62)    and ex2_sh16_r3_b(62)    );
+o_063:    ex2_sh_lvl3(63)      <= not( ex2_sh16_r1_b(63)    and ex2_sh16_r2_b(63)    and ex2_sh16_r3_b(63)    );
+o_064:    ex2_sh_lvl3(64)      <= not( ex2_sh16_r1_b(64)    and ex2_sh16_r2_b(64)    and ex2_sh16_r3_b(64)    );
+o_065:    ex2_sh_lvl3(65)      <= not( ex2_sh16_r1_b(65)    and ex2_sh16_r2_b(65)    and ex2_sh16_r3_b(65)    );
+o_066:    ex2_sh_lvl3(66)      <= not( ex2_sh16_r1_b(66)    and ex2_sh16_r2_b(66)    and ex2_sh16_r3_b(66)    );
+o_067:    ex2_sh_lvl3(67)      <= not( ex2_sh16_r1_b(67)    and ex2_sh16_r2_b(67)    and ex2_sh16_r3_b(67)    );
+o_068:    ex2_sh_lvl3(68)      <= not( ex2_sh16_r1_b(68)    and ex2_sh16_r2_b(68)    and ex2_sh16_r3_b(68)    );
+o_069:    ex2_sh_lvl3(69)      <= not( ex2_sh16_r1_b(69)    and ex2_sh16_r2_b(69)    and ex2_sh16_r3_b(69)    );
+o_070:    ex2_sh_lvl3(70)      <= not( ex2_sh16_r1_b(70)    and ex2_sh16_r2_b(70)    and ex2_sh16_r3_b(70)    );
+o_071:    ex2_sh_lvl3(71)      <= not( ex2_sh16_r1_b(71)    and ex2_sh16_r2_b(71)    and ex2_sh16_r3_b(71)    );
+o_072:    ex2_sh_lvl3(72)      <= not( ex2_sh16_r1_b(72)    and ex2_sh16_r2_b(72)    and ex2_sh16_r3_b(72)    );
+o_073:    ex2_sh_lvl3(73)      <= not( ex2_sh16_r1_b(73)    and ex2_sh16_r2_b(73)    and ex2_sh16_r3_b(73)    );
+o_074:    ex2_sh_lvl3(74)      <= not( ex2_sh16_r1_b(74)    and ex2_sh16_r2_b(74)    and ex2_sh16_r3_b(74)    );
+o_075:    ex2_sh_lvl3(75)      <= not( ex2_sh16_r1_b(75)    and ex2_sh16_r2_b(75)    and ex2_sh16_r3_b(75)    );
+o_076:    ex2_sh_lvl3(76)      <= not( ex2_sh16_r1_b(76)    and ex2_sh16_r2_b(76)    and ex2_sh16_r3_b(76)    );
+o_077:    ex2_sh_lvl3(77)      <= not( ex2_sh16_r1_b(77)    and ex2_sh16_r2_b(77)    and ex2_sh16_r3_b(77)    );
+o_078:    ex2_sh_lvl3(78)      <= not( ex2_sh16_r1_b(78)    and ex2_sh16_r2_b(78)    and ex2_sh16_r3_b(78)    );
+o_079:    ex2_sh_lvl3(79)      <= not( ex2_sh16_r1_b(79)    and ex2_sh16_r2_b(79)    and ex2_sh16_r3_b(79)    );
+o_080:    ex2_sh_lvl3(80)      <= not( ex2_sh16_r1_b(80)    and ex2_sh16_r2_b(80)    and ex2_sh16_r3_b(80)    );
+o_081:    ex2_sh_lvl3(81)      <= not( ex2_sh16_r1_b(81)    and ex2_sh16_r2_b(81)    and ex2_sh16_r3_b(81)    );
+o_082:    ex2_sh_lvl3(82)      <= not( ex2_sh16_r1_b(82)    and ex2_sh16_r2_b(82)    and ex2_sh16_r3_b(82)    );
+o_083:    ex2_sh_lvl3(83)      <= not( ex2_sh16_r1_b(83)    and ex2_sh16_r2_b(83)    and ex2_sh16_r3_b(83)    );
+o_084:    ex2_sh_lvl3(84)      <= not( ex2_sh16_r1_b(84)    and ex2_sh16_r2_b(84)    and ex2_sh16_r3_b(84)    );
+o_085:    ex2_sh_lvl3(85)      <= not( ex2_sh16_r1_b(85)    and ex2_sh16_r2_b(85)    and ex2_sh16_r3_b(85)    );
+o_086:    ex2_sh_lvl3(86)      <= not( ex2_sh16_r1_b(86)    and ex2_sh16_r2_b(86)    and ex2_sh16_r3_b(86)    );
+o_087:    ex2_sh_lvl3(87)      <= not( ex2_sh16_r1_b(87)    and ex2_sh16_r2_b(87)    and ex2_sh16_r3_b(87)    );
+o_088:    ex2_sh_lvl3(88)      <= not( ex2_sh16_r1_b(88)    and ex2_sh16_r2_b(88)    and ex2_sh16_r3_b(88)    );
+o_089:    ex2_sh_lvl3(89)      <= not( ex2_sh16_r1_b(89)    and ex2_sh16_r2_b(89)    and ex2_sh16_r3_b(89)    );
+o_090:    ex2_sh_lvl3(90)      <= not( ex2_sh16_r1_b(90)    and ex2_sh16_r2_b(90)    and ex2_sh16_r3_b(90)    );
+o_091:    ex2_sh_lvl3(91)      <= not( ex2_sh16_r1_b(91)    and ex2_sh16_r2_b(91)    and ex2_sh16_r3_b(91)    );
+o_092:    ex2_sh_lvl3(92)      <= not( ex2_sh16_r1_b(92)    and ex2_sh16_r2_b(92)    and ex2_sh16_r3_b(92)    );
+o_093:    ex2_sh_lvl3(93)      <= not( ex2_sh16_r1_b(93)    and ex2_sh16_r2_b(93)    and ex2_sh16_r3_b(93)    );
+o_094:    ex2_sh_lvl3(94)      <= not( ex2_sh16_r1_b(94)    and ex2_sh16_r2_b(94)    and ex2_sh16_r3_b(94)    );
+o_095:    ex2_sh_lvl3(95)      <= not( ex2_sh16_r1_b(95)    and ex2_sh16_r2_b(95)    and ex2_sh16_r3_b(95)    );
+o_096:    ex2_sh_lvl3(96)      <= not( ex2_sh16_r1_b(96)    and ex2_sh16_r2_b(96)    and ex2_sh16_r3_b(96)    );
+o_097:    ex2_sh_lvl3(97)      <= not( ex2_sh16_r1_b(97)    and ex2_sh16_r2_b(97)    and ex2_sh16_r3_b(97)    );
+o_098:    ex2_sh_lvl3(98)      <= not( ex2_sh16_r1_b(98)    and ex2_sh16_r2_b(98)    and ex2_sh16_r3_b(98)    );
+o_099:    ex2_sh_lvl3(99)      <= not( ex2_sh16_r1_b(99)    and ex2_sh16_r2_b(99)    and ex2_sh16_r3_b(99)    );
+o_100:    ex2_sh_lvl3(100)     <= not( ex2_sh16_r1_b(100)   and ex2_sh16_r2_b(100)   and ex2_sh16_r3_b(100)   );
+o_101:    ex2_sh_lvl3(101)     <= not( ex2_sh16_r1_b(101)   and ex2_sh16_r2_b(101)   and ex2_sh16_r3_b(101)   );
+o_102:    ex2_sh_lvl3(102)     <= not( ex2_sh16_r1_b(102)   and ex2_sh16_r2_b(102)   and ex2_sh16_r3_b(102)   );
+o_103:    ex2_sh_lvl3(103)     <= not( ex2_sh16_r1_b(103)   and ex2_sh16_r2_b(103)   and ex2_sh16_r3_b(103)   );
+o_104:    ex2_sh_lvl3(104)     <= not( ex2_sh16_r1_b(104)   and ex2_sh16_r2_b(104)   and ex2_sh16_r3_b(104)   );
+o_105:    ex2_sh_lvl3(105)     <= not( ex2_sh16_r1_b(105)   and ex2_sh16_r2_b(105)   and ex2_sh16_r3_b(105)   );
+o_106:    ex2_sh_lvl3(106)     <= not( ex2_sh16_r1_b(106)   and ex2_sh16_r2_b(106)   and ex2_sh16_r3_b(106)   );
+o_107:    ex2_sh_lvl3(107)     <= not( ex2_sh16_r1_b(107)   and ex2_sh16_r2_b(107)   and ex2_sh16_r3_b(107)   );
+o_108:    ex2_sh_lvl3(108)     <= not( ex2_sh16_r1_b(108)   and ex2_sh16_r2_b(108)   and ex2_sh16_r3_b(108)   );
+o_109:    ex2_sh_lvl3(109)     <= not( ex2_sh16_r1_b(109)   and ex2_sh16_r2_b(109)   and ex2_sh16_r3_b(109)   );
+o_110:    ex2_sh_lvl3(110)     <= not( ex2_sh16_r1_b(110)   and ex2_sh16_r2_b(110)   and ex2_sh16_r3_b(110)   );
+o_111:    ex2_sh_lvl3(111)     <= not( ex2_sh16_r1_b(111)   and ex2_sh16_r2_b(111)   and ex2_sh16_r3_b(111)   );
+o_112:    ex2_sh_lvl3(112)     <= not( ex2_sh16_r1_b(112)   and ex2_sh16_r2_b(112)   and ex2_sh16_r3_b(112)   );
+o_113:    ex2_sh_lvl3(113)     <= not( ex2_sh16_r1_b(113)   and ex2_sh16_r2_b(113)   and ex2_sh16_r3_b(113)   );
+o_114:    ex2_sh_lvl3(114)     <= not( ex2_sh16_r1_b(114)   and ex2_sh16_r2_b(114)   and ex2_sh16_r3_b(114)   );
+o_115:    ex2_sh_lvl3(115)     <= not( ex2_sh16_r1_b(115)   and ex2_sh16_r2_b(115)   and ex2_sh16_r3_b(115)   );
+o_116:    ex2_sh_lvl3(116)     <= not( ex2_sh16_r1_b(116)   and ex2_sh16_r2_b(116)   and ex2_sh16_r3_b(116)   );
+o_117:    ex2_sh_lvl3(117)     <= not( ex2_sh16_r1_b(117)   and ex2_sh16_r2_b(117)   and ex2_sh16_r3_b(117)   );
+o_118:    ex2_sh_lvl3(118)     <= not( ex2_sh16_r1_b(118)   and ex2_sh16_r2_b(118)   and ex2_sh16_r3_b(118)   );
+o_119:    ex2_sh_lvl3(119)     <= not( ex2_sh16_r1_b(119)   and ex2_sh16_r2_b(119)   and ex2_sh16_r3_b(119)   );
+o_120:    ex2_sh_lvl3(120)     <= not( ex2_sh16_r1_b(120)   and ex2_sh16_r2_b(120)   and ex2_sh16_r3_b(120)   );
+o_121:    ex2_sh_lvl3(121)     <= not( ex2_sh16_r1_b(121)   and ex2_sh16_r2_b(121)   and ex2_sh16_r3_b(121)   );
+o_122:    ex2_sh_lvl3(122)     <= not( ex2_sh16_r1_b(122)   and ex2_sh16_r2_b(122)   and ex2_sh16_r3_b(122)   );
+o_123:    ex2_sh_lvl3(123)     <= not( ex2_sh16_r1_b(123)   and ex2_sh16_r2_b(123)   and ex2_sh16_r3_b(123)   );
+o_124:    ex2_sh_lvl3(124)     <= not( ex2_sh16_r1_b(124)   and ex2_sh16_r2_b(124)   and ex2_sh16_r3_b(124)   );
+o_125:    ex2_sh_lvl3(125)     <= not( ex2_sh16_r1_b(125)   and ex2_sh16_r2_b(125)   and ex2_sh16_r3_b(125)   );
+o_126:    ex2_sh_lvl3(126)     <= not( ex2_sh16_r1_b(126)   and ex2_sh16_r2_b(126)   and ex2_sh16_r3_b(126)   );
+o_127:    ex2_sh_lvl3(127)     <= not( ex2_sh16_r1_b(127)   and ex2_sh16_r2_b(127)   and ex2_sh16_r3_b(127)   );
+o_128:    ex2_sh_lvl3(128)     <= not( ex2_sh16_r1_b(128)   and ex2_sh16_r2_b(128)   and ex2_sh16_r3_b(128)   );
+o_129:    ex2_sh_lvl3(129)     <= not( ex2_sh16_r1_b(129)   and ex2_sh16_r2_b(129)   and ex2_sh16_r3_b(129)   );
+o_130:    ex2_sh_lvl3(130)     <= not( ex2_sh16_r1_b(130)   and ex2_sh16_r2_b(130)   and ex2_sh16_r3_b(130)   );
+o_131:    ex2_sh_lvl3(131)     <= not( ex2_sh16_r1_b(131)   and ex2_sh16_r2_b(131)   and ex2_sh16_r3_b(131)   );
+o_132:    ex2_sh_lvl3(132)     <= not( ex2_sh16_r1_b(132)   and ex2_sh16_r2_b(132)   and ex2_sh16_r3_b(132)   );
+o_133:    ex2_sh_lvl3(133)     <= not( ex2_sh16_r1_b(133)   and ex2_sh16_r2_b(133)   and ex2_sh16_r3_b(133)   );
+o_134:    ex2_sh_lvl3(134)     <= not( ex2_sh16_r1_b(134)   and ex2_sh16_r2_b(134)   and ex2_sh16_r3_b(134)   );
+o_135:    ex2_sh_lvl3(135)     <= not( ex2_sh16_r1_b(135)   and ex2_sh16_r2_b(135)   and ex2_sh16_r3_b(135)   );
+o_136:    ex2_sh_lvl3(136)     <= not( ex2_sh16_r1_b(136)   and ex2_sh16_r2_b(136)   and ex2_sh16_r3_b(136)   );
+o_137:    ex2_sh_lvl3(137)     <= not( ex2_sh16_r1_b(137)   and ex2_sh16_r2_b(137)   and ex2_sh16_r3_b(137)   );
+o_138:    ex2_sh_lvl3(138)     <= not( ex2_sh16_r1_b(138)   and ex2_sh16_r2_b(138)   and ex2_sh16_r3_b(138)   );
+o_139:    ex2_sh_lvl3(139)     <= not( ex2_sh16_r1_b(139)   and ex2_sh16_r2_b(139)   and ex2_sh16_r3_b(139)   );
+o_140:    ex2_sh_lvl3(140)     <= not( ex2_sh16_r1_b(140)   and ex2_sh16_r2_b(140)   and ex2_sh16_r3_b(140)   );
+o_141:    ex2_sh_lvl3(141)     <= not( ex2_sh16_r1_b(141)   and ex2_sh16_r2_b(141)   and ex2_sh16_r3_b(141)   );
+o_142:    ex2_sh_lvl3(142)     <= not( ex2_sh16_r1_b(142)   and ex2_sh16_r2_b(142)   and ex2_sh16_r3_b(142)   );
+o_143:    ex2_sh_lvl3(143)     <= not( ex2_sh16_r1_b(143)   and ex2_sh16_r2_b(143)   and ex2_sh16_r3_b(143)   );
+o_144:    ex2_sh_lvl3(144)     <= not( ex2_sh16_r1_b(144)   and ex2_sh16_r2_b(144)   and ex2_sh16_r3_b(144)   );
+o_145:    ex2_sh_lvl3(145)     <= not( ex2_sh16_r1_b(145)   and ex2_sh16_r2_b(145)   and ex2_sh16_r3_b(145)   );
+o_146:    ex2_sh_lvl3(146)     <= not( ex2_sh16_r1_b(146)   and ex2_sh16_r2_b(146)   and ex2_sh16_r3_b(146)   );
+o_147:    ex2_sh_lvl3(147)     <= not( ex2_sh16_r1_b(147)   and ex2_sh16_r2_b(147)   and ex2_sh16_r3_b(147)   );
+o_148:    ex2_sh_lvl3(148)     <= not( ex2_sh16_r1_b(148)   and ex2_sh16_r2_b(148)   and ex2_sh16_r3_b(148)   );
+o_149:    ex2_sh_lvl3(149)     <= not( ex2_sh16_r1_b(149)   and ex2_sh16_r2_b(149)   and ex2_sh16_r3_b(149)   );
+o_150:    ex2_sh_lvl3(150)     <= not( ex2_sh16_r1_b(150)   and ex2_sh16_r2_b(150)   and ex2_sh16_r3_b(150)   );
+o_151:    ex2_sh_lvl3(151)     <= not( ex2_sh16_r1_b(151)   and ex2_sh16_r2_b(151)   and ex2_sh16_r3_b(151)   );
+o_152:    ex2_sh_lvl3(152)     <= not( ex2_sh16_r1_b(152)   and ex2_sh16_r2_b(152)   and ex2_sh16_r3_b(152)   );
+o_153:    ex2_sh_lvl3(153)     <= not( ex2_sh16_r1_b(153)   and ex2_sh16_r2_b(153)   and ex2_sh16_r3_b(153)   );
+o_154:    ex2_sh_lvl3(154)     <= not( ex2_sh16_r1_b(154)   and ex2_sh16_r2_b(154)   and ex2_sh16_r3_b(154)   );
+o_155:    ex2_sh_lvl3(155)     <= not( ex2_sh16_r1_b(155)   and ex2_sh16_r2_b(155)   and ex2_sh16_r3_b(155)   );
+o_156:    ex2_sh_lvl3(156)     <= not( ex2_sh16_r1_b(156)   and ex2_sh16_r2_b(156)   and ex2_sh16_r3_b(156)   );
+o_157:    ex2_sh_lvl3(157)     <= not( ex2_sh16_r1_b(157)   and ex2_sh16_r2_b(157)   and ex2_sh16_r3_b(157)   );
+o_158:    ex2_sh_lvl3(158)     <= not( ex2_sh16_r1_b(158)   and ex2_sh16_r2_b(158)   and ex2_sh16_r3_b(158)   );
+o_159:    ex2_sh_lvl3(159)     <= not( ex2_sh16_r1_b(159)   and ex2_sh16_r2_b(159)   and ex2_sh16_r3_b(159)   );
+o_160:    ex2_sh_lvl3(160)     <= not( ex2_sh16_r1_b(160)   and ex2_sh16_r2_b(160)   and ex2_sh16_r3_b(160)   );
+o_161:    ex2_sh_lvl3(161)     <= not( ex2_sh16_r1_b(161)   and ex2_sh16_r2_b(161)   and ex2_sh16_r3_b(161)   );
+o_162:    ex2_sh_lvl3(162)     <= not( ex2_sh16_r1_b(162)   and ex2_sh16_r2_b(162)   and ex2_sh16_r3_b(162)   );
+
+
+
+
+
+rr3_162:   ex2_sh16_r3_162_b    <= not( (ex2_lvl3_shdcd160 and ex2_sh_lvl2(2)      ) or (ex2_sel_special   and ex2_special(162)    ) );
+rr3_163:   ex2_sh16_r3_163_b    <= not(  ex2_lvl3_shdcd160 and ex2_sh_lvl2(3)      );
+
+rr2_162:   ex2_sh16_r2_162_b    <= not( (ex2_lvl3_shdcd128 and ex2_sh_lvl2(34)     ) or (ex2_lvl3_shdcd144 and ex2_sh_lvl2(18)     ) );
+rr2_163:   ex2_sh16_r2_163_b    <= not( (ex2_lvl3_shdcd128 and ex2_sh_lvl2(35)     ) or (ex2_lvl3_shdcd144 and ex2_sh_lvl2(19)     ) );
+
+rr1_162:   ex2_sh16_r1_162_b    <= not( (ex2_lvl3_shdcd096 and ex2_sh_lvl2(66)     ) or (ex2_lvl3_shdcd112 and ex2_sh_lvl2(50)     ) );
+rr1_163:   ex2_sh16_r1_163_b    <= not( (ex2_lvl3_shdcd096 and ex2_sh_lvl2(67)     ) or (ex2_lvl3_shdcd112 and ex2_sh_lvl2(51)     ) );
+
+ro_162:    ex2_sh16_162         <= not( ex2_sh16_r1_162_b  and ex2_sh16_r2_162_b and ex2_sh16_r3_162_b  );
+ro_163:    ex2_sh16_163         <= not( ex2_sh16_r1_163_b  and ex2_sh16_r2_163_b and ex2_sh16_r3_163_b  );
+
+
+
+end; 
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_alg_sh4.vhdl

@@ -0,0 +1,708 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+ 
+entity fuq_alg_sh4 is
+generic(       expand_type               : integer := 2  ); 
+port(
+      ex1_lvl1_shdcd000_b      :in   std_ulogic;
+      ex1_lvl1_shdcd001_b      :in   std_ulogic;
+      ex1_lvl1_shdcd002_b      :in   std_ulogic;
+      ex1_lvl1_shdcd003_b      :in   std_ulogic;
+      ex1_lvl2_shdcd000        :in   std_ulogic;
+      ex1_lvl2_shdcd004        :in   std_ulogic;
+      ex1_lvl2_shdcd008        :in   std_ulogic;
+      ex1_lvl2_shdcd012        :in   std_ulogic;
+      ex1_sel_special          :in   std_ulogic;
+
+      ex1_b_sign               :in   std_ulogic;
+      ex1_b_expo               :in   std_ulogic_vector(3 to 13) ;
+      ex1_b_frac               :in   std_ulogic_vector(0 to 52) ;
+
+      ex1_sh_lvl2              :out std_ulogic_vector(0 to 67)  
+);
+
+
+
+end fuq_alg_sh4; 
+
+architecture fuq_alg_sh4 of fuq_alg_sh4 is
+
+    constant tiup : std_ulogic := '1';
+    constant tidn : std_ulogic := '0';
+
+    signal ex1_special_fcfid :std_ulogic_vector(0 to 63);
+    signal ex1_sh_lv1       :std_ulogic_vector(0 to 55);
+    signal ex1_sh_lv1x_b     :std_ulogic_vector(0 to 53);
+    signal ex1_sh_lv1y_b     :std_ulogic_vector(2 to 55);
+    signal ex1_sh_lv2x_b :std_ulogic_vector(0 to 59);
+    signal ex1_sh_lv2y_b :std_ulogic_vector(8 to 67);
+    signal ex1_sh_lv2z_b :std_ulogic_vector(0 to 63);
+
+ signal sh1v2dcd0_cp1    :std_ulogic;
+ signal sh1v3dcd0_cp1_b  :std_ulogic;
+ signal sh1v3dcd0_cp2_b  :std_ulogic;
+ signal sh1v4dcd0_cp1    :std_ulogic;
+ signal sh1v4dcd0_cp2    :std_ulogic;
+ signal sh1v4dcd0_cp3    :std_ulogic;
+ signal sh1v4dcd0_cp4    :std_ulogic;
+ signal sh1v2dcd1_cp1    :std_ulogic;
+ signal sh1v3dcd1_cp1_b  :std_ulogic;
+ signal sh1v3dcd1_cp2_b  :std_ulogic;
+ signal sh1v4dcd1_cp1    :std_ulogic;
+ signal sh1v4dcd1_cp2    :std_ulogic;
+ signal sh1v4dcd1_cp3    :std_ulogic;
+ signal sh1v4dcd1_cp4    :std_ulogic;
+ signal sh1v2dcd2_cp1    :std_ulogic;
+ signal sh1v3dcd2_cp1_b  :std_ulogic;
+ signal sh1v3dcd2_cp2_b  :std_ulogic;
+ signal sh1v4dcd2_cp1    :std_ulogic;
+ signal sh1v4dcd2_cp2    :std_ulogic;
+ signal sh1v4dcd2_cp3    :std_ulogic;
+ signal sh1v4dcd2_cp4    :std_ulogic;
+ signal sh1v2dcd3_cp1    :std_ulogic;
+ signal sh1v3dcd3_cp1_b  :std_ulogic;
+ signal sh1v3dcd3_cp2_b  :std_ulogic;
+ signal sh1v4dcd3_cp1    :std_ulogic;
+ signal sh1v4dcd3_cp2    :std_ulogic;
+ signal sh1v4dcd3_cp3    :std_ulogic;
+ signal sh1v4dcd3_cp4    :std_ulogic;
+ signal sh2v1dcd00_cp1_b :std_ulogic;
+ signal sh2v2dcd00_cp1   :std_ulogic;
+ signal sh2v3dcd00_cp1_b :std_ulogic;
+ signal sh2v3dcd00_cp2_b :std_ulogic;
+ signal sh2v4dcd00_cp1   :std_ulogic;
+ signal sh2v4dcd00_cp2   :std_ulogic;
+ signal sh2v4dcd00_cp3   :std_ulogic;
+ signal sh2v4dcd00_cp4   :std_ulogic;
+ signal sh2v1dcd04_cp1_b :std_ulogic;
+ signal sh2v2dcd04_cp1   :std_ulogic;
+ signal sh2v3dcd04_cp1_b :std_ulogic;
+ signal sh2v3dcd04_cp2_b :std_ulogic;
+ signal sh2v4dcd04_cp1   :std_ulogic;
+ signal sh2v4dcd04_cp2   :std_ulogic;
+ signal sh2v4dcd04_cp3   :std_ulogic;
+ signal sh2v4dcd04_cp4   :std_ulogic;
+ signal sh2v1dcd08_cp1_b :std_ulogic;
+ signal sh2v2dcd08_cp1   :std_ulogic;
+ signal sh2v3dcd08_cp1_b :std_ulogic;
+ signal sh2v3dcd08_cp2_b :std_ulogic;
+ signal sh2v4dcd08_cp1   :std_ulogic;
+ signal sh2v4dcd08_cp2   :std_ulogic;
+ signal sh2v4dcd08_cp3   :std_ulogic;
+ signal sh2v4dcd08_cp4   :std_ulogic;
+ signal sh2v1dcd12_cp1_b :std_ulogic;
+ signal sh2v2dcd12_cp1   :std_ulogic;
+ signal sh2v3dcd12_cp1_b :std_ulogic;
+ signal sh2v3dcd12_cp2_b :std_ulogic;
+ signal sh2v4dcd12_cp1   :std_ulogic;
+ signal sh2v4dcd12_cp2   :std_ulogic;
+ signal sh2v4dcd12_cp3   :std_ulogic;
+ signal sh2v4dcd12_cp4   :std_ulogic;
+ signal sh2v1dcdpp_cp1_b :std_ulogic;
+ signal sh2v2dcdpp_cp1   :std_ulogic;
+ signal sh2v3dcdpp_cp1_b :std_ulogic;
+ signal sh2v3dcdpp_cp2_b :std_ulogic;
+ signal sh2v4dcdpp_cp1   :std_ulogic;
+ signal sh2v4dcdpp_cp2   :std_ulogic;
+ signal sh2v4dcdpp_cp3   :std_ulogic;
+ signal sh2v4dcdpp_cp4   :std_ulogic;
+ 
+
+
+
+
+
+
+
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+begin
+
+
+    ex1_special_fcfid(0)        <= ex1_b_sign     ;  
+    ex1_special_fcfid(1)        <= ex1_b_expo( 3) ;
+    ex1_special_fcfid(2)        <= ex1_b_expo( 4) and ex1_b_frac(0) ;
+    ex1_special_fcfid(3)        <= ex1_b_expo( 5) and ex1_b_frac(0) ;
+    ex1_special_fcfid(4)        <= ex1_b_expo( 6) and ex1_b_frac(0) ;
+    ex1_special_fcfid(5)        <= ex1_b_expo( 7) ;
+    ex1_special_fcfid(6)        <= ex1_b_expo( 8) ;
+    ex1_special_fcfid(7)        <= ex1_b_expo( 9) ;
+    ex1_special_fcfid(8)        <= ex1_b_expo(10) ;
+    ex1_special_fcfid(9)        <= ex1_b_expo(11) ;
+    ex1_special_fcfid(10)       <= ex1_b_expo(12) ;
+    ex1_special_fcfid(11)       <= ex1_b_expo(13) and ex1_b_frac(0) ;
+    ex1_special_fcfid(12 to 63) <= ex1_b_frac(1 to 52); 
+
+
+
+
+ s1v2d0c1:  sh1v2dcd0_cp1   <= not ex1_lvl1_shdcd000_b;
+ s1v3d0c1:  sh1v3dcd0_cp1_b <= not sh1v2dcd0_cp1 ;
+ s1v3d0c2:  sh1v3dcd0_cp2_b <= not sh1v2dcd0_cp1 ;
+ s1v4d0c1:  sh1v4dcd0_cp1   <= not sh1v3dcd0_cp1_b; 
+ s1v4d0c2:  sh1v4dcd0_cp2   <= not sh1v3dcd0_cp1_b; 
+ s1v4d0c3:  sh1v4dcd0_cp3   <= not sh1v3dcd0_cp2_b; 
+ s1v4d0c4:  sh1v4dcd0_cp4   <= not sh1v3dcd0_cp2_b; 
+
+ s1v2d1c1:  sh1v2dcd1_cp1   <= not ex1_lvl1_shdcd001_b;
+ s1v3d1c1:  sh1v3dcd1_cp1_b <= not sh1v2dcd1_cp1 ;
+ s1v3d1c2:  sh1v3dcd1_cp2_b <= not sh1v2dcd1_cp1 ;
+ s1v4d1c1:  sh1v4dcd1_cp1   <= not sh1v3dcd1_cp1_b; 
+ s1v4d1c2:  sh1v4dcd1_cp2   <= not sh1v3dcd1_cp1_b; 
+ s1v4d1c3:  sh1v4dcd1_cp3   <= not sh1v3dcd1_cp2_b; 
+ s1v4d1c4:  sh1v4dcd1_cp4   <= not sh1v3dcd1_cp2_b; 
+
+ s1v2d2c1:  sh1v2dcd2_cp1   <= not ex1_lvl1_shdcd002_b;
+ s1v3d2c1:  sh1v3dcd2_cp1_b <= not sh1v2dcd2_cp1 ;
+ s1v3d2c2:  sh1v3dcd2_cp2_b <= not sh1v2dcd2_cp1 ;
+ s1v4d2c1:  sh1v4dcd2_cp1   <= not sh1v3dcd2_cp1_b; 
+ s1v4d2c2:  sh1v4dcd2_cp2   <= not sh1v3dcd2_cp1_b; 
+ s1v4d2c3:  sh1v4dcd2_cp3   <= not sh1v3dcd2_cp2_b; 
+ s1v4d2c4:  sh1v4dcd2_cp4   <= not sh1v3dcd2_cp2_b; 
+
+ s1v2d3c1:  sh1v2dcd3_cp1   <= not ex1_lvl1_shdcd003_b;
+ s1v3d3c1:  sh1v3dcd3_cp1_b <= not sh1v2dcd3_cp1 ;
+ s1v3d3c2:  sh1v3dcd3_cp2_b <= not sh1v2dcd3_cp1 ;
+ s1v4d3c1:  sh1v4dcd3_cp1   <= not sh1v3dcd3_cp1_b; 
+ s1v4d3c2:  sh1v4dcd3_cp2   <= not sh1v3dcd3_cp1_b; 
+ s1v4d3c3:  sh1v4dcd3_cp3   <= not sh1v3dcd3_cp2_b; 
+ s1v4d3c4:  sh1v4dcd3_cp4   <= not sh1v3dcd3_cp2_b; 
+
+
+ s2v1d00c1:  sh2v1dcd00_cp1_b <= not ex1_lvl2_shdcd000;
+ s2v2d00c1:  sh2v2dcd00_cp1   <= not sh2v1dcd00_cp1_b ;
+ s2v3d00c1:  sh2v3dcd00_cp1_b <= not sh2v2dcd00_cp1 ;
+ s2v3d00c2:  sh2v3dcd00_cp2_b <= not sh2v2dcd00_cp1 ;
+ s2v4d00c1:  sh2v4dcd00_cp1   <= not sh2v3dcd00_cp1_b; 
+ s2v4d00c2:  sh2v4dcd00_cp2   <= not sh2v3dcd00_cp1_b; 
+ s2v4d00c3:  sh2v4dcd00_cp3   <= not sh2v3dcd00_cp2_b; 
+ s2v4d00c4:  sh2v4dcd00_cp4   <= not sh2v3dcd00_cp2_b; 
+
+ s2v1d04c1:  sh2v1dcd04_cp1_b <= not ex1_lvl2_shdcd004;
+ s2v2d04c1:  sh2v2dcd04_cp1   <= not sh2v1dcd04_cp1_b ;
+ s2v3d04c1:  sh2v3dcd04_cp1_b <= not sh2v2dcd04_cp1 ;
+ s2v3d04c2:  sh2v3dcd04_cp2_b <= not sh2v2dcd04_cp1 ;
+ s2v4d04c1:  sh2v4dcd04_cp1   <= not sh2v3dcd04_cp1_b; 
+ s2v4d04c2:  sh2v4dcd04_cp2   <= not sh2v3dcd04_cp1_b; 
+ s2v4d04c3:  sh2v4dcd04_cp3   <= not sh2v3dcd04_cp2_b; 
+ s2v4d04c4:  sh2v4dcd04_cp4   <= not sh2v3dcd04_cp2_b; 
+
+ s2v1d08c1:  sh2v1dcd08_cp1_b <= not ex1_lvl2_shdcd008;
+ s2v2d08c1:  sh2v2dcd08_cp1   <= not sh2v1dcd08_cp1_b ;
+ s2v3d08c1:  sh2v3dcd08_cp1_b <= not sh2v2dcd08_cp1 ;
+ s2v3d08c2:  sh2v3dcd08_cp2_b <= not sh2v2dcd08_cp1 ;
+ s2v4d08c1:  sh2v4dcd08_cp1   <= not sh2v3dcd08_cp1_b; 
+ s2v4d08c2:  sh2v4dcd08_cp2   <= not sh2v3dcd08_cp1_b; 
+ s2v4d08c3:  sh2v4dcd08_cp3   <= not sh2v3dcd08_cp2_b; 
+ s2v4d08c4:  sh2v4dcd08_cp4   <= not sh2v3dcd08_cp2_b; 
+
+ s2v1d12c1:  sh2v1dcd12_cp1_b <= not ex1_lvl2_shdcd012;
+ s2v2d12c1:  sh2v2dcd12_cp1   <= not sh2v1dcd12_cp1_b ;
+ s2v3d12c1:  sh2v3dcd12_cp1_b <= not sh2v2dcd12_cp1 ;
+ s2v3d12c2:  sh2v3dcd12_cp2_b <= not sh2v2dcd12_cp1 ;
+ s2v4d12c1:  sh2v4dcd12_cp1   <= not sh2v3dcd12_cp1_b; 
+ s2v4d12c2:  sh2v4dcd12_cp2   <= not sh2v3dcd12_cp1_b; 
+ s2v4d12c3:  sh2v4dcd12_cp3   <= not sh2v3dcd12_cp2_b; 
+ s2v4d12c4:  sh2v4dcd12_cp4   <= not sh2v3dcd12_cp2_b; 
+
+ s2v1dppc1:  sh2v1dcdpp_cp1_b <= not ex1_sel_special ;
+ s2v2dppc1:  sh2v2dcdpp_cp1   <= not sh2v1dcdpp_cp1_b ;
+ s2v3dppc1:  sh2v3dcdpp_cp1_b <= not sh2v2dcdpp_cp1 ;
+ s2v3dppc2:  sh2v3dcdpp_cp2_b <= not sh2v2dcdpp_cp1 ;
+ s2v4dppc1:  sh2v4dcdpp_cp1   <= not sh2v3dcdpp_cp1_b; 
+ s2v4dppc2:  sh2v4dcdpp_cp2   <= not sh2v3dcdpp_cp1_b; 
+ s2v4dppc3:  sh2v4dcdpp_cp3   <= not sh2v3dcdpp_cp2_b; 
+ s2v4dppc4:  sh2v4dcdpp_cp4   <= not sh2v3dcdpp_cp2_b; 
+
+
+
+  lv1x_00: ex1_sh_lv1x_b(0)  <= not(  sh1v4dcd0_cp1 and ex1_b_frac(0)  ) ;
+  lv1x_01: ex1_sh_lv1x_b(1)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(1)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(0)  ) );
+  lv1x_02: ex1_sh_lv1x_b(2)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(2)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(1)  ) );
+  lv1x_03: ex1_sh_lv1x_b(3)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(3)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(2)  ) );
+  lv1x_04: ex1_sh_lv1x_b(4)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(4)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(3)  ) );
+  lv1x_05: ex1_sh_lv1x_b(5)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(5)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(4)  ) );
+  lv1x_06: ex1_sh_lv1x_b(6)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(6)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(5)  ) );
+  lv1x_07: ex1_sh_lv1x_b(7)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(7)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(6)  ) );
+  lv1x_08: ex1_sh_lv1x_b(8)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(8)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(7)  ) );
+  lv1x_09: ex1_sh_lv1x_b(9)  <= not( (sh1v4dcd0_cp1 and ex1_b_frac(9)  ) or (sh1v4dcd1_cp1 and ex1_b_frac(8)  ) );
+  lv1x_10: ex1_sh_lv1x_b(10) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(10) ) or (sh1v4dcd1_cp1 and ex1_b_frac(9)  ) );
+  lv1x_11: ex1_sh_lv1x_b(11) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(11) ) or (sh1v4dcd1_cp1 and ex1_b_frac(10) ) );
+  lv1x_12: ex1_sh_lv1x_b(12) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(12) ) or (sh1v4dcd1_cp1 and ex1_b_frac(11) ) );
+  lv1x_13: ex1_sh_lv1x_b(13) <= not( (sh1v4dcd0_cp1 and ex1_b_frac(13) ) or (sh1v4dcd1_cp1 and ex1_b_frac(12) ) );
+  lv1x_14: ex1_sh_lv1x_b(14) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(14) ) or (sh1v4dcd1_cp2 and ex1_b_frac(13) ) );
+  lv1x_15: ex1_sh_lv1x_b(15) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(15) ) or (sh1v4dcd1_cp2 and ex1_b_frac(14) ) );
+  lv1x_16: ex1_sh_lv1x_b(16) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(16) ) or (sh1v4dcd1_cp2 and ex1_b_frac(15) ) );
+  lv1x_17: ex1_sh_lv1x_b(17) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(17) ) or (sh1v4dcd1_cp2 and ex1_b_frac(16) ) );
+  lv1x_18: ex1_sh_lv1x_b(18) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(18) ) or (sh1v4dcd1_cp2 and ex1_b_frac(17) ) );
+  lv1x_19: ex1_sh_lv1x_b(19) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(19) ) or (sh1v4dcd1_cp2 and ex1_b_frac(18) ) );
+  lv1x_20: ex1_sh_lv1x_b(20) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(20) ) or (sh1v4dcd1_cp2 and ex1_b_frac(19) ) );
+  lv1x_21: ex1_sh_lv1x_b(21) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(21) ) or (sh1v4dcd1_cp2 and ex1_b_frac(20) ) );
+  lv1x_22: ex1_sh_lv1x_b(22) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(22) ) or (sh1v4dcd1_cp2 and ex1_b_frac(21) ) );
+  lv1x_23: ex1_sh_lv1x_b(23) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(23) ) or (sh1v4dcd1_cp2 and ex1_b_frac(22) ) );
+  lv1x_24: ex1_sh_lv1x_b(24) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(24) ) or (sh1v4dcd1_cp2 and ex1_b_frac(23) ) );
+  lv1x_25: ex1_sh_lv1x_b(25) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(25) ) or (sh1v4dcd1_cp2 and ex1_b_frac(24) ) );
+  lv1x_26: ex1_sh_lv1x_b(26) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(26) ) or (sh1v4dcd1_cp2 and ex1_b_frac(25) ) );
+  lv1x_27: ex1_sh_lv1x_b(27) <= not( (sh1v4dcd0_cp2 and ex1_b_frac(27) ) or (sh1v4dcd1_cp2 and ex1_b_frac(26) ) );
+  lv1x_28: ex1_sh_lv1x_b(28) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(28) ) or (sh1v4dcd1_cp3 and ex1_b_frac(27) ) );
+  lv1x_29: ex1_sh_lv1x_b(29) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(29) ) or (sh1v4dcd1_cp3 and ex1_b_frac(28) ) );
+  lv1x_30: ex1_sh_lv1x_b(30) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(30) ) or (sh1v4dcd1_cp3 and ex1_b_frac(29) ) );
+  lv1x_31: ex1_sh_lv1x_b(31) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(31) ) or (sh1v4dcd1_cp3 and ex1_b_frac(30) ) );
+  lv1x_32: ex1_sh_lv1x_b(32) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(32) ) or (sh1v4dcd1_cp3 and ex1_b_frac(31) ) );
+  lv1x_33: ex1_sh_lv1x_b(33) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(33) ) or (sh1v4dcd1_cp3 and ex1_b_frac(32) ) );
+  lv1x_34: ex1_sh_lv1x_b(34) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(34) ) or (sh1v4dcd1_cp3 and ex1_b_frac(33) ) );
+  lv1x_35: ex1_sh_lv1x_b(35) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(35) ) or (sh1v4dcd1_cp3 and ex1_b_frac(34) ) );
+  lv1x_36: ex1_sh_lv1x_b(36) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(36) ) or (sh1v4dcd1_cp3 and ex1_b_frac(35) ) );
+  lv1x_37: ex1_sh_lv1x_b(37) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(37) ) or (sh1v4dcd1_cp3 and ex1_b_frac(36) ) );
+  lv1x_38: ex1_sh_lv1x_b(38) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(38) ) or (sh1v4dcd1_cp3 and ex1_b_frac(37) ) );
+  lv1x_39: ex1_sh_lv1x_b(39) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(39) ) or (sh1v4dcd1_cp3 and ex1_b_frac(38) ) );
+  lv1x_40: ex1_sh_lv1x_b(40) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(40) ) or (sh1v4dcd1_cp3 and ex1_b_frac(39) ) );
+  lv1x_41: ex1_sh_lv1x_b(41) <= not( (sh1v4dcd0_cp3 and ex1_b_frac(41) ) or (sh1v4dcd1_cp3 and ex1_b_frac(40) ) );
+  lv1x_42: ex1_sh_lv1x_b(42) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(42) ) or (sh1v4dcd1_cp4 and ex1_b_frac(41) ) );
+  lv1x_43: ex1_sh_lv1x_b(43) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(43) ) or (sh1v4dcd1_cp4 and ex1_b_frac(42) ) );
+  lv1x_44: ex1_sh_lv1x_b(44) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(44) ) or (sh1v4dcd1_cp4 and ex1_b_frac(43) ) );
+  lv1x_45: ex1_sh_lv1x_b(45) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(45) ) or (sh1v4dcd1_cp4 and ex1_b_frac(44) ) );
+  lv1x_46: ex1_sh_lv1x_b(46) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(46) ) or (sh1v4dcd1_cp4 and ex1_b_frac(45) ) );
+  lv1x_47: ex1_sh_lv1x_b(47) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(47) ) or (sh1v4dcd1_cp4 and ex1_b_frac(46) ) );
+  lv1x_48: ex1_sh_lv1x_b(48) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(48) ) or (sh1v4dcd1_cp4 and ex1_b_frac(47) ) );
+  lv1x_49: ex1_sh_lv1x_b(49) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(49) ) or (sh1v4dcd1_cp4 and ex1_b_frac(48) ) );
+  lv1x_50: ex1_sh_lv1x_b(50) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(50) ) or (sh1v4dcd1_cp4 and ex1_b_frac(49) ) );
+  lv1x_51: ex1_sh_lv1x_b(51) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(51) ) or (sh1v4dcd1_cp4 and ex1_b_frac(50) ) );
+  lv1x_52: ex1_sh_lv1x_b(52) <= not( (sh1v4dcd0_cp4 and ex1_b_frac(52) ) or (sh1v4dcd1_cp4 and ex1_b_frac(51) ) );
+  lv1x_53: ex1_sh_lv1x_b(53) <= not(                                         sh1v4dcd1_cp4 and ex1_b_frac(52)   );
+
+
+
+  lv1y_02: ex1_sh_lv1y_b(2)  <= not(  sh1v4dcd2_cp1 and ex1_b_frac(0)  ) ;
+  lv1y_03: ex1_sh_lv1y_b(3)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(1)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(0)  ) );
+  lv1y_04: ex1_sh_lv1y_b(4)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(2)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(1)  ) );
+  lv1y_05: ex1_sh_lv1y_b(5)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(3)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(2)  ) );
+  lv1y_06: ex1_sh_lv1y_b(6)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(4)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(3)  ) );
+  lv1y_07: ex1_sh_lv1y_b(7)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(5)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(4)  ) );
+  lv1y_08: ex1_sh_lv1y_b(8)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(6)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(5)  ) );
+  lv1y_09: ex1_sh_lv1y_b(9)  <= not( (sh1v4dcd2_cp1 and ex1_b_frac(7)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(6)  ) );
+  lv1y_10: ex1_sh_lv1y_b(10) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(8)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(7)  ) );
+  lv1y_11: ex1_sh_lv1y_b(11) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(9)  ) or (sh1v4dcd3_cp1 and ex1_b_frac(8)  ) );
+  lv1y_12: ex1_sh_lv1y_b(12) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(10) ) or (sh1v4dcd3_cp1 and ex1_b_frac(9)  ) );
+  lv1y_13: ex1_sh_lv1y_b(13) <= not( (sh1v4dcd2_cp1 and ex1_b_frac(11) ) or (sh1v4dcd3_cp1 and ex1_b_frac(10) ) );
+  lv1y_14: ex1_sh_lv1y_b(14) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(12) ) or (sh1v4dcd3_cp2 and ex1_b_frac(11) ) );
+  lv1y_15: ex1_sh_lv1y_b(15) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(13) ) or (sh1v4dcd3_cp2 and ex1_b_frac(12) ) );
+  lv1y_16: ex1_sh_lv1y_b(16) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(14) ) or (sh1v4dcd3_cp2 and ex1_b_frac(13) ) );
+  lv1y_17: ex1_sh_lv1y_b(17) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(15) ) or (sh1v4dcd3_cp2 and ex1_b_frac(14) ) );
+  lv1y_18: ex1_sh_lv1y_b(18) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(16) ) or (sh1v4dcd3_cp2 and ex1_b_frac(15) ) );
+  lv1y_19: ex1_sh_lv1y_b(19) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(17) ) or (sh1v4dcd3_cp2 and ex1_b_frac(16) ) );
+  lv1y_20: ex1_sh_lv1y_b(20) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(18) ) or (sh1v4dcd3_cp2 and ex1_b_frac(17) ) );
+  lv1y_21: ex1_sh_lv1y_b(21) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(19) ) or (sh1v4dcd3_cp2 and ex1_b_frac(18) ) );
+  lv1y_22: ex1_sh_lv1y_b(22) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(20) ) or (sh1v4dcd3_cp2 and ex1_b_frac(19) ) );
+  lv1y_23: ex1_sh_lv1y_b(23) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(21) ) or (sh1v4dcd3_cp2 and ex1_b_frac(20) ) );
+  lv1y_24: ex1_sh_lv1y_b(24) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(22) ) or (sh1v4dcd3_cp2 and ex1_b_frac(21) ) );
+  lv1y_25: ex1_sh_lv1y_b(25) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(23) ) or (sh1v4dcd3_cp2 and ex1_b_frac(22) ) );
+  lv1y_26: ex1_sh_lv1y_b(26) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(24) ) or (sh1v4dcd3_cp2 and ex1_b_frac(23) ) );
+  lv1y_27: ex1_sh_lv1y_b(27) <= not( (sh1v4dcd2_cp2 and ex1_b_frac(25) ) or (sh1v4dcd3_cp2 and ex1_b_frac(24) ) );
+  lv1y_28: ex1_sh_lv1y_b(28) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(26) ) or (sh1v4dcd3_cp3 and ex1_b_frac(25) ) );
+  lv1y_29: ex1_sh_lv1y_b(29) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(27) ) or (sh1v4dcd3_cp3 and ex1_b_frac(26) ) );
+  lv1y_30: ex1_sh_lv1y_b(30) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(28) ) or (sh1v4dcd3_cp3 and ex1_b_frac(27) ) );
+  lv1y_31: ex1_sh_lv1y_b(31) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(29) ) or (sh1v4dcd3_cp3 and ex1_b_frac(28) ) );
+  lv1y_32: ex1_sh_lv1y_b(32) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(30) ) or (sh1v4dcd3_cp3 and ex1_b_frac(29) ) );
+  lv1y_33: ex1_sh_lv1y_b(33) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(31) ) or (sh1v4dcd3_cp3 and ex1_b_frac(30) ) );
+  lv1y_34: ex1_sh_lv1y_b(34) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(32) ) or (sh1v4dcd3_cp3 and ex1_b_frac(31) ) );
+  lv1y_35: ex1_sh_lv1y_b(35) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(33) ) or (sh1v4dcd3_cp3 and ex1_b_frac(32) ) );
+  lv1y_36: ex1_sh_lv1y_b(36) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(34) ) or (sh1v4dcd3_cp3 and ex1_b_frac(33) ) );
+  lv1y_37: ex1_sh_lv1y_b(37) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(35) ) or (sh1v4dcd3_cp3 and ex1_b_frac(34) ) );
+  lv1y_38: ex1_sh_lv1y_b(38) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(36) ) or (sh1v4dcd3_cp3 and ex1_b_frac(35) ) );
+  lv1y_39: ex1_sh_lv1y_b(39) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(37) ) or (sh1v4dcd3_cp3 and ex1_b_frac(36) ) );
+  lv1y_40: ex1_sh_lv1y_b(40) <= not( (sh1v4dcd2_cp3 and ex1_b_frac(38) ) or (sh1v4dcd3_cp3 and ex1_b_frac(37) ) );
+  lv1y_41: ex1_sh_lv1y_b(41) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(39) ) or (sh1v4dcd3_cp4 and ex1_b_frac(38) ) );
+  lv1y_42: ex1_sh_lv1y_b(42) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(40) ) or (sh1v4dcd3_cp4 and ex1_b_frac(39) ) );
+  lv1y_43: ex1_sh_lv1y_b(43) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(41) ) or (sh1v4dcd3_cp4 and ex1_b_frac(40) ) );
+  lv1y_44: ex1_sh_lv1y_b(44) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(42) ) or (sh1v4dcd3_cp4 and ex1_b_frac(41) ) );
+  lv1y_45: ex1_sh_lv1y_b(45) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(43) ) or (sh1v4dcd3_cp4 and ex1_b_frac(42) ) );
+  lv1y_46: ex1_sh_lv1y_b(46) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(44) ) or (sh1v4dcd3_cp4 and ex1_b_frac(43) ) );
+  lv1y_47: ex1_sh_lv1y_b(47) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(45) ) or (sh1v4dcd3_cp4 and ex1_b_frac(44) ) );
+  lv1y_48: ex1_sh_lv1y_b(48) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(46) ) or (sh1v4dcd3_cp4 and ex1_b_frac(45) ) );
+  lv1y_49: ex1_sh_lv1y_b(49) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(47) ) or (sh1v4dcd3_cp4 and ex1_b_frac(46) ) );
+  lv1y_50: ex1_sh_lv1y_b(50) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(48) ) or (sh1v4dcd3_cp4 and ex1_b_frac(47) ) );
+  lv1y_51: ex1_sh_lv1y_b(51) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(49) ) or (sh1v4dcd3_cp4 and ex1_b_frac(48) ) );
+  lv1y_52: ex1_sh_lv1y_b(52) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(50) ) or (sh1v4dcd3_cp4 and ex1_b_frac(49) ) );
+  lv1y_53: ex1_sh_lv1y_b(53) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(51) ) or (sh1v4dcd3_cp4 and ex1_b_frac(50) ) );
+  lv1y_54: ex1_sh_lv1y_b(54) <= not( (sh1v4dcd2_cp4 and ex1_b_frac(52) ) or (sh1v4dcd3_cp4 and ex1_b_frac(51) ) );
+  lv1y_55: ex1_sh_lv1y_b(55) <= not(                                         sh1v4dcd3_cp4 and ex1_b_frac(52)   );
+  
+  lv1_00: ex1_sh_lv1(0)  <= not( ex1_sh_lv1x_b(0)                         );
+  lv1_01: ex1_sh_lv1(1)  <= not( ex1_sh_lv1x_b(1)                         );
+  lv1_02: ex1_sh_lv1(2)  <= not( ex1_sh_lv1x_b(2)   and ex1_sh_lv1y_b(2)  );
+  lv1_03: ex1_sh_lv1(3)  <= not( ex1_sh_lv1x_b(3)   and ex1_sh_lv1y_b(3)  );
+  lv1_04: ex1_sh_lv1(4)  <= not( ex1_sh_lv1x_b(4)   and ex1_sh_lv1y_b(4)  );
+  lv1_05: ex1_sh_lv1(5)  <= not( ex1_sh_lv1x_b(5)   and ex1_sh_lv1y_b(5)  );
+  lv1_06: ex1_sh_lv1(6)  <= not( ex1_sh_lv1x_b(6)   and ex1_sh_lv1y_b(6)  );
+  lv1_07: ex1_sh_lv1(7)  <= not( ex1_sh_lv1x_b(7)   and ex1_sh_lv1y_b(7)  );
+  lv1_08: ex1_sh_lv1(8)  <= not( ex1_sh_lv1x_b(8)   and ex1_sh_lv1y_b(8)  );
+  lv1_09: ex1_sh_lv1(9)  <= not( ex1_sh_lv1x_b(9)   and ex1_sh_lv1y_b(9)  );
+  lv1_10: ex1_sh_lv1(10) <= not( ex1_sh_lv1x_b(10)  and ex1_sh_lv1y_b(10) );
+  lv1_11: ex1_sh_lv1(11) <= not( ex1_sh_lv1x_b(11)  and ex1_sh_lv1y_b(11) );
+  lv1_12: ex1_sh_lv1(12) <= not( ex1_sh_lv1x_b(12)  and ex1_sh_lv1y_b(12) );
+  lv1_13: ex1_sh_lv1(13) <= not( ex1_sh_lv1x_b(13)  and ex1_sh_lv1y_b(13) );
+  lv1_14: ex1_sh_lv1(14) <= not( ex1_sh_lv1x_b(14)  and ex1_sh_lv1y_b(14) );
+  lv1_15: ex1_sh_lv1(15) <= not( ex1_sh_lv1x_b(15)  and ex1_sh_lv1y_b(15) );
+  lv1_16: ex1_sh_lv1(16) <= not( ex1_sh_lv1x_b(16)  and ex1_sh_lv1y_b(16) );
+  lv1_17: ex1_sh_lv1(17) <= not( ex1_sh_lv1x_b(17)  and ex1_sh_lv1y_b(17) );
+  lv1_18: ex1_sh_lv1(18) <= not( ex1_sh_lv1x_b(18)  and ex1_sh_lv1y_b(18) );
+  lv1_19: ex1_sh_lv1(19) <= not( ex1_sh_lv1x_b(19)  and ex1_sh_lv1y_b(19) );
+  lv1_20: ex1_sh_lv1(20) <= not( ex1_sh_lv1x_b(20)  and ex1_sh_lv1y_b(20) );
+  lv1_21: ex1_sh_lv1(21) <= not( ex1_sh_lv1x_b(21)  and ex1_sh_lv1y_b(21) );
+  lv1_22: ex1_sh_lv1(22) <= not( ex1_sh_lv1x_b(22)  and ex1_sh_lv1y_b(22) );
+  lv1_23: ex1_sh_lv1(23) <= not( ex1_sh_lv1x_b(23)  and ex1_sh_lv1y_b(23) );
+  lv1_24: ex1_sh_lv1(24) <= not( ex1_sh_lv1x_b(24)  and ex1_sh_lv1y_b(24) );
+  lv1_25: ex1_sh_lv1(25) <= not( ex1_sh_lv1x_b(25)  and ex1_sh_lv1y_b(25) );
+  lv1_26: ex1_sh_lv1(26) <= not( ex1_sh_lv1x_b(26)  and ex1_sh_lv1y_b(26) );
+  lv1_27: ex1_sh_lv1(27) <= not( ex1_sh_lv1x_b(27)  and ex1_sh_lv1y_b(27) );
+  lv1_28: ex1_sh_lv1(28) <= not( ex1_sh_lv1x_b(28)  and ex1_sh_lv1y_b(28) );
+  lv1_29: ex1_sh_lv1(29) <= not( ex1_sh_lv1x_b(29)  and ex1_sh_lv1y_b(29) );
+  lv1_30: ex1_sh_lv1(30) <= not( ex1_sh_lv1x_b(30)  and ex1_sh_lv1y_b(30) );
+  lv1_31: ex1_sh_lv1(31) <= not( ex1_sh_lv1x_b(31)  and ex1_sh_lv1y_b(31) );
+  lv1_32: ex1_sh_lv1(32) <= not( ex1_sh_lv1x_b(32)  and ex1_sh_lv1y_b(32) );
+  lv1_33: ex1_sh_lv1(33) <= not( ex1_sh_lv1x_b(33)  and ex1_sh_lv1y_b(33) );
+  lv1_34: ex1_sh_lv1(34) <= not( ex1_sh_lv1x_b(34)  and ex1_sh_lv1y_b(34) );
+  lv1_35: ex1_sh_lv1(35) <= not( ex1_sh_lv1x_b(35)  and ex1_sh_lv1y_b(35) );
+  lv1_36: ex1_sh_lv1(36) <= not( ex1_sh_lv1x_b(36)  and ex1_sh_lv1y_b(36) );
+  lv1_37: ex1_sh_lv1(37) <= not( ex1_sh_lv1x_b(37)  and ex1_sh_lv1y_b(37) );
+  lv1_38: ex1_sh_lv1(38) <= not( ex1_sh_lv1x_b(38)  and ex1_sh_lv1y_b(38) );
+  lv1_39: ex1_sh_lv1(39) <= not( ex1_sh_lv1x_b(39)  and ex1_sh_lv1y_b(39) );
+  lv1_40: ex1_sh_lv1(40) <= not( ex1_sh_lv1x_b(40)  and ex1_sh_lv1y_b(40) );
+  lv1_41: ex1_sh_lv1(41) <= not( ex1_sh_lv1x_b(41)  and ex1_sh_lv1y_b(41) );
+  lv1_42: ex1_sh_lv1(42) <= not( ex1_sh_lv1x_b(42)  and ex1_sh_lv1y_b(42) );
+  lv1_43: ex1_sh_lv1(43) <= not( ex1_sh_lv1x_b(43)  and ex1_sh_lv1y_b(43) );
+  lv1_44: ex1_sh_lv1(44) <= not( ex1_sh_lv1x_b(44)  and ex1_sh_lv1y_b(44) );
+  lv1_45: ex1_sh_lv1(45) <= not( ex1_sh_lv1x_b(45)  and ex1_sh_lv1y_b(45) );
+  lv1_46: ex1_sh_lv1(46) <= not( ex1_sh_lv1x_b(46)  and ex1_sh_lv1y_b(46) );
+  lv1_47: ex1_sh_lv1(47) <= not( ex1_sh_lv1x_b(47)  and ex1_sh_lv1y_b(47) );
+  lv1_48: ex1_sh_lv1(48) <= not( ex1_sh_lv1x_b(48)  and ex1_sh_lv1y_b(48) );
+  lv1_49: ex1_sh_lv1(49) <= not( ex1_sh_lv1x_b(49)  and ex1_sh_lv1y_b(49) );
+  lv1_50: ex1_sh_lv1(50) <= not( ex1_sh_lv1x_b(50)  and ex1_sh_lv1y_b(50) );
+  lv1_51: ex1_sh_lv1(51) <= not( ex1_sh_lv1x_b(51)  and ex1_sh_lv1y_b(51) );
+  lv1_52: ex1_sh_lv1(52) <= not( ex1_sh_lv1x_b(52)  and ex1_sh_lv1y_b(52) );
+  lv1_53: ex1_sh_lv1(53) <= not( ex1_sh_lv1x_b(53)  and ex1_sh_lv1y_b(53) );
+  lv1_54: ex1_sh_lv1(54) <= not(                        ex1_sh_lv1y_b(54) );
+  lv1_55: ex1_sh_lv1(55) <= not(                        ex1_sh_lv1y_b(55) );
+
+
+
+  lv2x_00: ex1_sh_lv2x_b(0)  <= not(  sh2v4dcd00_cp1 and ex1_sh_lv1(0)                                            );
+  lv2x_01: ex1_sh_lv2x_b(1)  <= not(  sh2v4dcd00_cp1 and ex1_sh_lv1(1)                                            );
+  lv2x_02: ex1_sh_lv2x_b(2)  <= not(  sh2v4dcd00_cp1 and ex1_sh_lv1(2)                                            );
+  lv2x_03: ex1_sh_lv2x_b(3)  <= not(  sh2v4dcd00_cp1 and ex1_sh_lv1(3)                                            );
+  lv2x_04: ex1_sh_lv2x_b(4)  <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(4)  ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(0)  ) );
+  lv2x_05: ex1_sh_lv2x_b(5)  <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(5)  ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(1)  ) );
+  lv2x_06: ex1_sh_lv2x_b(6)  <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(6)  ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(2)  ) );
+  lv2x_07: ex1_sh_lv2x_b(7)  <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(7)  ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(3)  ) );
+  lv2x_08: ex1_sh_lv2x_b(8)  <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(8)  ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(4)  ) );
+  lv2x_09: ex1_sh_lv2x_b(9)  <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(9)  ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(5)  ) );
+  lv2x_10: ex1_sh_lv2x_b(10) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(10) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(6)  ) );
+  lv2x_11: ex1_sh_lv2x_b(11) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(11) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(7)  ) );
+  lv2x_12: ex1_sh_lv2x_b(12) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(12) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(8)  ) );
+  lv2x_13: ex1_sh_lv2x_b(13) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(13) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(9)  ) );
+  lv2x_14: ex1_sh_lv2x_b(14) <= not( (sh2v4dcd00_cp1 and ex1_sh_lv1(14) ) or (sh2v4dcd04_cp1 and ex1_sh_lv1(10) ) );
+  lv2x_15: ex1_sh_lv2x_b(15) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(15) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(11) ) );
+  lv2x_16: ex1_sh_lv2x_b(16) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(16) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(12) ) );
+  lv2x_17: ex1_sh_lv2x_b(17) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(17) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(13) ) );
+  lv2x_18: ex1_sh_lv2x_b(18) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(18) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(14) ) );
+  lv2x_19: ex1_sh_lv2x_b(19) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(19) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(15) ) );
+  lv2x_20: ex1_sh_lv2x_b(20) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(20) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(16) ) ); 
+  lv2x_21: ex1_sh_lv2x_b(21) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(21) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(17) ) );
+  lv2x_22: ex1_sh_lv2x_b(22) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(22) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(18) ) );
+  lv2x_23: ex1_sh_lv2x_b(23) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(23) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(19) ) );
+  lv2x_24: ex1_sh_lv2x_b(24) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(24) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(20) ) );
+  lv2x_25: ex1_sh_lv2x_b(25) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(25) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(21) ) );
+  lv2x_26: ex1_sh_lv2x_b(26) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(26) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(22) ) );
+  lv2x_27: ex1_sh_lv2x_b(27) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(27) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(23) ) );
+  lv2x_28: ex1_sh_lv2x_b(28) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(28) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(24) ) );
+  lv2x_29: ex1_sh_lv2x_b(29) <= not( (sh2v4dcd00_cp2 and ex1_sh_lv1(29) ) or (sh2v4dcd04_cp2 and ex1_sh_lv1(25) ) );
+  lv2x_30: ex1_sh_lv2x_b(30) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(30) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(26) ) );
+  lv2x_31: ex1_sh_lv2x_b(31) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(31) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(27) ) );
+  lv2x_32: ex1_sh_lv2x_b(32) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(32) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(28) ) );
+  lv2x_33: ex1_sh_lv2x_b(33) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(33) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(29) ) );
+  lv2x_34: ex1_sh_lv2x_b(34) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(34) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(30) ) );
+  lv2x_35: ex1_sh_lv2x_b(35) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(35) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(31) ) );
+  lv2x_36: ex1_sh_lv2x_b(36) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(36) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(32) ) );
+  lv2x_37: ex1_sh_lv2x_b(37) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(37) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(33) ) );
+  lv2x_38: ex1_sh_lv2x_b(38) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(38) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(34) ) );
+  lv2x_39: ex1_sh_lv2x_b(39) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(39) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(35) ) );
+  lv2x_40: ex1_sh_lv2x_b(40) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(40) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(36) ) );
+  lv2x_41: ex1_sh_lv2x_b(41) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(41) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(37) ) );
+  lv2x_42: ex1_sh_lv2x_b(42) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(42) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(38) ) );
+  lv2x_43: ex1_sh_lv2x_b(43) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(43) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(39) ) );
+  lv2x_44: ex1_sh_lv2x_b(44) <= not( (sh2v4dcd00_cp3 and ex1_sh_lv1(44) ) or (sh2v4dcd04_cp3 and ex1_sh_lv1(40) ) );
+  lv2x_45: ex1_sh_lv2x_b(45) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(45) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(41) ) );
+  lv2x_46: ex1_sh_lv2x_b(46) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(46) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(42) ) );
+  lv2x_47: ex1_sh_lv2x_b(47) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(47) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(43) ) );
+  lv2x_48: ex1_sh_lv2x_b(48) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(48) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(44) ) );
+  lv2x_49: ex1_sh_lv2x_b(49) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(49) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(45) ) );
+  lv2x_50: ex1_sh_lv2x_b(50) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(50) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(46) ) );
+  lv2x_51: ex1_sh_lv2x_b(51) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(51) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(47) ) );
+  lv2x_52: ex1_sh_lv2x_b(52) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(52) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(48) ) );
+  lv2x_53: ex1_sh_lv2x_b(53) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(53) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(49) ) );
+  lv2x_54: ex1_sh_lv2x_b(54) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(54) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(50) ) );
+  lv2x_55: ex1_sh_lv2x_b(55) <= not( (sh2v4dcd00_cp4 and ex1_sh_lv1(55) ) or (sh2v4dcd04_cp4 and ex1_sh_lv1(51) ) );
+  lv2x_56: ex1_sh_lv2x_b(56) <= not(                                          sh2v4dcd04_cp4 and ex1_sh_lv1(52)   );
+  lv2x_57: ex1_sh_lv2x_b(57) <= not(                                          sh2v4dcd04_cp4 and ex1_sh_lv1(53)   );
+  lv2x_58: ex1_sh_lv2x_b(58) <= not(                                          sh2v4dcd04_cp4 and ex1_sh_lv1(54)   );
+  lv2x_59: ex1_sh_lv2x_b(59) <= not(                                          sh2v4dcd04_cp4 and ex1_sh_lv1(55)   );
+
+
+
+  lv2y_08: ex1_sh_lv2y_b(8)  <= not(  sh2v4dcd08_cp1 and ex1_sh_lv1(0)                                            );
+  lv2y_09: ex1_sh_lv2y_b(9)  <= not(  sh2v4dcd08_cp1 and ex1_sh_lv1(1)                                            );
+  lv2y_10: ex1_sh_lv2y_b(10) <= not(  sh2v4dcd08_cp1 and ex1_sh_lv1(2)                                            );
+  lv2y_11: ex1_sh_lv2y_b(11) <= not(  sh2v4dcd08_cp1 and ex1_sh_lv1(3)                                            );
+  lv2y_12: ex1_sh_lv2y_b(12) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(4)  ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(0)  ) );
+  lv2y_13: ex1_sh_lv2y_b(13) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(5)  ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(1)  ) );
+  lv2y_14: ex1_sh_lv2y_b(14) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(6)  ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(2)  ) );
+  lv2y_15: ex1_sh_lv2y_b(15) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(7)  ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(3)  ) );
+  lv2y_16: ex1_sh_lv2y_b(16) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(8)  ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(4)  ) );
+  lv2y_17: ex1_sh_lv2y_b(17) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(9)  ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(5)  ) );
+  lv2y_18: ex1_sh_lv2y_b(18) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(10) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(6)  ) );
+  lv2y_19: ex1_sh_lv2y_b(19) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(11) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(7)  ) );
+  lv2y_20: ex1_sh_lv2y_b(20) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(12) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(8)  ) );
+  lv2y_21: ex1_sh_lv2y_b(21) <= not( (sh2v4dcd08_cp1 and ex1_sh_lv1(13) ) or (sh2v4dcd12_cp1 and ex1_sh_lv1(9)  ) );
+  lv2y_22: ex1_sh_lv2y_b(22) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(14) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(10) ) );
+  lv2y_23: ex1_sh_lv2y_b(23) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(15) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(11) ) );
+  lv2y_24: ex1_sh_lv2y_b(24) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(16) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(12) ) );
+  lv2y_25: ex1_sh_lv2y_b(25) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(17) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(13) ) );
+  lv2y_26: ex1_sh_lv2y_b(26) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(18) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(14) ) );
+  lv2y_27: ex1_sh_lv2y_b(27) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(19) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(15) ) );
+  lv2y_28: ex1_sh_lv2y_b(28) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(20) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(16) ) ); 
+  lv2y_29: ex1_sh_lv2y_b(29) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(21) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(17) ) );
+  lv2y_30: ex1_sh_lv2y_b(30) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(22) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(18) ) );
+  lv2y_31: ex1_sh_lv2y_b(31) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(23) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(19) ) );
+  lv2y_32: ex1_sh_lv2y_b(32) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(24) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(20) ) );
+  lv2y_33: ex1_sh_lv2y_b(33) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(25) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(21) ) );
+  lv2y_34: ex1_sh_lv2y_b(34) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(26) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(22) ) );
+  lv2y_35: ex1_sh_lv2y_b(35) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(27) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(23) ) );
+  lv2y_36: ex1_sh_lv2y_b(36) <= not( (sh2v4dcd08_cp2 and ex1_sh_lv1(28) ) or (sh2v4dcd12_cp2 and ex1_sh_lv1(24) ) );
+  lv2y_37: ex1_sh_lv2y_b(37) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(29) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(25) ) );
+  lv2y_38: ex1_sh_lv2y_b(38) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(30) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(26) ) );
+  lv2y_39: ex1_sh_lv2y_b(39) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(31) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(27) ) );
+  lv2y_40: ex1_sh_lv2y_b(40) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(32) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(28) ) );
+  lv2y_41: ex1_sh_lv2y_b(41) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(33) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(29) ) );
+  lv2y_42: ex1_sh_lv2y_b(42) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(34) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(30) ) );
+  lv2y_43: ex1_sh_lv2y_b(43) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(35) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(31) ) );
+  lv2y_44: ex1_sh_lv2y_b(44) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(36) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(32) ) );
+  lv2y_45: ex1_sh_lv2y_b(45) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(37) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(33) ) );
+  lv2y_46: ex1_sh_lv2y_b(46) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(38) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(34) ) );
+  lv2y_47: ex1_sh_lv2y_b(47) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(39) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(35) ) );
+  lv2y_48: ex1_sh_lv2y_b(48) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(40) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(36) ) );
+  lv2y_49: ex1_sh_lv2y_b(49) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(41) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(37) ) );
+  lv2y_50: ex1_sh_lv2y_b(50) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(42) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(38) ) );
+  lv2y_51: ex1_sh_lv2y_b(51) <= not( (sh2v4dcd08_cp3 and ex1_sh_lv1(43) ) or (sh2v4dcd12_cp3 and ex1_sh_lv1(39) ) );
+  lv2y_52: ex1_sh_lv2y_b(52) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(44) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(40) ) );
+  lv2y_53: ex1_sh_lv2y_b(53) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(45) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(41) ) );
+  lv2y_54: ex1_sh_lv2y_b(54) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(46) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(42) ) );
+  lv2y_55: ex1_sh_lv2y_b(55) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(47) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(43) ) );
+  lv2y_56: ex1_sh_lv2y_b(56) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(48) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(44) ) );
+  lv2y_57: ex1_sh_lv2y_b(57) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(49) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(45) ) );
+  lv2y_58: ex1_sh_lv2y_b(58) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(50) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(46) ) );
+  lv2y_59: ex1_sh_lv2y_b(59) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(51) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(47) ) );
+  lv2y_60: ex1_sh_lv2y_b(60) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(52) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(48) ) );
+  lv2y_61: ex1_sh_lv2y_b(61) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(53) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(49) ) );
+  lv2y_62: ex1_sh_lv2y_b(62) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(54) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(50) ) );
+  lv2y_63: ex1_sh_lv2y_b(63) <= not( (sh2v4dcd08_cp4 and ex1_sh_lv1(55) ) or (sh2v4dcd12_cp4 and ex1_sh_lv1(51) ) );
+  lv2y_64: ex1_sh_lv2y_b(64) <= not(                                          sh2v4dcd12_cp4 and ex1_sh_lv1(52)   );
+  lv2y_65: ex1_sh_lv2y_b(65) <= not(                                          sh2v4dcd12_cp4 and ex1_sh_lv1(53)   );
+  lv2y_66: ex1_sh_lv2y_b(66) <= not(                                          sh2v4dcd12_cp4 and ex1_sh_lv1(54)   );
+  lv2y_67: ex1_sh_lv2y_b(67) <= not(                                          sh2v4dcd12_cp4 and ex1_sh_lv1(55)   );
+
+
+  lv2z_00: ex1_sh_lv2z_b( 0) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 0) );
+  lv2z_01: ex1_sh_lv2z_b( 1) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 1) );
+  lv2z_02: ex1_sh_lv2z_b( 2) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 2) );
+  lv2z_03: ex1_sh_lv2z_b( 3) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 3) );
+  lv2z_04: ex1_sh_lv2z_b( 4) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 4) );
+  lv2z_05: ex1_sh_lv2z_b( 5) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 5) );
+  lv2z_06: ex1_sh_lv2z_b( 6) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 6) );
+  lv2z_07: ex1_sh_lv2z_b( 7) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 7) );
+  lv2z_08: ex1_sh_lv2z_b( 8) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 8) );
+  lv2z_09: ex1_sh_lv2z_b( 9) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid( 9) );
+  lv2z_10: ex1_sh_lv2z_b(10) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(10) );
+  lv2z_11: ex1_sh_lv2z_b(11) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(11) );
+  lv2z_12: ex1_sh_lv2z_b(12) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(12) );
+  lv2z_13: ex1_sh_lv2z_b(13) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(13) );
+  lv2z_14: ex1_sh_lv2z_b(14) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(14) );
+  lv2z_15: ex1_sh_lv2z_b(15) <= not( sh2v4dcdpp_cp1 and ex1_special_fcfid(15) );
+  lv2z_16: ex1_sh_lv2z_b(16) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(16) );
+  lv2z_17: ex1_sh_lv2z_b(17) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(17) );
+  lv2z_18: ex1_sh_lv2z_b(18) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(18) );
+  lv2z_19: ex1_sh_lv2z_b(19) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(19) );
+  lv2z_20: ex1_sh_lv2z_b(20) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(20) );
+  lv2z_21: ex1_sh_lv2z_b(21) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(21) );
+  lv2z_22: ex1_sh_lv2z_b(22) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(22) );
+  lv2z_23: ex1_sh_lv2z_b(23) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(23) );
+  lv2z_24: ex1_sh_lv2z_b(24) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(24) );
+  lv2z_25: ex1_sh_lv2z_b(25) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(25) );
+  lv2z_26: ex1_sh_lv2z_b(26) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(26) );
+  lv2z_27: ex1_sh_lv2z_b(27) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(27) );
+  lv2z_28: ex1_sh_lv2z_b(28) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(28) );
+  lv2z_29: ex1_sh_lv2z_b(29) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(29) );
+  lv2z_30: ex1_sh_lv2z_b(30) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(30) );
+  lv2z_31: ex1_sh_lv2z_b(31) <= not( sh2v4dcdpp_cp2 and ex1_special_fcfid(31) );
+  lv2z_32: ex1_sh_lv2z_b(32) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(32) );
+  lv2z_33: ex1_sh_lv2z_b(33) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(33) );
+  lv2z_34: ex1_sh_lv2z_b(34) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(34) );
+  lv2z_35: ex1_sh_lv2z_b(35) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(35) );
+  lv2z_36: ex1_sh_lv2z_b(36) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(36) );
+  lv2z_37: ex1_sh_lv2z_b(37) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(37) );
+  lv2z_38: ex1_sh_lv2z_b(38) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(38) );
+  lv2z_39: ex1_sh_lv2z_b(39) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(39) );
+  lv2z_40: ex1_sh_lv2z_b(40) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(40) );
+  lv2z_41: ex1_sh_lv2z_b(41) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(41) );
+  lv2z_42: ex1_sh_lv2z_b(42) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(42) );
+  lv2z_43: ex1_sh_lv2z_b(43) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(43) );
+  lv2z_44: ex1_sh_lv2z_b(44) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(44) );
+  lv2z_45: ex1_sh_lv2z_b(45) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(45) );
+  lv2z_46: ex1_sh_lv2z_b(46) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(46) );
+  lv2z_47: ex1_sh_lv2z_b(47) <= not( sh2v4dcdpp_cp3 and ex1_special_fcfid(47) );
+  lv2z_48: ex1_sh_lv2z_b(48) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(48) );
+  lv2z_49: ex1_sh_lv2z_b(49) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(49) );
+  lv2z_50: ex1_sh_lv2z_b(50) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(50) );
+  lv2z_51: ex1_sh_lv2z_b(51) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(51) );
+  lv2z_52: ex1_sh_lv2z_b(52) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(52) );
+  lv2z_53: ex1_sh_lv2z_b(53) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(53) );
+  lv2z_54: ex1_sh_lv2z_b(54) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(54) );
+  lv2z_55: ex1_sh_lv2z_b(55) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(55) );
+  lv2z_56: ex1_sh_lv2z_b(56) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(56) );
+  lv2z_57: ex1_sh_lv2z_b(57) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(57) );
+  lv2z_58: ex1_sh_lv2z_b(58) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(58) );
+  lv2z_59: ex1_sh_lv2z_b(59) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(59) );
+  lv2z_60: ex1_sh_lv2z_b(60) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(60) );
+  lv2z_61: ex1_sh_lv2z_b(61) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(61) );
+  lv2z_62: ex1_sh_lv2z_b(62) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(62) );
+  lv2z_63: ex1_sh_lv2z_b(63) <= not( sh2v4dcdpp_cp4 and ex1_special_fcfid(63) );
+
+
+
+  lv2_00: ex1_sh_lvl2(00) <= not( ex1_sh_lv2x_b(00) and                       ex1_sh_lv2z_b(00) ) ; 
+  lv2_01: ex1_sh_lvl2(01) <= not( ex1_sh_lv2x_b(01) and                       ex1_sh_lv2z_b(01) ) ; 
+  lv2_02: ex1_sh_lvl2(02) <= not( ex1_sh_lv2x_b(02) and                       ex1_sh_lv2z_b(02) ) ; 
+  lv2_03: ex1_sh_lvl2(03) <= not( ex1_sh_lv2x_b(03) and                       ex1_sh_lv2z_b(03) ) ; 
+  lv2_04: ex1_sh_lvl2(04) <= not( ex1_sh_lv2x_b(04) and                       ex1_sh_lv2z_b(04) ) ; 
+  lv2_05: ex1_sh_lvl2(05) <= not( ex1_sh_lv2x_b(05) and                       ex1_sh_lv2z_b(05) ) ; 
+  lv2_06: ex1_sh_lvl2(06) <= not( ex1_sh_lv2x_b(06) and                       ex1_sh_lv2z_b(06) ) ; 
+  lv2_07: ex1_sh_lvl2(07) <= not( ex1_sh_lv2x_b(07) and                       ex1_sh_lv2z_b(07) ) ; 
+  lv2_08: ex1_sh_lvl2(08) <= not( ex1_sh_lv2x_b(08) and ex1_sh_lv2y_b(08) and ex1_sh_lv2z_b(08) ) ; 
+  lv2_09: ex1_sh_lvl2(09) <= not( ex1_sh_lv2x_b(09) and ex1_sh_lv2y_b(09) and ex1_sh_lv2z_b(09) ) ; 
+  lv2_10: ex1_sh_lvl2(10) <= not( ex1_sh_lv2x_b(10) and ex1_sh_lv2y_b(10) and ex1_sh_lv2z_b(10) ) ; 
+  lv2_11: ex1_sh_lvl2(11) <= not( ex1_sh_lv2x_b(11) and ex1_sh_lv2y_b(11) and ex1_sh_lv2z_b(11) ) ; 
+  lv2_12: ex1_sh_lvl2(12) <= not( ex1_sh_lv2x_b(12) and ex1_sh_lv2y_b(12) and ex1_sh_lv2z_b(12) ) ; 
+  lv2_13: ex1_sh_lvl2(13) <= not( ex1_sh_lv2x_b(13) and ex1_sh_lv2y_b(13) and ex1_sh_lv2z_b(13) ) ; 
+  lv2_14: ex1_sh_lvl2(14) <= not( ex1_sh_lv2x_b(14) and ex1_sh_lv2y_b(14) and ex1_sh_lv2z_b(14) ) ; 
+  lv2_15: ex1_sh_lvl2(15) <= not( ex1_sh_lv2x_b(15) and ex1_sh_lv2y_b(15) and ex1_sh_lv2z_b(15) ) ; 
+  lv2_16: ex1_sh_lvl2(16) <= not( ex1_sh_lv2x_b(16) and ex1_sh_lv2y_b(16) and ex1_sh_lv2z_b(16) ) ; 
+  lv2_17: ex1_sh_lvl2(17) <= not( ex1_sh_lv2x_b(17) and ex1_sh_lv2y_b(17) and ex1_sh_lv2z_b(17) ) ; 
+  lv2_18: ex1_sh_lvl2(18) <= not( ex1_sh_lv2x_b(18) and ex1_sh_lv2y_b(18) and ex1_sh_lv2z_b(18) ) ; 
+  lv2_19: ex1_sh_lvl2(19) <= not( ex1_sh_lv2x_b(19) and ex1_sh_lv2y_b(19) and ex1_sh_lv2z_b(19) ) ; 
+  lv2_20: ex1_sh_lvl2(20) <= not( ex1_sh_lv2x_b(20) and ex1_sh_lv2y_b(20) and ex1_sh_lv2z_b(20) ) ; 
+  lv2_21: ex1_sh_lvl2(21) <= not( ex1_sh_lv2x_b(21) and ex1_sh_lv2y_b(21) and ex1_sh_lv2z_b(21) ) ; 
+  lv2_22: ex1_sh_lvl2(22) <= not( ex1_sh_lv2x_b(22) and ex1_sh_lv2y_b(22) and ex1_sh_lv2z_b(22) ) ; 
+  lv2_23: ex1_sh_lvl2(23) <= not( ex1_sh_lv2x_b(23) and ex1_sh_lv2y_b(23) and ex1_sh_lv2z_b(23) ) ; 
+  lv2_24: ex1_sh_lvl2(24) <= not( ex1_sh_lv2x_b(24) and ex1_sh_lv2y_b(24) and ex1_sh_lv2z_b(24) ) ; 
+  lv2_25: ex1_sh_lvl2(25) <= not( ex1_sh_lv2x_b(25) and ex1_sh_lv2y_b(25) and ex1_sh_lv2z_b(25) ) ; 
+  lv2_26: ex1_sh_lvl2(26) <= not( ex1_sh_lv2x_b(26) and ex1_sh_lv2y_b(26) and ex1_sh_lv2z_b(26) ) ; 
+  lv2_27: ex1_sh_lvl2(27) <= not( ex1_sh_lv2x_b(27) and ex1_sh_lv2y_b(27) and ex1_sh_lv2z_b(27) ) ; 
+  lv2_28: ex1_sh_lvl2(28) <= not( ex1_sh_lv2x_b(28) and ex1_sh_lv2y_b(28) and ex1_sh_lv2z_b(28) ) ; 
+  lv2_29: ex1_sh_lvl2(29) <= not( ex1_sh_lv2x_b(29) and ex1_sh_lv2y_b(29) and ex1_sh_lv2z_b(29) ) ; 
+  lv2_30: ex1_sh_lvl2(30) <= not( ex1_sh_lv2x_b(30) and ex1_sh_lv2y_b(30) and ex1_sh_lv2z_b(30) ) ; 
+  lv2_31: ex1_sh_lvl2(31) <= not( ex1_sh_lv2x_b(31) and ex1_sh_lv2y_b(31) and ex1_sh_lv2z_b(31) ) ; 
+  lv2_32: ex1_sh_lvl2(32) <= not( ex1_sh_lv2x_b(32) and ex1_sh_lv2y_b(32) and ex1_sh_lv2z_b(32) ) ; 
+  lv2_33: ex1_sh_lvl2(33) <= not( ex1_sh_lv2x_b(33) and ex1_sh_lv2y_b(33) and ex1_sh_lv2z_b(33) ) ; 
+  lv2_34: ex1_sh_lvl2(34) <= not( ex1_sh_lv2x_b(34) and ex1_sh_lv2y_b(34) and ex1_sh_lv2z_b(34) ) ; 
+  lv2_35: ex1_sh_lvl2(35) <= not( ex1_sh_lv2x_b(35) and ex1_sh_lv2y_b(35) and ex1_sh_lv2z_b(35) ) ; 
+  lv2_36: ex1_sh_lvl2(36) <= not( ex1_sh_lv2x_b(36) and ex1_sh_lv2y_b(36) and ex1_sh_lv2z_b(36) ) ; 
+  lv2_37: ex1_sh_lvl2(37) <= not( ex1_sh_lv2x_b(37) and ex1_sh_lv2y_b(37) and ex1_sh_lv2z_b(37) ) ; 
+  lv2_38: ex1_sh_lvl2(38) <= not( ex1_sh_lv2x_b(38) and ex1_sh_lv2y_b(38) and ex1_sh_lv2z_b(38) ) ; 
+  lv2_39: ex1_sh_lvl2(39) <= not( ex1_sh_lv2x_b(39) and ex1_sh_lv2y_b(39) and ex1_sh_lv2z_b(39) ) ; 
+  lv2_40: ex1_sh_lvl2(40) <= not( ex1_sh_lv2x_b(40) and ex1_sh_lv2y_b(40) and ex1_sh_lv2z_b(40) ) ; 
+  lv2_41: ex1_sh_lvl2(41) <= not( ex1_sh_lv2x_b(41) and ex1_sh_lv2y_b(41) and ex1_sh_lv2z_b(41) ) ; 
+  lv2_42: ex1_sh_lvl2(42) <= not( ex1_sh_lv2x_b(42) and ex1_sh_lv2y_b(42) and ex1_sh_lv2z_b(42) ) ; 
+  lv2_43: ex1_sh_lvl2(43) <= not( ex1_sh_lv2x_b(43) and ex1_sh_lv2y_b(43) and ex1_sh_lv2z_b(43) ) ; 
+  lv2_44: ex1_sh_lvl2(44) <= not( ex1_sh_lv2x_b(44) and ex1_sh_lv2y_b(44) and ex1_sh_lv2z_b(44) ) ; 
+  lv2_45: ex1_sh_lvl2(45) <= not( ex1_sh_lv2x_b(45) and ex1_sh_lv2y_b(45) and ex1_sh_lv2z_b(45) ) ; 
+  lv2_46: ex1_sh_lvl2(46) <= not( ex1_sh_lv2x_b(46) and ex1_sh_lv2y_b(46) and ex1_sh_lv2z_b(46) ) ; 
+  lv2_47: ex1_sh_lvl2(47) <= not( ex1_sh_lv2x_b(47) and ex1_sh_lv2y_b(47) and ex1_sh_lv2z_b(47) ) ; 
+  lv2_48: ex1_sh_lvl2(48) <= not( ex1_sh_lv2x_b(48) and ex1_sh_lv2y_b(48) and ex1_sh_lv2z_b(48) ) ; 
+  lv2_49: ex1_sh_lvl2(49) <= not( ex1_sh_lv2x_b(49) and ex1_sh_lv2y_b(49) and ex1_sh_lv2z_b(49) ) ; 
+  lv2_50: ex1_sh_lvl2(50) <= not( ex1_sh_lv2x_b(50) and ex1_sh_lv2y_b(50) and ex1_sh_lv2z_b(50) ) ; 
+  lv2_51: ex1_sh_lvl2(51) <= not( ex1_sh_lv2x_b(51) and ex1_sh_lv2y_b(51) and ex1_sh_lv2z_b(51) ) ; 
+  lv2_52: ex1_sh_lvl2(52) <= not( ex1_sh_lv2x_b(52) and ex1_sh_lv2y_b(52) and ex1_sh_lv2z_b(52) ) ; 
+  lv2_53: ex1_sh_lvl2(53) <= not( ex1_sh_lv2x_b(53) and ex1_sh_lv2y_b(53) and ex1_sh_lv2z_b(53) ) ; 
+  lv2_54: ex1_sh_lvl2(54) <= not( ex1_sh_lv2x_b(54) and ex1_sh_lv2y_b(54) and ex1_sh_lv2z_b(54) ) ; 
+  lv2_55: ex1_sh_lvl2(55) <= not( ex1_sh_lv2x_b(55) and ex1_sh_lv2y_b(55) and ex1_sh_lv2z_b(55) ) ; 
+  lv2_56: ex1_sh_lvl2(56) <= not( ex1_sh_lv2x_b(56) and ex1_sh_lv2y_b(56) and ex1_sh_lv2z_b(56) ) ; 
+  lv2_57: ex1_sh_lvl2(57) <= not( ex1_sh_lv2x_b(57) and ex1_sh_lv2y_b(57) and ex1_sh_lv2z_b(57) ) ; 
+  lv2_58: ex1_sh_lvl2(58) <= not( ex1_sh_lv2x_b(58) and ex1_sh_lv2y_b(58) and ex1_sh_lv2z_b(58) ) ; 
+  lv2_59: ex1_sh_lvl2(59) <= not( ex1_sh_lv2x_b(59) and ex1_sh_lv2y_b(59) and ex1_sh_lv2z_b(59) ) ; 
+  lv2_60: ex1_sh_lvl2(60) <= not(                       ex1_sh_lv2y_b(60) and ex1_sh_lv2z_b(60) ) ; 
+  lv2_61: ex1_sh_lvl2(61) <= not(                       ex1_sh_lv2y_b(61) and ex1_sh_lv2z_b(61) ) ; 
+  lv2_62: ex1_sh_lvl2(62) <= not(                       ex1_sh_lv2y_b(62) and ex1_sh_lv2z_b(62) ) ; 
+  lv2_63: ex1_sh_lvl2(63) <= not(                       ex1_sh_lv2y_b(63) and ex1_sh_lv2z_b(63) ) ; 
+  lv2_64: ex1_sh_lvl2(64) <= not(                       ex1_sh_lv2y_b(64)                       ) ; 
+  lv2_65: ex1_sh_lvl2(65) <= not(                       ex1_sh_lv2y_b(65)                       ) ; 
+  lv2_66: ex1_sh_lvl2(66) <= not(                       ex1_sh_lv2y_b(66)                       ) ; 
+  lv2_67: ex1_sh_lvl2(67) <= not(                       ex1_sh_lv2y_b(67)                       ) ;
+
+
+
+end; 
+                
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_cr2.vhdl

@@ -0,0 +1,751 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+  
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+
+              
+ 
+entity fuq_cr2 is 
+generic(       expand_type               : integer := 2  ); 
+port( 
+
+       vdd                                       :inout power_logic;
+       gnd                                       :inout power_logic;
+       clkoff_b                                  :in   std_ulogic; 
+       act_dis                                   :in   std_ulogic; 
+       flush                                     :in   std_ulogic; 
+       delay_lclkr                               :in   std_ulogic_vector(1 to 7); 
+       mpw1_b                                    :in   std_ulogic_vector(1 to 7); 
+       mpw2_b                                    :in   std_ulogic_vector(0 to 1); 
+       sg_1                                      :in   std_ulogic;
+       thold_1                                   :in   std_ulogic;
+       fpu_enable                                :in   std_ulogic; 
+       nclk                                      :in   clk_logic;
+
+
+       f_cr2_si                                 :in   std_ulogic                   ;
+       f_cr2_so                                 :out  std_ulogic                   ;
+       rf1_act                                  :in   std_ulogic                   ;
+       ex1_act                                  :in   std_ulogic                   ;
+       rf1_thread_b                             :in   std_ulogic_vector(0 to 3)    ;
+       f_dcd_ex6_cancel                         :in   std_ulogic                   ;
+
+       f_fmt_ex1_bop_byt                        :in  std_ulogic_vector(45 to 52); 
+       f_dcd_rf1_fpscr_bit_data_b               :in  std_ulogic_vector(0 to 3);   
+       f_dcd_rf1_fpscr_bit_mask_b               :in  std_ulogic_vector(0 to 3);   
+       f_dcd_rf1_fpscr_nib_mask_b               :in  std_ulogic_vector(0 to 8);   
+       f_dcd_rf1_mtfsbx_b                       :in  std_ulogic;                  
+       f_dcd_rf1_mcrfs_b                        :in  std_ulogic;                  
+       f_dcd_rf1_mtfsf_b                        :in  std_ulogic;                  
+       f_dcd_rf1_mtfsfi_b                       :in  std_ulogic;                  
+
+       f_cr2_ex3_thread_b                       :out  std_ulogic_vector(0 to 3)  ;
+       f_cr2_ex3_fpscr_bit_data_b               :out std_ulogic_vector(0 to 3);   
+       f_cr2_ex3_fpscr_bit_mask_b               :out std_ulogic_vector(0 to 3);   
+       f_cr2_ex3_fpscr_nib_mask_b               :out std_ulogic_vector(0 to 8);   
+       f_cr2_ex3_mtfsbx_b                       :out std_ulogic;                  
+       f_cr2_ex3_mcrfs_b                        :out std_ulogic;                  
+       f_cr2_ex3_mtfsf_b                        :out std_ulogic;                  
+       f_cr2_ex3_mtfsfi_b                       :out std_ulogic;                  
+
+       f_cr2_ex5_fpscr_rd_dat                   :out  std_ulogic_vector(24 to 31); 
+       f_cr2_ex6_fpscr_rd_dat                   :out  std_ulogic_vector(24 to 31); 
+       f_cr2_ex1_fpscr_shadow                   :out  std_ulogic_vector(0 to 7)    
+
+
+); 
+ 
+ 
+
+end fuq_cr2; 
+ 
+ 
+architecture fuq_cr2 of fuq_cr2 is 
+ 
+  constant tiup :std_ulogic := '1';
+  constant tidn :std_ulogic := '0';
+ 
+ signal sg_0   :std_ulogic  ;
+ signal thold_0_b , thold_0, forcee  :std_ulogic  ;
+ signal ex6_th0_act  :std_ulogic  ;
+ signal ex6_th1_act  :std_ulogic  ;
+ signal ex6_th2_act  :std_ulogic  ;
+ signal ex6_th3_act  :std_ulogic  ;
+ signal ex2_act   :std_ulogic  ;
+ signal ex3_act   :std_ulogic  ;
+ signal ex4_act, ex5_act, ex6_act :std_ulogic  ;
+ signal ex4_mv_to_op  :std_ulogic  ;
+ signal ex5_mv_to_op  :std_ulogic  ;
+ signal ex6_mv_to_op  :std_ulogic  ;
+ 
+ signal ex1_thread   :std_ulogic_vector(0 to 3) ;
+ signal ex2_thread   :std_ulogic_vector(0 to 3) ;
+ signal ex3_thread   :std_ulogic_vector(0 to 3) ;
+ signal ex4_thread   :std_ulogic_vector(0 to 3) ;
+ signal ex5_thread   :std_ulogic_vector(0 to 3) ;
+ signal ex6_thread   :std_ulogic_vector(0 to 3) ;
+ signal act_spare_unused  :std_ulogic_vector(0 to 2) ;
+ signal act_so   , act_si     :std_ulogic_vector(0 to 6) ;
+ signal ex1_ctl_so   , ex1_ctl_si    :std_ulogic_vector(0 to 33) ;
+ signal ex2_ctl_so   , ex2_ctl_si    :std_ulogic_vector(0 to 24) ;
+ signal ex3_ctl_so   , ex3_ctl_si    :std_ulogic_vector(0 to 24) ;
+ signal ex4_ctl_so   , ex4_ctl_si    :std_ulogic_vector(0 to 4) ;
+ signal ex5_ctl_so   , ex5_ctl_si    :std_ulogic_vector(0 to 4) ;
+ signal ex6_ctl_so   , ex6_ctl_si    :std_ulogic_vector(0 to 4) ;
+ signal shadow0_so   , shadow0_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow1_so   , shadow1_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow2_so   , shadow2_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow3_so   , shadow3_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp2_so   , shadow_byp2_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp3_so   , shadow_byp3_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp4_so   , shadow_byp4_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp5_so   , shadow_byp5_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp6_so   , shadow_byp6_si    :std_ulogic_vector(0 to 7) ;
+ signal shadow0 :std_ulogic_vector(0 to 7) ;
+ signal shadow1 :std_ulogic_vector(0 to 7) ;
+ signal shadow2 :std_ulogic_vector(0 to 7) ;
+ signal shadow3 :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp2 :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp3 :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp4 :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp5 :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp6 :std_ulogic_vector(0 to 7) ;
+ signal shadow_byp2_din  :std_ulogic_vector(0 to 7) ;
+
+ signal ex1_bit_sel  :std_ulogic_vector(0 to 7) ;
+ signal ex1_fpscr_bit_data  :std_ulogic_vector(0 to 3);
+ signal ex1_fpscr_bit_mask  :std_ulogic_vector(0 to 3);
+ signal ex1_fpscr_nib_mask  :std_ulogic_vector(0 to 8);
+ signal ex1_mtfsbx   :std_ulogic;
+ signal ex1_mcrfs   :std_ulogic;
+ signal ex1_mtfsf   :std_ulogic;
+ signal ex1_mtfsfi   :std_ulogic;
+ signal ex2_fpscr_bit_data  :std_ulogic_vector(0 to 3);
+ signal ex2_fpscr_bit_mask  :std_ulogic_vector(0 to 3);
+ signal ex2_fpscr_nib_mask  :std_ulogic_vector(0 to 8);
+ signal ex2_mtfsbx   :std_ulogic;
+ signal ex2_mcrfs   :std_ulogic;
+ signal ex2_mtfsf   :std_ulogic;
+ signal ex2_mtfsfi   :std_ulogic;
+
+ signal ex3_fpscr_bit_data  :std_ulogic_vector(0 to 3);
+ signal ex3_fpscr_bit_mask  :std_ulogic_vector(0 to 3);
+ signal ex3_fpscr_nib_mask  :std_ulogic_vector(0 to 8);
+ signal ex3_mtfsbx   :std_ulogic;
+ signal ex3_mcrfs   :std_ulogic;
+ signal ex3_mtfsf   :std_ulogic;
+ signal ex3_mtfsfi   :std_ulogic;
+ signal ex1_mv_to_op  :std_ulogic;
+ signal ex2_mv_to_op  :std_ulogic;
+ signal ex3_mv_to_op  :std_ulogic;
+ signal ex1_fpscr_data  :std_ulogic_vector(0 to 7);
+ signal rf1_thread :std_ulogic_vector(0 to 3); 
+ signal rf1_rd_sel_0 ,   ex1_rd_sel_0  :std_ulogic;
+ signal rf1_rd_sel_1 ,   ex1_rd_sel_1  :std_ulogic;
+ signal rf1_rd_sel_2 ,   ex1_rd_sel_2  :std_ulogic;
+ signal rf1_rd_sel_3 ,   ex1_rd_sel_3  :std_ulogic; 
+ signal rf1_rd_sel_byp2, ex1_rd_sel_byp2 :std_ulogic;
+ signal rf1_rd_sel_byp3, ex1_rd_sel_byp3 :std_ulogic;
+ signal rf1_rd_sel_byp4, ex1_rd_sel_byp4 :std_ulogic;
+ signal rf1_rd_sel_byp5, ex1_rd_sel_byp5 :std_ulogic;
+ signal rf1_rd_sel_byp6, ex1_rd_sel_byp6 :std_ulogic;
+
+ signal rf1_rd_sel_byp2_pri  :std_ulogic;
+ signal rf1_rd_sel_byp3_pri  :std_ulogic;
+ signal rf1_rd_sel_byp4_pri  :std_ulogic;
+ signal rf1_rd_sel_byp5_pri  :std_ulogic;
+ signal rf1_rd_sel_byp6_pri  :std_ulogic;
+
+ signal ex1_fpscr_shadow_mux :std_ulogic_vector(0 to 7);
+ signal rf1_thread_match_1 :std_ulogic;
+ signal rf1_thread_match_2 :std_ulogic;
+ signal rf1_thread_match_3 :std_ulogic;
+ signal rf1_thread_match_4 :std_ulogic;
+ signal rf1_thread_match_5 :std_ulogic;
+ signal rf1_fpscr_bit_data :std_ulogic_vector(0 to 3) ;
+ signal rf1_fpscr_bit_mask :std_ulogic_vector(0 to 3) ;
+ signal rf1_fpscr_nib_mask :std_ulogic_vector(0 to 8) ;
+ signal rf1_mtfsbx         :std_ulogic         ;
+ signal rf1_mcrfs          :std_ulogic         ;
+ signal rf1_mtfsf          :std_ulogic         ;
+ signal rf1_mtfsfi         :std_ulogic         ;
+ signal ex6_cancel :std_ulogic;
+ signal ex6_fpscr_rd_dat_no_byp :std_ulogic_vector(24 to 31);
+
+
+begin 
+
+
+    
+    thold_reg_0:  tri_plat  generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,  
+         flush     => flush ,
+         din(0)    => thold_1,   
+         q(0)      => thold_0  ); 
+    
+    sg_reg_0:  tri_plat     generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,
+         flush     => flush ,
+         din(0)    => sg_1  ,     
+         q(0)      => sg_0  );   
+
+
+    lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
+        clkoff_b     => clkoff_b,
+        thold        => thold_0,  
+        sg           => sg_0,
+        act_dis      => act_dis,
+        forcee => forcee,
+        thold_b      => thold_0_b );
+
+    
+
+
+    act_lat:  tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(6)     ,
+        mpw1_b           => mpw1_b(6)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => act_so   ,                     
+        scin             => act_si   ,                   
+         din(0)             => act_spare_unused(0),
+         din(1)             => act_spare_unused(1),        
+         din(2)             => ex1_act,
+         din(3)             => ex2_act,
+         din(4)             => ex3_act,
+         din(5)             => ex4_act,
+         din(6)             => ex5_act,
+        dout(0)             => act_spare_unused(0),
+        dout(1)             => act_spare_unused(1),
+        dout(2)             => ex2_act,
+        dout(3)             => ex3_act,
+        dout(4)             => ex4_act,
+        dout(5)             => ex5_act ,
+        dout(6)             => ex6_act  );
+
+       
+        act_spare_unused(2) <= rf1_act;
+
+
+    rf1_thread(0 to 3)         <= not rf1_thread_b(0 to 3)              ;
+    rf1_fpscr_bit_data(0 to 3) <= not f_dcd_rf1_fpscr_bit_data_b(0 to 3);
+    rf1_fpscr_bit_mask(0 to 3) <= not f_dcd_rf1_fpscr_bit_mask_b(0 to 3);
+    rf1_fpscr_nib_mask(0 to 8) <= not f_dcd_rf1_fpscr_nib_mask_b(0 to 8);
+    rf1_mtfsbx                 <= not f_dcd_rf1_mtfsbx_b                ;
+    rf1_mcrfs                  <= not f_dcd_rf1_mcrfs_b                 ;
+    rf1_mtfsf                  <= not f_dcd_rf1_mtfsf_b                 ;
+    rf1_mtfsfi                 <= not f_dcd_rf1_mtfsfi_b                ;
+
+
+    ex1_ctl_lat:  tri_rlmreg_p generic map (width=> 34, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(1)     ,
+        mpw1_b           => mpw1_b(1)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk            => nclk, 
+        thold_b         => thold_0_b,
+        sg              => sg_0, 
+        act             => fpu_enable,   
+        scout            => ex1_ctl_so   ,                     
+        scin             => ex1_ctl_si   ,                   
+         din(0 to 3)        => rf1_thread(0 to 3)        ,
+         din(4 to 7)        => rf1_fpscr_bit_data(0 to 3),
+         din(8 to 11)       => rf1_fpscr_bit_mask(0 to 3),
+         din(12 to 20)      => rf1_fpscr_nib_mask(0 to 8),
+         din(21)            => rf1_mtfsbx                ,
+         din(22)            => rf1_mcrfs                 ,
+         din(23)            => rf1_mtfsf                 ,
+         din(24)            => rf1_mtfsfi                ,
+         din(25)            => rf1_rd_sel_0 ,
+         din(26)            => rf1_rd_sel_1 ,
+         din(27)            => rf1_rd_sel_2 ,
+         din(28)            => rf1_rd_sel_3 ,
+         din(29)            => rf1_rd_sel_byp2_pri ,
+         din(30)            => rf1_rd_sel_byp3_pri ,
+         din(31)            => rf1_rd_sel_byp4_pri ,
+         din(32)            => rf1_rd_sel_byp5_pri ,
+         din(33)            => rf1_rd_sel_byp6_pri ,
+        dout(0 to 3)        => ex1_thread(0 to 3)        ,
+        dout(4 to 7)        => ex1_fpscr_bit_data(0 to 3),
+        dout(8 to 11)       => ex1_fpscr_bit_mask(0 to 3),
+        dout(12 to 20)      => ex1_fpscr_nib_mask(0 to 8),
+        dout(21)            => ex1_mtfsbx                ,
+        dout(22)            => ex1_mcrfs                 ,
+        dout(23)            => ex1_mtfsf                 ,
+        dout(24)            => ex1_mtfsfi                ,
+        dout(25)            => ex1_rd_sel_0              ,
+        dout(26)            => ex1_rd_sel_1              ,
+        dout(27)            => ex1_rd_sel_2              ,
+        dout(28)            => ex1_rd_sel_3              ,
+        dout(29)            => ex1_rd_sel_byp2         ,
+        dout(30)            => ex1_rd_sel_byp3         ,
+        dout(31)            => ex1_rd_sel_byp4         ,
+        dout(32)            => ex1_rd_sel_byp5         ,
+        dout(33)            => ex1_rd_sel_byp6        );
+
+
+
+    ex2_ctl_lat:  tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)     ,
+        mpw1_b           => mpw1_b(2)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => ex2_ctl_so   ,                     
+        scin             => ex2_ctl_si   ,                   
+         din(0 to 3)        => ex1_thread(0 to 3)          ,
+         din(4 to 7)        => ex1_fpscr_bit_data(0 to 3)  ,
+         din(8 to 11)       => ex1_fpscr_bit_mask(0 to 3)  ,
+         din(12 to 20)      => ex1_fpscr_nib_mask(0 to 8)  ,
+         din(21)            => ex1_mtfsbx                  ,
+         din(22)            => ex1_mcrfs                   ,
+         din(23)            => ex1_mtfsf                   ,
+         din(24)            => ex1_mtfsfi                  ,
+        dout(0 to 3)        => ex2_thread(0 to 3)          ,
+        dout(4 to 7)        => ex2_fpscr_bit_data(0 to 3)  ,
+        dout(8 to 11)       => ex2_fpscr_bit_mask(0 to 3)  ,
+        dout(12 to 20)      => ex2_fpscr_nib_mask(0 to 8)  ,
+        dout(21)            => ex2_mtfsbx                  ,
+        dout(22)            => ex2_mcrfs                   ,
+        dout(23)            => ex2_mtfsf                   ,
+        dout(24)            => ex2_mtfsfi                 );
+
+
+
+    ex3_ctl_lat:  tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(3)     ,
+        mpw1_b           => mpw1_b(3)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk            => nclk, 
+        thold_b         => thold_0_b,
+        sg              => sg_0, 
+        act             => fpu_enable, 
+        scout            => ex3_ctl_so   ,                     
+        scin             => ex3_ctl_si   ,                   
+         din(0 to 3)        => ex2_thread(0 to 3)          ,
+         din(4 to 7)        => ex2_fpscr_bit_data(0 to 3)  ,
+         din(8 to 11)       => ex2_fpscr_bit_mask(0 to 3)  ,
+         din(12 to 20)      => ex2_fpscr_nib_mask(0 to 8)  ,
+         din(21)            => ex2_mtfsbx                  ,
+         din(22)            => ex2_mcrfs                   ,
+         din(23)            => ex2_mtfsf                   ,
+         din(24)            => ex2_mtfsfi                  ,
+        dout(0 to 3)        => ex3_thread(0 to 3)          ,
+        dout(4 to 7)        => ex3_fpscr_bit_data(0 to 3)  ,
+        dout(8 to 11)       => ex3_fpscr_bit_mask(0 to 3)  ,
+        dout(12 to 20)      => ex3_fpscr_nib_mask(0 to 8)  ,
+        dout(21)            => ex3_mtfsbx                  ,
+        dout(22)            => ex3_mcrfs                   ,
+        dout(23)            => ex3_mtfsf                   ,
+        dout(24)            => ex3_mtfsfi                  );
+
+   f_cr2_ex3_thread_b(0 to 3)         <= not ex3_thread(0 to 3)        ;
+   f_cr2_ex3_fpscr_bit_data_b(0 to 3) <= not ex3_fpscr_bit_data(0 to 3);
+   f_cr2_ex3_fpscr_bit_mask_b(0 to 3) <= not ex3_fpscr_bit_mask(0 to 3);
+   f_cr2_ex3_fpscr_nib_mask_b(0 to 8) <= not ex3_fpscr_nib_mask(0 to 8);
+   f_cr2_ex3_mtfsbx_b                 <= not ex3_mtfsbx                ;
+   f_cr2_ex3_mcrfs_b                  <= not ex3_mcrfs                 ;
+   f_cr2_ex3_mtfsf_b                  <= not ex3_mtfsf                 ;
+   f_cr2_ex3_mtfsfi_b                 <= not ex3_mtfsfi                ;
+
+
+
+    ex4_ctl_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(4)     ,
+        mpw1_b           => mpw1_b(4)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => ex4_ctl_so   ,                     
+        scin             => ex4_ctl_si   ,                   
+         din(0 to 3)        => ex3_thread(0 to 3)     ,
+         din(4)             => ex3_mv_to_op           ,
+        dout(0 to 3)        => ex4_thread(0 to 3)   ,
+        dout(4)             => ex4_mv_to_op        );
+
+
+    ex5_ctl_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map (  
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(5)     ,
+        mpw1_b           => mpw1_b(5)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => ex5_ctl_so   ,                     
+        scin             => ex5_ctl_si   ,                   
+         din(0 to 3)        => ex4_thread(0 to 3)   ,
+         din(4)             => ex4_mv_to_op,
+        dout(0 to 3)        => ex5_thread(0 to 3) ,
+        dout(4)             => ex5_mv_to_op );
+
+    ex6_ctl_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(6)     ,
+        mpw1_b           => mpw1_b(6)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => ex6_ctl_so   ,                     
+        scin             => ex6_ctl_si   ,                   
+         din(0 to 3)     => ex5_thread(0 to 3)   ,
+         din(4)          => ex5_mv_to_op , 
+        dout(0 to 3)     => ex6_thread(0 to 3) ,
+        dout(4)          => ex6_mv_to_op ); 
+
+ex6_cancel <= f_dcd_ex6_cancel;
+
+
+f_cr2_ex5_fpscr_rd_dat(24 to 31) <= 
+   ( (24 to 31 => ex5_thread(0)) and shadow0(0 to 7) ) or 
+   ( (24 to 31 => ex5_thread(1)) and shadow1(0 to 7) ) or 
+   ( (24 to 31 => ex5_thread(2)) and shadow2(0 to 7) ) or 
+   ( (24 to 31 => ex5_thread(3)) and shadow3(0 to 7) ) ;
+
+
+ex6_fpscr_rd_dat_no_byp(24 to 31) <=                       
+   ( (24 to 31 => ex6_thread(0)) and shadow0(0 to 7) ) or  
+   ( (24 to 31 => ex6_thread(1)) and shadow1(0 to 7) ) or  
+   ( (24 to 31 => ex6_thread(2)) and shadow2(0 to 7) ) or  
+   ( (24 to 31 => ex6_thread(3)) and shadow3(0 to 7) ) ;   
+
+f_cr2_ex6_fpscr_rd_dat(24 to 31)   <=                                            
+   ( (24 to 31 =>     ex6_mv_to_op) and shadow_byp6(0 to 7)                ) or  
+   ( (24 to 31 => not ex6_mv_to_op) and ex6_fpscr_rd_dat_no_byp(24 to 31)  ) ;   
+   
+
+
+
+  ex1_bit_sel(0 to 3) <= ex1_fpscr_bit_mask(0 to 3) and (0 to 3 => ex1_mv_to_op and ex1_fpscr_nib_mask(6) );
+  ex1_bit_sel(4 to 7) <= ex1_fpscr_bit_mask(0 to 3) and (0 to 3 => ex1_mv_to_op and ex1_fpscr_nib_mask(7) );
+
+  ex1_fpscr_data(0 to 3) <=
+         ( f_fmt_ex1_bop_byt(45 to 48)  and     (0 to 3=> ex1_mtfsf) ) or 
+         ( ex1_fpscr_bit_data(0 to 3)   and not (0 to 3=> ex1_mtfsf) ) ;
+  ex1_fpscr_data(4 to 7) <=
+         ( f_fmt_ex1_bop_byt(49 to 52)  and     (0 to 3=> ex1_mtfsf) ) or 
+         ( ex1_fpscr_bit_data(0 to 3)   and not (0 to 3=> ex1_mtfsf) ) ;
+
+  shadow_byp2_din(0 to 7) <=  
+       (ex1_fpscr_shadow_mux(0 to 7) and not ex1_bit_sel(0 to 7) ) or
+       (ex1_fpscr_data(0 to 7)       and     ex1_bit_sel(0 to 7) ) ;
+
+
+  
+  ex1_mv_to_op <= ex1_mtfsbx or ex1_mtfsf or ex1_mtfsfi ;
+  ex2_mv_to_op <= ex2_mtfsbx or ex2_mtfsf or ex2_mtfsfi ;
+  ex3_mv_to_op <= ex3_mtfsbx or ex3_mtfsf or ex3_mtfsfi ;
+  
+
+  rf1_thread_match_1 <=
+      ( rf1_thread(0) and ex1_thread(0) ) or 
+      ( rf1_thread(1) and ex1_thread(1) ) or 
+      ( rf1_thread(2) and ex1_thread(2) ) or 
+      ( rf1_thread(3) and ex1_thread(3) ) ;
+
+  rf1_thread_match_2 <=
+      ( rf1_thread(0) and ex2_thread(0) ) or 
+      ( rf1_thread(1) and ex2_thread(1) ) or 
+      ( rf1_thread(2) and ex2_thread(2) ) or 
+      ( rf1_thread(3) and ex2_thread(3) ) ;
+
+  rf1_thread_match_3 <=
+      ( rf1_thread(0) and ex3_thread(0) ) or 
+      ( rf1_thread(1) and ex3_thread(1) ) or 
+      ( rf1_thread(2) and ex3_thread(2) ) or 
+      ( rf1_thread(3) and ex3_thread(3) ) ;
+
+  rf1_thread_match_4 <=
+      ( rf1_thread(0) and ex4_thread(0) ) or 
+      ( rf1_thread(1) and ex4_thread(1) ) or 
+      ( rf1_thread(2) and ex4_thread(2) ) or 
+      ( rf1_thread(3) and ex4_thread(3) ) ;
+
+  rf1_thread_match_5 <=                       
+      ( rf1_thread(0) and ex5_thread(0) ) or  
+      ( rf1_thread(1) and ex5_thread(1) ) or  
+      ( rf1_thread(2) and ex5_thread(2) ) or  
+      ( rf1_thread(3) and ex5_thread(3) ) ;   
+
+  rf1_rd_sel_byp2 <= rf1_thread_match_1 and ex1_mv_to_op ;
+  rf1_rd_sel_byp3 <= rf1_thread_match_2 and ex2_mv_to_op ;
+  rf1_rd_sel_byp4 <= rf1_thread_match_3 and ex3_mv_to_op ;
+  rf1_rd_sel_byp5 <= rf1_thread_match_4 and ex4_mv_to_op ;
+  rf1_rd_sel_byp6 <= rf1_thread_match_5 and ex5_mv_to_op ;
+
+  rf1_rd_sel_0 <= rf1_thread(0) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5  and not rf1_rd_sel_byp6 ;
+  rf1_rd_sel_1 <= rf1_thread(1) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5  and not rf1_rd_sel_byp6 ;
+  rf1_rd_sel_2 <= rf1_thread(2) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5  and not rf1_rd_sel_byp6 ;
+  rf1_rd_sel_3 <= rf1_thread(3) and not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5  and not rf1_rd_sel_byp6 ;
+
+
+  rf1_rd_sel_byp2_pri <=     rf1_rd_sel_byp2;
+  rf1_rd_sel_byp3_pri <= not rf1_rd_sel_byp2 and     rf1_rd_sel_byp3;
+  rf1_rd_sel_byp4_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and     rf1_rd_sel_byp4;
+  rf1_rd_sel_byp5_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and     rf1_rd_sel_byp5;
+  rf1_rd_sel_byp6_pri <= not rf1_rd_sel_byp2 and not rf1_rd_sel_byp3 and not rf1_rd_sel_byp4 and not rf1_rd_sel_byp5 and rf1_rd_sel_byp6 ;
+
+
+
+  ex1_fpscr_shadow_mux(0 to 7) <=
+        ( (0 to 7 => ex1_rd_sel_0)    and  shadow0    (0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_1)    and  shadow1    (0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_2)    and  shadow2    (0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_3)    and  shadow3    (0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_byp2) and  shadow_byp2(0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_byp3) and  shadow_byp3(0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_byp4) and  shadow_byp4(0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_byp5) and  shadow_byp5(0 to 7) ) or 
+        ( (0 to 7 => ex1_rd_sel_byp6) and  shadow_byp6(0 to 7) ) ;  
+
+   f_cr2_ex1_fpscr_shadow(0 to 7) <= ex1_fpscr_shadow_mux(0 to 7);
+
+           
+
+    shadow_byp2_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)     ,
+        mpw1_b           => mpw1_b(2)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk            => nclk, 
+        thold_b         => thold_0_b,
+        sg              => sg_0, 
+        act             => ex1_act, 
+        scout            => shadow_byp2_so  ,                      
+        scin             => shadow_byp2_si  ,                    
+        din              => shadow_byp2_din(0 to 7),
+        dout             => shadow_byp2    (0 to 7) );
+
+    shadow_byp3_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(3)     ,
+        mpw1_b           => mpw1_b(3)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk            => nclk, 
+        thold_b         => thold_0_b,
+        sg              => sg_0, 
+        act             => ex2_act, 
+        scout            => shadow_byp3_so  ,                  
+        scin             => shadow_byp3_si  ,                    
+        din              => shadow_byp2(0 to 7),
+        dout             => shadow_byp3(0 to 7) );
+
+    shadow_byp4_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(4)     ,
+        mpw1_b           => mpw1_b(4)          ,
+        mpw2_b           => mpw2_b(0)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex3_act, 
+        scout            => shadow_byp4_so  ,                      
+        scin             => shadow_byp4_si  ,                    
+        din              => shadow_byp3(0 to 7),
+        dout             => shadow_byp4(0 to 7) );
+
+    shadow_byp5_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(5)     ,
+        mpw1_b           => mpw1_b(5)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex4_act, 
+        scout            => shadow_byp5_so  ,                      
+        scin             => shadow_byp5_si  ,                    
+        din              => shadow_byp4(0 to 7),
+        dout             => shadow_byp5(0 to 7) );
+
+    shadow_byp6_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map (  
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(6)     ,
+        mpw1_b           => mpw1_b(6)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex5_act,  
+        scout            => shadow_byp6_so  ,                      
+        scin             => shadow_byp6_si  ,                    
+        din              => shadow_byp5(0 to 7), 
+        dout             => shadow_byp6(0 to 7) );
+
+        ex6_th0_act <= ex6_act and ex6_thread(0) and not ex6_cancel and ex6_mv_to_op ; 
+        ex6_th1_act <= ex6_act and ex6_thread(1) and not ex6_cancel and ex6_mv_to_op ; 
+        ex6_th2_act <= ex6_act and ex6_thread(2) and not ex6_cancel and ex6_mv_to_op ; 
+        ex6_th3_act <= ex6_act and ex6_thread(3) and not ex6_cancel and ex6_mv_to_op ; 
+
+
+
+    shadow0_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(7)     ,
+        mpw1_b           => mpw1_b(7)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex6_th0_act,  
+        scout            => shadow0_so  ,                      
+        scin             => shadow0_si  ,                    
+        din              => shadow_byp6(0 to 7), 
+        dout             => shadow0(0 to 7) );
+       
+    shadow1_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(7)     ,
+        mpw1_b           => mpw1_b(7)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex6_th1_act,  
+        scout            => shadow1_so  ,                      
+        scin             => shadow1_si  ,                    
+        din              => shadow_byp6(0 to 7), 
+        dout             => shadow1(0 to 7) );
+       
+    shadow2_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(7)     ,
+        mpw1_b           => mpw1_b(7)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex6_th2_act,  
+        scout            => shadow2_so  ,                      
+        scin             => shadow2_si  ,                    
+        din              => shadow_byp6(0 to 7), 
+        dout             => shadow2(0 to 7) );
+       
+    shadow3_lat:  tri_rlmreg_p generic map (width=> 8, expand_type => expand_type) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(7)     ,
+        mpw1_b           => mpw1_b(7)          ,
+        mpw2_b           => mpw2_b(1)          ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex6_th3_act,  
+        scout            => shadow3_so  ,                      
+        scin             => shadow3_si  ,                    
+        din              => shadow_byp6(0 to 7), 
+        dout             => shadow3(0 to 7) );
+
+
+       
+
+
+    ex1_ctl_si      (0 to 33) <= ex1_ctl_so      (1 to 33) & f_cr2_si ;
+    ex2_ctl_si      (0 to 24) <= ex2_ctl_so      (1 to 24) & ex1_ctl_so  (0);
+    ex3_ctl_si      (0 to 24) <= ex3_ctl_so      (1 to 24) & ex2_ctl_so  (0);
+    ex4_ctl_si      (0 to 4)  <= ex4_ctl_so      (1 to 4)  & ex3_ctl_so  (0);
+    ex5_ctl_si      (0 to 4)  <= ex5_ctl_so      (1 to 4)  & ex4_ctl_so  (0); 
+    ex6_ctl_si      (0 to 4)  <= ex6_ctl_so      (1 to 4)  & ex5_ctl_so  (0); 
+    shadow0_si      (0 to 7)  <= shadow0_so      (1 to 7)  & ex6_ctl_so  (0); 
+    shadow1_si      (0 to 7)  <= shadow1_so      (1 to 7)  & shadow0_so  (0);
+    shadow2_si      (0 to 7)  <= shadow2_so      (1 to 7)  & shadow1_so  (0);
+    shadow3_si      (0 to 7)  <= shadow3_so      (1 to 7)  & shadow2_so  (0);
+    shadow_byp2_si  (0 to 7)  <= shadow_byp2_so  (1 to 7)  & shadow3_so  (0);
+    shadow_byp3_si  (0 to 7)  <= shadow_byp3_so  (1 to 7)  & shadow_byp2_so  (0);
+    shadow_byp4_si  (0 to 7)  <= shadow_byp4_so  (1 to 7)  & shadow_byp3_so  (0);
+    shadow_byp5_si  (0 to 7)  <= shadow_byp5_so  (1 to 7)  & shadow_byp4_so  (0);
+    shadow_byp6_si  (0 to 7)  <= shadow_byp6_so  (1 to 7)  & shadow_byp5_so  (0); 
+    act_si          (0 to 6)  <= act_so          (1 to 6)  & shadow_byp6_so  (0);  
+    f_cr2_so                  <=  act_so  (0) ;
+ 
+
+
+end; 
+ 
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_csa22_h2.vhdl

@@ -0,0 +1,63 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm; 
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+
+ENTITY fuq_csa22_h2 IS
+  PORT(
+   a       : IN  std_ulogic;
+   b       : IN  std_ulogic;
+   car     : OUT std_ulogic;
+   sum     : OUT std_ulogic
+  );
+END                               fuq_csa22_h2;
+
+ARCHITECTURE fuq_csa22_h2 OF fuq_csa22_h2 IS
+
+    signal car_b, sum_b : std_ulogic;
+
+
+
+BEGIN
+
+  u_22nandc: car_b <= not( a and b );
+  u_22nands: sum_b <= not( car_b and (a or b) ); 
+  u_22invc:  car   <= not car_b;
+  u_22invs:  sum   <= not sum_b ;
+
+END;
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eie.vhdl

@@ -0,0 +1,599 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+   
+
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+
+
+ 
+entity fuq_eie is 
+generic(  expand_type               : integer := 2  ); 
+port( 
+
+       vdd                                       :inout power_logic;
+       gnd                                       :inout power_logic;
+       clkoff_b                                  :in   std_ulogic; 
+       act_dis                                   :in   std_ulogic; 
+       flush                                     :in   std_ulogic; 
+       delay_lclkr                               :in   std_ulogic_vector(2 to 3); 
+       mpw1_b                                    :in   std_ulogic_vector(2 to 3); 
+       mpw2_b                                    :in   std_ulogic_vector(0 to 0); 
+       sg_1                                      :in   std_ulogic;
+       thold_1                                   :in   std_ulogic;
+       fpu_enable                                :in   std_ulogic; 
+       nclk                                      :in   clk_logic;
+
+       f_eie_si                                  :in   std_ulogic                    ;
+       f_eie_so                                  :out  std_ulogic                    ;
+       ex1_act                                   :in   std_ulogic                    ;
+
+       f_byp_eie_ex1_a_expo                      :in   std_ulogic_vector(1 to 13)    ;
+       f_byp_eie_ex1_c_expo                      :in   std_ulogic_vector(1 to 13)    ;
+       f_byp_eie_ex1_b_expo                      :in   std_ulogic_vector(1 to 13)    ;
+
+       f_pic_ex1_from_integer                    :in   std_ulogic                    ;
+       f_pic_ex1_fsel                            :in   std_ulogic                    ;
+       f_pic_ex2_frsp_ue1                        :in   std_ulogic                    ;
+
+       f_alg_ex2_sel_byp                         :in   std_ulogic                    ;
+       f_fmt_ex2_fsel_bsel                       :in   std_ulogic                    ;
+       f_pic_ex2_force_sel_bexp                  :in   std_ulogic                    ;
+       f_pic_ex2_sp_b                            :in   std_ulogic                    ;
+       f_pic_ex2_math_bzer_b                     :in   std_ulogic                    ;
+
+       f_eie_ex2_tbl_expo                        :out  std_ulogic_vector(1 to 13)    ;
+
+       f_eie_ex2_lt_bias                         :out  std_ulogic                    ; 
+       f_eie_ex2_eq_bias_m1                      :out  std_ulogic                    ; 
+       f_eie_ex2_wd_ov                           :out  std_ulogic                    ; 
+       f_eie_ex2_dw_ov                           :out  std_ulogic                    ; 
+       f_eie_ex2_wd_ov_if                        :out  std_ulogic                    ; 
+       f_eie_ex2_dw_ov_if                        :out  std_ulogic                    ; 
+       f_eie_ex2_lzo_expo                        :out  std_ulogic_vector(1 to 13)    ; 
+       f_eie_ex2_b_expo                          :out  std_ulogic_vector(1 to 13)    ; 
+       f_eie_ex2_use_bexp                        :out  std_ulogic;
+       f_eie_ex3_iexp                            :out  std_ulogic_vector(1 to 13)      
+
+); 
+ 
+ 
+
+end fuq_eie; 
+ 
+ 
+architecture fuq_eie of fuq_eie is  
+ 
+    constant tiup  :std_ulogic := '1';
+    constant tidn  :std_ulogic := '0';
+ 
+    signal sg_0                                  :std_ulogic                   ;
+    signal thold_0_b , thold_0, forcee              :std_ulogic                   ;
+
+    signal ex2_act                                 :std_ulogic                   ;
+    signal act_spare_unused                        :std_ulogic_vector(0 to 3)    ;
+    signal act_so                                  :std_ulogic_vector(0 to 4)    ;
+    signal act_si                                  :std_ulogic_vector(0 to 4)    ;
+    signal ex2_bop_so                              :std_ulogic_vector(0 to 12)   ;
+    signal ex2_bop_si                              :std_ulogic_vector(0 to 12)   ;
+    signal ex2_pop_so                              :std_ulogic_vector(0 to 12)   ;
+    signal ex2_pop_si                              :std_ulogic_vector(0 to 12)   ;
+    signal ex2_ctl_so                              :std_ulogic_vector(0 to 6)    ;
+    signal ex2_ctl_si                              :std_ulogic_vector(0 to 6)    ;
+    signal ex3_iexp_so                             :std_ulogic_vector(0 to 13)   ;
+    signal ex3_iexp_si                             :std_ulogic_vector(0 to 13)   ;
+    signal ex1_a_expo                              :std_ulogic_vector(1 to 13) ;
+    signal ex1_c_expo                              :std_ulogic_vector(1 to 13) ;
+    signal ex1_b_expo                              :std_ulogic_vector(1 to 13) ;
+    signal ex1_ep56_sum                            :std_ulogic_vector(1 to 13) ;
+    signal ex1_ep56_car                            :std_ulogic_vector(1 to 12) ;
+    signal ex1_ep56_p                              :std_ulogic_vector(1 to 13) ;
+    signal ex1_ep56_g                              :std_ulogic_vector(2 to 12) ;
+    signal ex1_ep56_t                              :std_ulogic_vector(2 to 11) ;
+    signal ex1_ep56_s                              :std_ulogic_vector(1 to 13) ;
+    signal ex1_ep56_c                              :std_ulogic_vector(2 to 12) ;
+    signal ex1_p_expo_adj                          :std_ulogic_vector(1 to 13) ;
+    signal ex1_from_k                              :std_ulogic_vector(1 to 13) ;
+    signal ex1_b_expo_adj                          :std_ulogic_vector(1 to 13) ;
+    signal ex2_p_expo                              :std_ulogic_vector(1 to 13) ;
+    signal ex2_b_expo                              :std_ulogic_vector(1 to 13) ;
+    signal ex2_iexp                                :std_ulogic_vector(1 to 13) ;
+    signal ex2_b_expo_adj                          :std_ulogic_vector(1 to 13) ;
+    signal ex2_p_expo_adj                          :std_ulogic_vector(1 to 13) ;
+    signal ex3_iexp                                :std_ulogic_vector(1 to 13) ;
+    signal ex1_wd_ge_bot                           :std_ulogic    ;
+    signal ex1_dw_ge_bot                           :std_ulogic    ;
+    signal ex1_ge_2048                             :std_ulogic    ;
+    signal ex1_ge_1024                             :std_ulogic    ;
+    signal ex1_dw_ge_mid                           :std_ulogic    ;
+    signal ex1_wd_ge_mid                           :std_ulogic    ;
+    signal ex1_dw_ge                               :std_ulogic    ;
+    signal ex1_wd_ge                               :std_ulogic    ;
+    signal ex1_dw_eq_top                           :std_ulogic    ;
+    signal ex1_wd_eq_bot                           :std_ulogic    ;
+    signal ex1_wd_eq                               :std_ulogic    ;
+    signal ex1_dw_eq                               :std_ulogic    ;
+    signal ex2_iexp_b_sel                          :std_ulogic    ;
+    signal ex2_dw_ge                               :std_ulogic    ;
+    signal ex2_wd_ge                               :std_ulogic    ;
+    signal ex2_wd_eq                               :std_ulogic    ;
+    signal ex2_dw_eq                               :std_ulogic    ;
+    signal ex2_fsel                                :std_ulogic    ;
+    signal ex3_sp_b                                :std_ulogic    ;
+
+
+   signal ex2_b_expo_fixed :std_ulogic_vector(1 to 13); 
+   signal ex1_ge_bias, ex1_lt_bias, ex1_eq_bias_m1 :std_ulogic;
+   signal ex2_lt_bias, ex2_eq_bias_m1 :std_ulogic;
+  signal  ex1_ep56_g2 :std_ulogic_vector( 2 to 12);
+  signal  ex1_ep56_t2 :std_ulogic_vector( 2 to 10);
+  signal  ex1_ep56_g4 :std_ulogic_vector( 2 to 12);
+  signal  ex1_ep56_t4 :std_ulogic_vector( 2 to 8);
+  signal  ex1_ep56_g8 :std_ulogic_vector( 2 to 12);
+  signal  ex1_ep56_t8 :std_ulogic_vector( 2 to 4);
+
+
+
+begin 
+ 
+
+    
+    thold_reg_0:  tri_plat  generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,  
+         flush     => flush ,
+         din(0)    => thold_1,   
+         q(0)      => thold_0  ); 
+    
+    sg_reg_0:  tri_plat     generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,
+         flush     => flush ,
+         din(0)    => sg_1  ,     
+         q(0)      => sg_0  );   
+
+
+    lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
+        clkoff_b     => clkoff_b,
+        thold        => thold_0,  
+        sg           => sg_0,
+        act_dis      => act_dis,
+        forcee => forcee,
+        thold_b      => thold_0_b );
+
+
+
+ 
+
+
+    act_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)  ,
+        mpw1_b           => mpw1_b(2)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => act_so   ,                     
+        scin             => act_si   ,                   
+         din(0)             => act_spare_unused(0),
+         din(1)             => act_spare_unused(1),
+         din(2)             => ex1_act,
+         din(3)             => act_spare_unused(2),
+         din(4)             => act_spare_unused(3),
+        dout(0)             => act_spare_unused(0),
+        dout(1)             => act_spare_unused(1),
+        dout(2)             => ex2_act,
+        dout(3)             => act_spare_unused(2),
+        dout(4)             => act_spare_unused(3) );
+
+
+
+    ex1_a_expo(1 to 13) <= f_byp_eie_ex1_a_expo(1 to 13);
+    ex1_c_expo(1 to 13) <= f_byp_eie_ex1_c_expo(1 to 13);
+    ex1_b_expo(1 to 13) <= f_byp_eie_ex1_b_expo(1 to 13);
+
+
+
+    
+    ex1_ep56_sum( 1) <= not( ex1_a_expo( 1) xor ex1_c_expo( 1) ); 
+    ex1_ep56_sum( 2) <= not( ex1_a_expo( 2) xor ex1_c_expo( 2) ); 
+    ex1_ep56_sum( 3) <= not( ex1_a_expo( 3) xor ex1_c_expo( 3) ); 
+    ex1_ep56_sum( 4) <=    ( ex1_a_expo( 4) xor ex1_c_expo( 4) ); 
+    ex1_ep56_sum( 5) <=    ( ex1_a_expo( 5) xor ex1_c_expo( 5) ); 
+    ex1_ep56_sum( 6) <=    ( ex1_a_expo( 6) xor ex1_c_expo( 6) ); 
+    ex1_ep56_sum( 7) <=    ( ex1_a_expo( 7) xor ex1_c_expo( 7) ); 
+    ex1_ep56_sum( 8) <= not( ex1_a_expo( 8) xor ex1_c_expo( 8) ); 
+    ex1_ep56_sum( 9) <= not( ex1_a_expo( 9) xor ex1_c_expo( 9) ); 
+    ex1_ep56_sum(10) <= not( ex1_a_expo(10) xor ex1_c_expo(10) ); 
+    ex1_ep56_sum(11) <=    ( ex1_a_expo(11) xor ex1_c_expo(11) ); 
+    ex1_ep56_sum(12) <=    ( ex1_a_expo(12) xor ex1_c_expo(12) ); 
+    ex1_ep56_sum(13) <= not( ex1_a_expo(13) xor ex1_c_expo(13) ); 
+  
+    ex1_ep56_car( 1) <=    ( ex1_a_expo( 2) or  ex1_c_expo( 2) ); 
+    ex1_ep56_car( 2) <=    ( ex1_a_expo( 3) or  ex1_c_expo( 3) ); 
+    ex1_ep56_car( 3) <=    ( ex1_a_expo( 4) and ex1_c_expo( 4) ); 
+    ex1_ep56_car( 4) <=    ( ex1_a_expo( 5) and ex1_c_expo( 5) ); 
+    ex1_ep56_car( 5) <=    ( ex1_a_expo( 6) and ex1_c_expo( 6) ); 
+    ex1_ep56_car( 6) <=    ( ex1_a_expo( 7) and ex1_c_expo( 7) ); 
+    ex1_ep56_car( 7) <=    ( ex1_a_expo( 8) or  ex1_c_expo( 8) ); 
+    ex1_ep56_car( 8) <=    ( ex1_a_expo( 9) or  ex1_c_expo( 9) ); 
+    ex1_ep56_car( 9) <=    ( ex1_a_expo(10) or  ex1_c_expo(10) ); 
+    ex1_ep56_car(10) <=    ( ex1_a_expo(11) and ex1_c_expo(11) ); 
+    ex1_ep56_car(11) <=    ( ex1_a_expo(12) and ex1_c_expo(12) ); 
+    ex1_ep56_car(12) <=    ( ex1_a_expo(13) or  ex1_c_expo(13) ); 
+    
+    ex1_ep56_p(1 to 12) <= ex1_ep56_sum(1 to 12) xor ex1_ep56_car(1 to 12);
+    ex1_ep56_p(13)      <= ex1_ep56_sum(13);  
+    ex1_ep56_g(2 to 12) <= ex1_ep56_sum(2 to 12) and ex1_ep56_car(2 to 12);
+    ex1_ep56_t(2 to 11) <= ex1_ep56_sum(2 to 11) or  ex1_ep56_car(2 to 11);
+    
+    ex1_ep56_s(1 to 11) <= ex1_ep56_p(1 to 11) xor ex1_ep56_c(2 to 12);    
+    ex1_ep56_s(12) <= ex1_ep56_p(12);
+    ex1_ep56_s(13) <= ex1_ep56_p(13);
+
+
+    ex1_ep56_g2(12) <= ex1_ep56_g(12) ;
+    ex1_ep56_g2(11) <= ex1_ep56_g(11) or (ex1_ep56_t(11) and ex1_ep56_g(12)) ;
+    ex1_ep56_g2(10) <= ex1_ep56_g(10) or (ex1_ep56_t(10) and ex1_ep56_g(11)) ;
+    ex1_ep56_g2( 9) <= ex1_ep56_g( 9) or (ex1_ep56_t( 9) and ex1_ep56_g(10)) ;
+    ex1_ep56_g2( 8) <= ex1_ep56_g( 8) or (ex1_ep56_t( 8) and ex1_ep56_g( 9)) ;
+    ex1_ep56_g2( 7) <= ex1_ep56_g( 7) or (ex1_ep56_t( 7) and ex1_ep56_g( 8)) ;
+    ex1_ep56_g2( 6) <= ex1_ep56_g( 6) or (ex1_ep56_t( 6) and ex1_ep56_g( 7)) ;
+    ex1_ep56_g2( 5) <= ex1_ep56_g( 5) or (ex1_ep56_t( 5) and ex1_ep56_g( 6)) ;
+    ex1_ep56_g2( 4) <= ex1_ep56_g( 4) or (ex1_ep56_t( 4) and ex1_ep56_g( 5)) ;
+    ex1_ep56_g2( 3) <= ex1_ep56_g( 3) or (ex1_ep56_t( 3) and ex1_ep56_g( 4)) ;
+    ex1_ep56_g2( 2) <= ex1_ep56_g( 2) or (ex1_ep56_t( 2) and ex1_ep56_g( 3)) ;
+
+    ex1_ep56_t2(10) <=                   (ex1_ep56_t(10) and ex1_ep56_t(11)) ;
+    ex1_ep56_t2( 9) <=                   (ex1_ep56_t( 9) and ex1_ep56_t(10)) ;
+    ex1_ep56_t2( 8) <=                   (ex1_ep56_t( 8) and ex1_ep56_t( 9)) ;
+    ex1_ep56_t2( 7) <=                   (ex1_ep56_t( 7) and ex1_ep56_t( 8)) ;
+    ex1_ep56_t2( 6) <=                   (ex1_ep56_t( 6) and ex1_ep56_t( 7)) ;
+    ex1_ep56_t2( 5) <=                   (ex1_ep56_t( 5) and ex1_ep56_t( 6)) ;
+    ex1_ep56_t2( 4) <=                   (ex1_ep56_t( 4) and ex1_ep56_t( 5)) ;
+    ex1_ep56_t2( 3) <=                   (ex1_ep56_t( 3) and ex1_ep56_t( 4)) ;
+    ex1_ep56_t2( 2) <=                   (ex1_ep56_t( 2) and ex1_ep56_t( 3)) ;
+
+    ex1_ep56_g4(12) <= ex1_ep56_g2(12) ;
+    ex1_ep56_g4(11) <= ex1_ep56_g2(11) ;
+    ex1_ep56_g4(10) <= ex1_ep56_g2(10) or (ex1_ep56_t2(10) and ex1_ep56_g2(12)) ;
+    ex1_ep56_g4( 9) <= ex1_ep56_g2( 9) or (ex1_ep56_t2( 9) and ex1_ep56_g2(11)) ;
+    ex1_ep56_g4( 8) <= ex1_ep56_g2( 8) or (ex1_ep56_t2( 8) and ex1_ep56_g2(10)) ;
+    ex1_ep56_g4( 7) <= ex1_ep56_g2( 7) or (ex1_ep56_t2( 7) and ex1_ep56_g2( 9)) ;
+    ex1_ep56_g4( 6) <= ex1_ep56_g2( 6) or (ex1_ep56_t2( 6) and ex1_ep56_g2( 8)) ;
+    ex1_ep56_g4( 5) <= ex1_ep56_g2( 5) or (ex1_ep56_t2( 5) and ex1_ep56_g2( 7)) ;
+    ex1_ep56_g4( 4) <= ex1_ep56_g2( 4) or (ex1_ep56_t2( 4) and ex1_ep56_g2( 6)) ;
+    ex1_ep56_g4( 3) <= ex1_ep56_g2( 3) or (ex1_ep56_t2( 3) and ex1_ep56_g2( 5)) ;
+    ex1_ep56_g4( 2) <= ex1_ep56_g2( 2) or (ex1_ep56_t2( 2) and ex1_ep56_g2( 4)) ;
+
+    ex1_ep56_t4( 8) <=                    (ex1_ep56_t2( 8) and ex1_ep56_t2(10)) ;
+    ex1_ep56_t4( 7) <=                    (ex1_ep56_t2( 7) and ex1_ep56_t2( 9)) ;
+    ex1_ep56_t4( 6) <=                    (ex1_ep56_t2( 6) and ex1_ep56_t2( 8)) ;
+    ex1_ep56_t4( 5) <=                    (ex1_ep56_t2( 5) and ex1_ep56_t2( 7)) ;
+    ex1_ep56_t4( 4) <=                    (ex1_ep56_t2( 4) and ex1_ep56_t2( 6)) ;
+    ex1_ep56_t4( 3) <=                    (ex1_ep56_t2( 3) and ex1_ep56_t2( 5)) ;
+    ex1_ep56_t4( 2) <=                    (ex1_ep56_t2( 2) and ex1_ep56_t2( 4)) ;
+
+    ex1_ep56_g8(12) <= ex1_ep56_g4(12) ;
+    ex1_ep56_g8(11) <= ex1_ep56_g4(11) ;
+    ex1_ep56_g8(10) <= ex1_ep56_g4(10) ;
+    ex1_ep56_g8( 9) <= ex1_ep56_g4( 9) ;
+    ex1_ep56_g8( 8) <= ex1_ep56_g4( 8) or (ex1_ep56_t4( 8) and ex1_ep56_g4(12)) ;
+    ex1_ep56_g8( 7) <= ex1_ep56_g4( 7) or (ex1_ep56_t4( 7) and ex1_ep56_g4(11)) ;
+    ex1_ep56_g8( 6) <= ex1_ep56_g4( 6) or (ex1_ep56_t4( 6) and ex1_ep56_g4(10)) ;
+    ex1_ep56_g8( 5) <= ex1_ep56_g4( 5) or (ex1_ep56_t4( 5) and ex1_ep56_g4( 9)) ;
+    ex1_ep56_g8( 4) <= ex1_ep56_g4( 4) or (ex1_ep56_t4( 4) and ex1_ep56_g4( 8)) ;
+    ex1_ep56_g8( 3) <= ex1_ep56_g4( 3) or (ex1_ep56_t4( 3) and ex1_ep56_g4( 7)) ;
+    ex1_ep56_g8( 2) <= ex1_ep56_g4( 2) or (ex1_ep56_t4( 2) and ex1_ep56_g4( 6)) ;
+
+    ex1_ep56_t8( 4) <=                    (ex1_ep56_t4( 4) and ex1_ep56_t4( 8)) ;
+    ex1_ep56_t8( 3) <=                    (ex1_ep56_t4( 3) and ex1_ep56_t4( 7)) ;
+    ex1_ep56_t8( 2) <=                    (ex1_ep56_t4( 2) and ex1_ep56_t4( 6)) ;
+
+    ex1_ep56_c(12) <= ex1_ep56_g8(12) ;
+    ex1_ep56_c(11) <= ex1_ep56_g8(11) ;
+    ex1_ep56_c(10) <= ex1_ep56_g8(10) ;
+    ex1_ep56_c( 9) <= ex1_ep56_g8( 9) ;
+    ex1_ep56_c( 8) <= ex1_ep56_g8( 8) ;
+    ex1_ep56_c( 7) <= ex1_ep56_g8( 7) ;
+    ex1_ep56_c( 6) <= ex1_ep56_g8( 6) ;
+    ex1_ep56_c( 5) <= ex1_ep56_g8( 5) ;
+    ex1_ep56_c( 4) <= ex1_ep56_g8( 4) or (ex1_ep56_t8( 4) and ex1_ep56_g8(12)) ;
+    ex1_ep56_c( 3) <= ex1_ep56_g8( 3) or (ex1_ep56_t8( 3) and ex1_ep56_g8(11)) ;
+    ex1_ep56_c( 2) <= ex1_ep56_g8( 2) or (ex1_ep56_t8( 2) and ex1_ep56_g8(10)) ;
+
+
+
+
+
+   ex1_p_expo_adj(1 to 13) <=
+         ( ex1_ep56_s(1 to 13) and (1 to 13 => not f_pic_ex1_fsel) ) or 
+         ( ex1_c_expo(1 to 13) and (1 to 13 =>     f_pic_ex1_fsel) );
+
+   
+
+
+   ex1_from_k( 1) <= tidn; 
+   ex1_from_k( 2) <= tidn; 
+   ex1_from_k( 3) <= tiup; 
+   ex1_from_k( 4) <= tidn; 
+   ex1_from_k( 5) <= tidn; 
+   ex1_from_k( 6) <= tiup; 
+   ex1_from_k( 7) <= tidn; 
+   ex1_from_k( 8) <= tiup; 
+   ex1_from_k( 9) <= tidn; 
+   ex1_from_k(10) <= tidn; 
+   ex1_from_k(11) <= tidn; 
+   ex1_from_k(12) <= tidn; 
+   ex1_from_k(13) <= tiup; 
+
+   ex1_b_expo_adj(1 to 13) <=
+       ( ex1_from_k  (1 to 13) and (1 to 13=>     f_pic_ex1_from_integer ) ) or 
+       ( ex1_b_expo  (1 to 13) and (1 to 13=> not f_pic_ex1_from_integer ) ) ;
+
+
+
+
+     
+
+
+     ex1_wd_ge_bot <=      ex1_b_expo( 9) and
+                           ex1_b_expo(10) and 
+                           ex1_b_expo(11) and 
+                           ex1_b_expo(12) and 
+                           ex1_b_expo(13) ;
+
+     ex1_dw_ge_bot <=      ex1_b_expo( 8) and
+                           ex1_wd_ge_bot  ;
+                          
+     ex1_ge_2048    <= not ex1_b_expo( 1) and ex1_b_expo( 2) ;
+     ex1_ge_1024    <= not ex1_b_expo( 1) and ex1_b_expo( 3) ;
+
+     ex1_dw_ge_mid  <=     ex1_b_expo( 4) or                           
+                           ex1_b_expo( 5) or                           
+                           ex1_b_expo( 6) or                           
+                           ex1_b_expo( 7) ;
+
+     ex1_wd_ge_mid  <=     ex1_b_expo( 8) or 
+                           ex1_dw_ge_mid  ;
+                       
+     ex1_dw_ge <=  ( ex1_ge_2048                   ) or
+                   ( ex1_ge_1024 and ex1_dw_ge_mid ) or 
+                   ( ex1_ge_1024 and ex1_dw_ge_bot ) ;
+
+     ex1_wd_ge <=  ( ex1_ge_2048                   ) or
+                   ( ex1_ge_1024 and ex1_wd_ge_mid ) or 
+                   ( ex1_ge_1024 and ex1_wd_ge_bot ) ;
+
+     ex1_dw_eq_top <=  not ex1_b_expo( 1) and
+                       not ex1_b_expo( 2) and
+                           ex1_b_expo( 3) and 
+                       not ex1_b_expo( 4) and
+                       not ex1_b_expo( 5) and
+                       not ex1_b_expo( 6) and
+                       not ex1_b_expo( 7) ;
+
+     ex1_wd_eq_bot <=      ex1_b_expo( 9) and
+                           ex1_b_expo(10) and 
+                           ex1_b_expo(11) and 
+                           ex1_b_expo(12) and 
+                       not ex1_b_expo(13) ;
+
+     ex1_wd_eq     <=      ex1_dw_eq_top  and
+                       not ex1_b_expo( 8) and
+                           ex1_wd_eq_bot ;
+
+     ex1_dw_eq     <=      ex1_dw_eq_top  and
+                           ex1_b_expo( 8) and
+                           ex1_wd_eq_bot ;
+
+
+
+
+     ex1_ge_bias   <= 
+         (not ex1_b_expo(1) and ex1_b_expo(2)       ) or  
+         (not ex1_b_expo(1) and ex1_b_expo(3)       ) or 
+         (not ex1_b_expo(1) and ex1_b_expo(4)  and
+                                ex1_b_expo(5)  and
+                                ex1_b_expo(6)  and
+                                ex1_b_expo(7)  and
+                                ex1_b_expo(8)  and
+                                ex1_b_expo(9)  and
+                                ex1_b_expo(10) and
+                                ex1_b_expo(11) and
+                                ex1_b_expo(12) and
+                                ex1_b_expo(13)      );
+
+    ex1_lt_bias <= not ex1_ge_bias;
+    ex1_eq_bias_m1 <= 
+         not ex1_b_expo(1)  and 
+         not ex1_b_expo(2)  and 
+         not ex1_b_expo(3)  and 
+             ex1_b_expo(4)  and 
+             ex1_b_expo(5)  and 
+             ex1_b_expo(6)  and 
+             ex1_b_expo(7)  and 
+             ex1_b_expo(8)  and 
+             ex1_b_expo(9)  and 
+             ex1_b_expo(10) and 
+             ex1_b_expo(11) and 
+             ex1_b_expo(12) and 
+         not ex1_b_expo(13) ;   
+
+                 
+
+  ex2_bop_lat:  tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)  ,
+        mpw1_b           => mpw1_b(2)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex1_act, 
+        scout            => ex2_bop_so  ,                      
+        scin             => ex2_bop_si  ,                    
+         din(0 to 12)       => ex1_b_expo_adj  (1 to 13)   ,
+        dout(0 to 12)       => ex2_b_expo_adj  (1 to 13)  );
+ 
+  ex2_pop_lat:  tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)  ,
+        mpw1_b           => mpw1_b(2)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex1_act, 
+        scout            => ex2_pop_so  ,                      
+        scin             => ex2_pop_si  ,                    
+         din(0 to 12)       => ex1_p_expo_adj  (1 to 13)   ,
+        dout(0 to 12)       => ex2_p_expo_adj  (1 to 13)  );
+ 
+  ex2_ctl_lat:  tri_rlmreg_p generic map (width=> 7, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(2)  ,
+        mpw1_b           => mpw1_b(2)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex1_act, 
+        scout            => ex2_ctl_so  ,                      
+        scin             => ex2_ctl_si  ,                    
+         din(0)             => ex1_dw_ge ,
+         din(1)             => ex1_wd_ge ,
+         din(2)             => ex1_wd_eq ,
+         din(3)             => ex1_dw_eq ,
+         din(4)             => f_pic_ex1_fsel,
+         din(5)             => ex1_lt_bias ,
+         din(6)             => ex1_eq_bias_m1, 
+        dout(0)             => ex2_dw_ge    ,  
+        dout(1)             => ex2_wd_ge    ,  
+        dout(2)             => ex2_wd_eq    ,  
+        dout(3)             => ex2_dw_eq    ,  
+        dout(4)             => ex2_fsel     ,  
+        dout(5)             => ex2_lt_bias  ,  
+        dout(6)             => ex2_eq_bias_m1 );  
+
+        f_eie_ex2_lt_bias    <= ex2_lt_bias;
+        f_eie_ex2_eq_bias_m1 <= ex2_eq_bias_m1;
+
+       ex2_p_expo(1 to 13) <=     ex2_p_expo_adj  (1 to 13);
+       ex2_b_expo(1 to 13) <=     ex2_b_expo_adj  (1 to 13);
+
+       f_eie_ex2_wd_ov      <=     ex2_wd_ge   ;
+       f_eie_ex2_dw_ov      <=     ex2_dw_ge   ;
+       f_eie_ex2_wd_ov_if   <=     ex2_wd_eq   ;
+       f_eie_ex2_dw_ov_if   <=     ex2_dw_eq   ;
+
+       f_eie_ex2_lzo_expo(1 to 13) <=     ex2_p_expo_adj  (1 to 13) ;
+       f_eie_ex2_b_expo(1 to 13) <= ex2_b_expo(1 to 13);
+       f_eie_ex2_tbl_expo(1 to 13) <= ex2_b_expo(1 to 13);
+
+
+ ex2_b_expo_fixed(1 to 13) <= ex2_b_expo(1 to 13) ;
+
+ f_eie_ex2_use_bexp <= ex2_iexp_b_sel ;
+
+       ex2_iexp_b_sel <=
+           (f_alg_ex2_sel_byp and not ex2_fsel and f_pic_ex2_math_bzer_b )   or 
+            f_fmt_ex2_fsel_bsel      or  
+            f_pic_ex2_force_sel_bexp or  
+            f_pic_ex2_frsp_ue1 ;         
+
+       ex2_iexp(1 to 13) <=
+          ( ex2_b_expo_fixed(1 to 13) and (1 to 13 =>     ex2_iexp_b_sel) ) or 
+          ( ex2_p_expo(1 to 13)       and (1 to 13 => not ex2_iexp_b_sel) ) ;
+
+
+  ex3_iexp_lat:  tri_rlmreg_p generic map (width=> 14, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(3)  ,
+        mpw1_b           => mpw1_b(3)       ,
+        mpw2_b           => mpw2_b(0)       ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex2_act, 
+        scout            => ex3_iexp_so  ,                      
+        scin             => ex3_iexp_si  ,                    
+         din(0)             => f_pic_ex2_sp_b   ,
+         din(1 to 13)       => ex2_iexp  (1 to 13)   ,
+        dout(0)             => ex3_sp_b               ,
+        dout(1 to 13)       => ex3_iexp  (1 to 13)   );
+
+
+
+
+       f_eie_ex3_iexp(1 to 13)    <=     ex3_iexp(1 to 13)   ;
+
+
+
+
+
+    ex2_bop_si     (0 to 12)  <= ex2_bop_so     (1 to 12)  &  f_eie_si;
+    ex2_pop_si     (0 to 12)  <= ex2_pop_so     (1 to 12)  &  ex2_bop_so  (0);
+    ex2_ctl_si     (0 to 6)   <= ex2_ctl_so     (1 to 6)   &  ex2_pop_so  (0);
+    ex3_iexp_si    (0 to 13)  <= ex3_iexp_so    (1 to 13)  &  ex2_ctl_so  (0);
+    act_si         (0 to 4)   <= act_so         (1 to 4)   &  ex3_iexp_so  (0);
+    f_eie_so                  <=   act_so  (0);
+
+
+end; 
+  
+
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_eov.vhdl

@@ -0,0 +1,996 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+  
+library ieee,ibm,support,tri,work;
+   use ieee.std_logic_1164.all;
+   use ibm.std_ulogic_unsigned.all;
+   use ibm.std_ulogic_support.all; 
+   use ibm.std_ulogic_function_support.all;
+   use support.power_logic_pkg.all;
+   use tri.tri_latches_pkg.all;
+   use ibm.std_ulogic_ao_support.all; 
+   use ibm.std_ulogic_mux_support.all; 
+
+
+ 
+entity fuq_eov is 
+generic( expand_type               : integer := 2  ); 
+port( 
+ 
+
+       vdd                                       :inout power_logic;
+       gnd                                       :inout power_logic;
+       clkoff_b                                  :in   std_ulogic; 
+       act_dis                                   :in   std_ulogic; 
+       flush                                     :in   std_ulogic; 
+       delay_lclkr                               :in   std_ulogic_vector(4 to 5); 
+       mpw1_b                                    :in   std_ulogic_vector(4 to 5); 
+       mpw2_b                                    :in   std_ulogic_vector(0 to 1); 
+       sg_1                                      :in   std_ulogic;
+       thold_1                                   :in   std_ulogic;
+       fpu_enable                                :in   std_ulogic; 
+       nclk                                      :in   clk_logic;
+
+
+
+       f_eov_si                                 :in   std_ulogic                    ;
+       f_eov_so                                 :out  std_ulogic                    ;
+       ex2_act_b                                :in   std_ulogic                    ;
+
+       f_tbl_ex4_unf_expo                        :in   std_ulogic ; 
+       f_tbe_ex3_may_ov                          :in   std_ulogic;
+       f_tbe_ex3_expo                            :in   std_ulogic_vector(1 to 13)    ;
+       f_pic_ex3_sel_est                         :in   std_ulogic;
+       f_eie_ex3_iexp                            :in   std_ulogic_vector(1 to 13)    ;
+
+       f_pic_ex3_sp_b                            :in   std_ulogic                    ;
+       f_pic_ex4_oe                              :in   std_ulogic                    ;
+       f_pic_ex4_ue                              :in   std_ulogic                    ;
+       f_pic_ex4_ov_en                           :in   std_ulogic                    ;
+       f_pic_ex4_uf_en                           :in   std_ulogic                    ;
+       f_pic_ex4_spec_sel_k_e                    :in   std_ulogic                    ;
+       f_pic_ex4_spec_sel_k_f                    :in   std_ulogic                    ;
+       f_pic_ex4_sel_ov_spec                     :in   std_ulogic                    ;
+       f_pic_ex4_to_int_ov_all                   :in   std_ulogic                    ;
+
+       f_lza_ex4_sh_rgt_en_eov                   :in   std_ulogic; 
+       f_lza_ex4_lza_amt_eov                     :in   std_ulogic_vector(0 to 7)     ;
+       f_lza_ex4_no_lza_edge                     :in   std_ulogic                    ;
+       f_nrm_ex4_extra_shift                     :in   std_ulogic                    ;
+       f_eov_ex4_may_ovf                         :out  std_ulogic                    ;
+
+       f_eov_ex5_sel_k_f                         :out  std_ulogic                    ;
+       f_eov_ex5_sel_k_e                         :out  std_ulogic                    ;
+       f_eov_ex5_sel_kif_f                       :out  std_ulogic                    ;
+       f_eov_ex5_sel_kif_e                       :out  std_ulogic                    ;
+       f_eov_ex5_unf_expo                        :out  std_ulogic                    ;
+       f_eov_ex5_ovf_expo                        :out  std_ulogic                    ;
+       f_eov_ex5_ovf_if_expo                     :out  std_ulogic                    ;
+       f_eov_ex5_expo_p0                         :out  std_ulogic_vector(1 to 13)    ;
+       f_eov_ex5_expo_p1                         :out  std_ulogic_vector(1 to 13)    ;
+       f_eov_ex5_expo_p0_ue1oe1                  :out  std_ulogic_vector(3 to 7)     ;
+       f_eov_ex5_expo_p1_ue1oe1                  :out  std_ulogic_vector(3 to 7)      
+
+); 
+ 
+-- synopsys translate_off
+ 
+
+
+-- synopsys translate_on
+
+end fuq_eov; 
+ 
+ 
+architecture fuq_eov of fuq_eov is 
+ 
+    constant tiup  :std_ulogic := '1';
+    constant tidn  :std_ulogic := '0';
+ 
+    signal sg_0                                  :std_ulogic                   ;
+    signal thold_0_b, thold_0, forcee               :std_ulogic                   ;
+    signal ex3_act                                 :std_ulogic                   ;
+    signal ex2_act                                 :std_ulogic                   ;
+    signal ex4_act                                 :std_ulogic                   ;
+    signal act_spare_unused                        :std_ulogic_vector(0 to 2)    ;
+    signal act_so                                  :std_ulogic_vector(0 to 4)    ;
+    signal act_si                                  :std_ulogic_vector(0 to 4)    ;
+    signal ex4_iexp_so                             :std_ulogic_vector(0 to 15)   ;
+    signal ex4_iexp_si                             :std_ulogic_vector(0 to 15)   ;
+    signal ex5_ovctl_so                            :std_ulogic_vector(0 to 2)    ;
+    signal ex5_ovctl_si                            :std_ulogic_vector(0 to 2)    ;
+    signal ex5_misc_so                             :std_ulogic_vector(0 to 12)   ;
+    signal ex5_misc_si                             :std_ulogic_vector(0 to 12)   ;
+    signal ex5_urnd0_so                            :std_ulogic_vector(0 to 12)   ;
+    signal ex5_urnd0_si                            :std_ulogic_vector(0 to 12)   ;
+    signal ex5_urnd1_so                            :std_ulogic_vector(0 to 12)   ;
+    signal ex5_urnd1_si                            :std_ulogic_vector(0 to 12)   ;
+    signal ex4_sp                                  :std_ulogic                   ;
+    signal ex4_unf_m1_co12                         :std_ulogic                   ;
+    signal ex4_unf_p0_co12                         :std_ulogic                   ;
+    signal ex4_ovf_m1_co12                         :std_ulogic                   ;
+    signal ex4_ovf_p0_co12                         :std_ulogic                   ;
+    signal ex4_ovf_p1_co12                         :std_ulogic                   ;
+    signal ex4_ovf_m1                              :std_ulogic                   ;
+    signal ex4_ovf_p0                              :std_ulogic                   ;
+    signal ex4_ovf_p1                              :std_ulogic                   ;
+    signal ex4_unf_m1                              :std_ulogic                   ;
+    signal ex4_unf_p0                              :std_ulogic                   ;
+
+
+    signal ex4_i_exp                               :std_ulogic_vector(1 to 13)  ;
+    signal ex4_ue1oe1_k                            :std_ulogic_vector(3 to 7)   ;
+    signal ex4_lzasub_sum                          :std_ulogic_vector(1 to 13)  ;  
+    signal ex4_lzasub_car                          :std_ulogic_vector(1 to 12)  ;
+    signal ex4_lzasub_p                            :std_ulogic_vector(1 to 12)  ;
+    signal ex4_lzasub_t                            :std_ulogic_vector(2 to 12)  ;
+    signal ex4_lzasub_g                            :std_ulogic_vector(2 to 12)  ;
+    signal ex4_lzasub_m1                           :std_ulogic_vector(1 to 13)  ;
+    signal ex4_lzasub_p0                           :std_ulogic_vector(1 to 13)  ;
+    signal ex4_lzasub_p1                           :std_ulogic_vector(1 to 13)  ;   
+    signal ex4_lzasub_c0                           :std_ulogic_vector(2 to 11)  ;
+    signal ex4_lzasub_c1                           :std_ulogic_vector(2 to 11)  ;
+    signal ex4_lzasub_s0                           :std_ulogic_vector(1 to 11)  ;
+    signal ex4_lzasub_s1                           :std_ulogic_vector(1 to 11)  ;
+    signal ex4_ovf_sum                             :std_ulogic_vector(1 to 13)  ;
+    signal ex4_ovf_car                             :std_ulogic_vector(1 to 12)  ;
+    signal ex4_ovf_g                               :std_ulogic_vector(2 to 12)  ;
+    signal ex4_ovf_t                               :std_ulogic_vector(2 to 12)  ;
+    signal ex4_ovf_p                               :std_ulogic_vector(1 to  1)  ;
+    signal ex4_unf_sum                             :std_ulogic_vector(1 to 13)  ;  
+    signal ex4_unf_car                             :std_ulogic_vector(1 to 12)  ;
+    signal ex4_unf_g                               :std_ulogic_vector(2 to 12)  ;
+    signal ex4_unf_t                               :std_ulogic_vector(2 to 12)  ;
+    signal ex4_unf_p                               :std_ulogic_vector(1 to 1)  ;
+    signal ex4_unf_ci0_02t11                       :std_ulogic;
+    signal ex4_unf_ci1_02t11                       :std_ulogic;
+    signal ex4_expo_p0                             :std_ulogic_vector(1 to 13)  ;
+    signal ex4_expo_p1                             :std_ulogic_vector(1 to 13)  ;
+    signal ex5_expo_p0                             :std_ulogic_vector(1 to 13)  ;
+    signal ex5_expo_p1                             :std_ulogic_vector(1 to 13)  ;
+    signal ex5_ue1oe1_k                            :std_ulogic_vector(3 to 7)   ;
+    signal ex5_ue1oe1_p0_p                         :std_ulogic_vector(3 to 7)   ;
+    signal ex5_ue1oe1_p0_t                         :std_ulogic_vector(4 to 6)   ;
+    signal ex5_ue1oe1_p0_g                         :std_ulogic_vector(4 to 7)   ;
+    signal ex5_ue1oe1_p0_c                         :std_ulogic_vector(4 to 7)   ;
+    signal ex5_ue1oe1_p1_p                         :std_ulogic_vector(3 to 7)   ;
+    signal ex5_ue1oe1_p1_t                         :std_ulogic_vector(4 to 6)   ;
+    signal ex5_ue1oe1_p1_g                         :std_ulogic_vector(4 to 7)   ;
+    signal ex5_ue1oe1_p1_c                         :std_ulogic_vector(4 to 7)   ;
+    signal ex4_lzasub_m1_c12                       :std_ulogic                  ;
+    signal ex4_lzasub_p0_c12                       :std_ulogic                  ;
+    signal ex4_lzasub_p1_c12                       :std_ulogic                  ;
+    signal ex4_may_ovf                             :std_ulogic                  ;
+    signal ex4_lza_amt_b                           :std_ulogic_vector(0 to 7)   ;
+    signal ex4_lza_amt                             :std_ulogic_vector(0 to 7)   ;
+    signal ex3_iexp                                :std_ulogic_vector(1 to 13)  ;
+    signal ex3_sp                                  :std_ulogic                  ;
+    signal ex3_may_ovf                             :std_ulogic                  ;
+    signal ex4_unf_c2_m1  :std_ulogic;
+    signal ex4_unf_c2_p0  :std_ulogic;
+    signal ex4_c2_m1  :std_ulogic;
+    signal ex4_c2_p0  :std_ulogic;
+    signal ex4_c2_p1  :std_ulogic;
+    signal ex5_ue1oe1_p0_g2_b :std_ulogic_vector(4 to 7);
+    signal ex5_ue1oe1_p0_t2_b :std_ulogic_vector(4 to 5);
+    signal ex5_ue1oe1_p1_g2_b :std_ulogic_vector(4 to 7);
+    signal ex5_ue1oe1_p1_t2_b :std_ulogic_vector(4 to 5);
+ signal ex4_unf_g2_02t03  :std_ulogic;
+ signal ex4_unf_g2_04t05  :std_ulogic;
+ signal ex4_unf_g2_06t07  :std_ulogic;
+ signal ex4_unf_g2_08t09  :std_ulogic;
+ signal ex4_unf_g2_10t11  :std_ulogic;
+ signal ex4_unf_ci0_g2    :std_ulogic;
+ signal ex4_unf_ci1_g2    :std_ulogic;
+ signal ex4_unf_t2_02t03  :std_ulogic;
+ signal ex4_unf_t2_04t05  :std_ulogic;
+ signal ex4_unf_t2_06t07  :std_ulogic;
+ signal ex4_unf_t2_08t09  :std_ulogic;
+ signal ex4_unf_t2_10t11  :std_ulogic;
+ signal ex4_unf_g4_02t05  :std_ulogic;
+ signal ex4_unf_g4_06t09  :std_ulogic;
+ signal ex4_unf_ci0_g4    :std_ulogic;
+ signal ex4_unf_ci1_g4    :std_ulogic;
+ signal ex4_unf_t4_02t05  :std_ulogic;
+ signal ex4_unf_t4_06t09  :std_ulogic;
+ signal ex4_unf_g8_02t09  :std_ulogic;
+ signal ex4_unf_ci0_g8    :std_ulogic;
+ signal ex4_unf_ci1_g8    :std_ulogic;
+ signal ex4_unf_t8_02t09  :std_ulogic;
+
+    signal ex4_ovf_ci0_02t11                       :std_ulogic;
+    signal ex4_ovf_ci1_02t11                       :std_ulogic;
+
+    signal ex4_ovf_g2_02t03 :std_ulogic;
+    signal ex4_ovf_g2_04t05 :std_ulogic;
+    signal ex4_ovf_g2_06t07 :std_ulogic;
+    signal ex4_ovf_g2_08t09 :std_ulogic;
+    signal ex4_ovf_g2_ci0   :std_ulogic;
+    signal ex4_ovf_g2_ci1   :std_ulogic;
+    signal ex4_ovf_t2_02t03 :std_ulogic;
+    signal ex4_ovf_t2_04t05 :std_ulogic;
+    signal ex4_ovf_t2_06t07 :std_ulogic;
+    signal ex4_ovf_t2_08t09 :std_ulogic;
+    signal ex4_ovf_g4_02t05 :std_ulogic;
+    signal ex4_ovf_g4_06t09 :std_ulogic;
+    signal ex4_ovf_g4_ci0   :std_ulogic;
+    signal ex4_ovf_g4_ci1   :std_ulogic;
+    signal ex4_ovf_t4_02t05 :std_ulogic;
+    signal ex4_ovf_t4_06t09 :std_ulogic;
+    signal ex4_ovf_g8_02t09 :std_ulogic;
+    signal ex4_ovf_g8_ci0   :std_ulogic;
+    signal ex4_ovf_g8_ci1   :std_ulogic;
+    signal ex4_ovf_t8_02t09 :std_ulogic;
+
+    signal ex4_lzasub_gg02 :std_ulogic_vector(2 to 11);
+    signal ex4_lzasub_gt02 :std_ulogic_vector(2 to 11);
+    signal ex4_lzasub_gg04 :std_ulogic_vector(2 to 11);
+    signal ex4_lzasub_gt04 :std_ulogic_vector(2 to 11);
+    signal ex4_lzasub_gg08 :std_ulogic_vector(2 to 11);
+    signal ex4_lzasub_gt08 :std_ulogic_vector(2 to 11);
+    signal ex4_sh_rgt_en_b :std_ulogic;
+
+    signal ex3_may_ov_usual :std_ulogic;
+
+
+
+  signal ex4_ovf_calc            :std_ulogic;
+  signal ex4_ovf_if_calc         :std_ulogic;
+  signal ex4_unf_calc            :std_ulogic;
+  signal ex4_unf_tbl             :std_ulogic;
+  signal ex4_unf_tbl_spec_e      :std_ulogic;
+  signal ex4_ov_en               :std_ulogic;
+  signal ex4_ov_en_oe0           :std_ulogic;
+  signal ex4_sel_ov_spec         :std_ulogic;
+  signal ex4_unf_en_nedge        :std_ulogic;
+  signal ex4_unf_ue0_nestsp       :std_ulogic;
+  signal ex4_sel_k_part_f        :std_ulogic;
+  signal ex4_sel_k_part_e        :std_ulogic;
+  signal ex5_ovf_calc            :std_ulogic;
+  signal ex5_ovf_if_calc         :std_ulogic;
+  signal ex5_unf_calc            :std_ulogic;
+  signal ex5_unf_tbl             :std_ulogic;
+  signal ex5_unf_tbl_b           :std_ulogic;
+  signal ex5_unf_tbl_spec_e      :std_ulogic;
+  signal ex5_ov_en               :std_ulogic;
+  signal ex5_ov_en_oe0           :std_ulogic;
+  signal ex5_sel_ov_spec         :std_ulogic;
+  signal ex5_unf_en_nedge        :std_ulogic;
+  signal ex5_unf_ue0_nestsp      :std_ulogic;
+  signal ex5_sel_k_part_f        :std_ulogic;
+  signal ex5_sel_ov_spec_b     :std_ulogic;
+  signal ex5_ovf_b             :std_ulogic;
+  signal ex5_ovf_if_b          :std_ulogic;
+  signal ex5_ovf_oe0_b         :std_ulogic;
+  signal ex5_ovf_if_oe0_b      :std_ulogic;
+  signal ex5_unf_b             :std_ulogic;
+  signal ex5_unf_ue0_b         :std_ulogic;
+  signal ex5_sel_k_part_f_b    :std_ulogic;
+  signal ex5_unf_tbl_spec_e_b  :std_ulogic;
+  signal ex4_sel_est :std_ulogic;
+  signal ex4_est_sp :std_ulogic;
+
+signal ex4_expo_p0_0_b, ex4_expo_p0_1_b, ex4_expo_p1_0_b, ex4_expo_p1_1_b :std_ulogic_vector(1 to 13) ;
+signal ex4_ovf_calc_0_b, ex4_ovf_calc_1_b, ex4_ovf_if_calc_0_b, ex4_ovf_if_calc_1_b, ex4_unf_calc_0_b, ex4_unf_calc_1_b :std_ulogic ;
+   signal ex5_d1clk, ex5_d2clk :std_ulogic ; 
+   signal ex5_lclk :clk_logic; 
+   signal unused :std_ulogic ;
+
+-- synopsys translate_off
+
+-- synopsys translate_on
+
+   
+begin 
+
+unused <= 
+     or_reduce( ex4_expo_p0(1 to 13) ) or 
+     or_reduce( ex4_expo_p1(1 to 13) ) or 
+                ex4_ovf_calc           or 
+                ex4_ovf_if_calc        or 
+                ex4_unf_calc           ;
+
+    
+    thold_reg_0:  tri_plat  generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,  
+         flush     => flush ,
+         din(0)    => thold_1,   
+         q(0)      => thold_0  ); 
+    
+    sg_reg_0:  tri_plat     generic map (expand_type => expand_type) port map (
+         vd        => vdd,
+         gd        => gnd,
+         nclk      => nclk,
+         flush     => flush ,
+         din(0)    => sg_1  ,     
+         q(0)      => sg_0  );   
+
+
+    lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
+        clkoff_b     => clkoff_b,
+        thold        => thold_0,  
+        sg           => sg_0,
+        act_dis      => act_dis,
+        forcee => forcee,
+        thold_b      => thold_0_b );
+
+    ex5_lcb : tri_lcbnd generic map (expand_type => expand_type) port map( 
+        delay_lclkr =>  delay_lclkr(5) ,
+        mpw1_b      =>  mpw1_b(5)      ,
+        mpw2_b      =>  mpw2_b(1)      ,
+        forcee => forcee,
+        nclk        =>  nclk        ,
+        vd          =>  vdd         ,
+        gd          =>  gnd         ,
+        act         =>  ex4_act     ,
+        sg          =>  sg_0        ,
+        thold_b     =>  thold_0_b   ,
+        d1clk       =>  ex5_d1clk   ,
+        d2clk       =>  ex5_d2clk   ,
+        lclk        =>  ex5_lclk   );
+
+
+ 
+
+    ex2_act <= not ex2_act_b;
+ 
+    act_lat:  tri_rlmreg_p generic map (width=> 5, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(4)   ,
+        mpw1_b           => mpw1_b(4)        ,
+        mpw2_b           => mpw2_b(0)        ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => fpu_enable, 
+        scout            => act_so   ,                     
+        scin             => act_si   ,                   
+         din(0)             => act_spare_unused(0),
+         din(1)             => act_spare_unused(1),
+         din(2)             => ex2_act,
+         din(3)             => ex3_act,
+         din(4)             => act_spare_unused(2),
+        dout(0)             => act_spare_unused(0),
+        dout(1)             => act_spare_unused(1),
+        dout(2)             => ex3_act,
+        dout(3)             => ex4_act,
+        dout(4)             => act_spare_unused(2) );
+
+
+        
+       ex3_iexp(1 to 13) <=
+             ( (1 to 13=> not f_pic_ex3_sel_est) and f_eie_ex3_iexp(1 to 13) ) or
+             ( (1 to 13=>     f_pic_ex3_sel_est) and f_tbe_ex3_expo(1 to 13) ) ;
+
+       ex3_sp               <= not f_pic_ex3_sp_b;
+
+
+
+
+       ex3_may_ovf <=
+                ( ex3_may_ov_usual and  not f_pic_ex3_sel_est) or
+                ( f_tbe_ex3_may_ov and      f_pic_ex3_sel_est);
+
+       ex3_may_ov_usual <=
+            (not f_eie_ex3_iexp(1) and  f_eie_ex3_iexp(2)                                             ) or 
+            (not f_eie_ex3_iexp(1) and  f_eie_ex3_iexp(3) and f_eie_ex3_iexp(4)                       ) or
+            (not f_eie_ex3_iexp(1) and  f_eie_ex3_iexp(3) and f_eie_ex3_iexp(5)                       ) or
+            (not f_eie_ex3_iexp(1) and  f_eie_ex3_iexp(3) and f_eie_ex3_iexp(6)                       ) or
+            (not f_eie_ex3_iexp(1) and  f_eie_ex3_iexp(3) and f_eie_ex3_iexp(7)                       ) or
+            (not f_eie_ex3_iexp(1) and  f_eie_ex3_iexp(3) and f_eie_ex3_iexp(8) and f_eie_ex3_iexp(9) );
+
+
+    ex4_iexp_lat:  tri_rlmreg_p generic map (width=> 16, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(4)   ,
+        mpw1_b           => mpw1_b(4)        ,
+        mpw2_b           => mpw2_b(0)        ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex3_act, 
+        scout            => ex4_iexp_so  ,                      
+        scin             => ex4_iexp_si  ,                    
+         din(0)             => ex3_sp ,
+         din(1 to 13)       => ex3_iexp(1 to 13) ,
+         din(14)            => ex3_may_ovf ,
+         din(15)            => f_pic_ex3_sel_est,
+        dout(0)             => ex4_sp               ,
+        dout(1 to 13)       => ex4_i_exp(1 to 13)   ,
+        dout(14)            => ex4_may_ovf          ,
+        dout(15)            => ex4_sel_est         );
+
+        f_eov_ex4_may_ovf <= ex4_may_ovf;
+ 
+
+
+    ex4_ue1oe1_k(3) <= (not ex4_may_ovf and not ex4_sp) or
+                       (    ex4_may_ovf and     ex4_sp) ;
+
+    ex4_ue1oe1_k(4) <= (                not     ex4_sp) or
+                       (    ex4_may_ovf and     ex4_sp) ;
+
+    ex4_ue1oe1_k(5) <= (    ex4_may_ovf and     ex4_sp) ;
+
+    ex4_ue1oe1_k(6) <= (not ex4_may_ovf and     ex4_sp) ;
+    ex4_ue1oe1_k(7) <= (                        ex4_sp) ;
+
+
+
+
+     ex4_lza_amt_b(0 to 7) <= not f_lza_ex4_lza_amt_eov(0 to 7);
+     ex4_lza_amt  (0 to 7) <=     f_lza_ex4_lza_amt_eov(0 to 7);
+     ex4_sh_rgt_en_b <= not f_lza_ex4_sh_rgt_en_eov;
+
+    ex4_lzasub_sum( 1) <=      ex4_sh_rgt_en_b  xor ex4_i_exp( 1);
+    ex4_lzasub_sum( 2) <=      ex4_sh_rgt_en_b  xor ex4_i_exp( 2);
+    ex4_lzasub_sum( 3) <=      ex4_sh_rgt_en_b  xor ex4_i_exp( 3);
+    ex4_lzasub_sum( 4) <=      ex4_sh_rgt_en_b  xor ex4_i_exp( 4);
+    ex4_lzasub_sum( 5) <=      ex4_sh_rgt_en_b  xor ex4_i_exp( 5);
+    ex4_lzasub_sum( 6) <=      ex4_lza_amt_b(0) xor ex4_i_exp( 6);
+    ex4_lzasub_sum( 7) <=      ex4_lza_amt_b(1) xor ex4_i_exp( 7);
+    ex4_lzasub_sum( 8) <=      ex4_lza_amt_b(2) xor ex4_i_exp( 8);
+    ex4_lzasub_sum( 9) <=      ex4_lza_amt_b(3) xor ex4_i_exp( 9);
+    ex4_lzasub_sum(10) <=      ex4_lza_amt_b(4) xor ex4_i_exp(10);
+    ex4_lzasub_sum(11) <=      ex4_lza_amt_b(5) xor ex4_i_exp(11);
+    ex4_lzasub_sum(12) <=      ex4_lza_amt_b(6) xor ex4_i_exp(12);
+    ex4_lzasub_sum(13) <= not( ex4_lza_amt_b(7) xor ex4_i_exp(13) );
+    
+    ex4_lzasub_car( 1) <= ex4_sh_rgt_en_b  and ex4_i_exp( 2);
+    ex4_lzasub_car( 2) <= ex4_sh_rgt_en_b  and ex4_i_exp( 3);
+    ex4_lzasub_car( 3) <= ex4_sh_rgt_en_b  and ex4_i_exp( 4);
+    ex4_lzasub_car( 4) <= ex4_sh_rgt_en_b  and ex4_i_exp( 5);
+    ex4_lzasub_car( 5) <= ex4_lza_amt_b(0) and ex4_i_exp( 6);
+    ex4_lzasub_car( 6) <= ex4_lza_amt_b(1) and ex4_i_exp( 7);
+    ex4_lzasub_car( 7) <= ex4_lza_amt_b(2) and ex4_i_exp( 8);
+    ex4_lzasub_car( 8) <= ex4_lza_amt_b(3) and ex4_i_exp( 9);
+    ex4_lzasub_car( 9) <= ex4_lza_amt_b(4) and ex4_i_exp(10);
+    ex4_lzasub_car(10) <= ex4_lza_amt_b(5) and ex4_i_exp(11);
+    ex4_lzasub_car(11) <= ex4_lza_amt_b(6) and ex4_i_exp(12);
+    ex4_lzasub_car(12) <= ex4_lza_amt_b(7) or  ex4_i_exp(13);
+
+    ex4_lzasub_p(1 to 12) <= ex4_lzasub_car(1 to 12) xor ex4_lzasub_sum(1 to 12);
+    ex4_lzasub_t(2 to 12) <= ex4_lzasub_car(2 to 12)  or ex4_lzasub_sum(2 to 12);    
+    ex4_lzasub_g(2 to 12) <= ex4_lzasub_car(2 to 12) and ex4_lzasub_sum(2 to 12);
+    
+
+
+    ex4_lzasub_m1_c12    <=  ex4_lzasub_g(12);
+    ex4_lzasub_p0_c12    <=  ex4_lzasub_g(12) or (ex4_lzasub_t(12) and ex4_lzasub_sum(13) );
+    ex4_lzasub_p1_c12    <=  ex4_lzasub_t(12);
+
+    ex4_lzasub_m1(13)    <=     ex4_lzasub_sum(13); 
+    ex4_lzasub_p0(13)    <= not ex4_lzasub_sum(13); 
+    ex4_lzasub_p1(13)    <=     ex4_lzasub_sum(13); 
+
+    ex4_lzasub_m1(12)    <=      ex4_lzasub_p(12);                           
+    ex4_lzasub_p0(12)    <=      ex4_lzasub_p(12) xor ex4_lzasub_sum(13);    
+    ex4_lzasub_p1(12)    <=  not ex4_lzasub_p(12);                           
+
+   
+
+
+    ex4_lzasub_gg02(11) <= ex4_lzasub_g(11) ;
+    ex4_lzasub_gg02(10) <= ex4_lzasub_g(10) or ( ex4_lzasub_t(10) and ex4_lzasub_g(11) );
+    ex4_lzasub_gg02( 9) <= ex4_lzasub_g( 9) or ( ex4_lzasub_t( 9) and ex4_lzasub_g(10) );
+    ex4_lzasub_gg02( 8) <= ex4_lzasub_g( 8) or ( ex4_lzasub_t( 8) and ex4_lzasub_g( 9) );
+    ex4_lzasub_gg02( 7) <= ex4_lzasub_g( 7) or ( ex4_lzasub_t( 7) and ex4_lzasub_g( 8) );
+    ex4_lzasub_gg02( 6) <= ex4_lzasub_g( 6) or ( ex4_lzasub_t( 6) and ex4_lzasub_g( 7) );
+    ex4_lzasub_gg02( 5) <= ex4_lzasub_g( 5) or ( ex4_lzasub_t( 5) and ex4_lzasub_g( 6) );
+    ex4_lzasub_gg02( 4) <= ex4_lzasub_g( 4) or ( ex4_lzasub_t( 4) and ex4_lzasub_g( 5) );
+    ex4_lzasub_gg02( 3) <= ex4_lzasub_g( 3) or ( ex4_lzasub_t( 3) and ex4_lzasub_g( 4) );
+    ex4_lzasub_gg02( 2) <= ex4_lzasub_g( 2) or ( ex4_lzasub_t( 2) and ex4_lzasub_g( 3) );
+
+    ex4_lzasub_gt02(11) <=                                            ex4_lzasub_t(11) ;
+    ex4_lzasub_gt02(10) <= ex4_lzasub_g(10) or ( ex4_lzasub_t(10) and ex4_lzasub_t(11) );
+    ex4_lzasub_gt02( 9) <=                     ( ex4_lzasub_t( 9) and ex4_lzasub_t(10) );
+    ex4_lzasub_gt02( 8) <=                     ( ex4_lzasub_t( 8) and ex4_lzasub_t( 9) );
+    ex4_lzasub_gt02( 7) <=                     ( ex4_lzasub_t( 7) and ex4_lzasub_t( 8) );
+    ex4_lzasub_gt02( 6) <=                     ( ex4_lzasub_t( 6) and ex4_lzasub_t( 7) );
+    ex4_lzasub_gt02( 5) <=                     ( ex4_lzasub_t( 5) and ex4_lzasub_t( 6) );
+    ex4_lzasub_gt02( 4) <=                     ( ex4_lzasub_t( 4) and ex4_lzasub_t( 5) );
+    ex4_lzasub_gt02( 3) <=                     ( ex4_lzasub_t( 3) and ex4_lzasub_t( 4) );
+    ex4_lzasub_gt02( 2) <=                     ( ex4_lzasub_t( 2) and ex4_lzasub_t( 3) );
+
+    ex4_lzasub_gg04(11) <= ex4_lzasub_gg02(11) ;
+    ex4_lzasub_gg04(10) <= ex4_lzasub_gg02(10) ;
+    ex4_lzasub_gg04( 9) <= ex4_lzasub_gg02( 9) or ( ex4_lzasub_gt02( 9) and ex4_lzasub_gg02(11) );
+    ex4_lzasub_gg04( 8) <= ex4_lzasub_gg02( 8) or ( ex4_lzasub_gt02( 8) and ex4_lzasub_gg02(10) );
+    ex4_lzasub_gg04( 7) <= ex4_lzasub_gg02( 7) or ( ex4_lzasub_gt02( 7) and ex4_lzasub_gg02( 9) );
+    ex4_lzasub_gg04( 6) <= ex4_lzasub_gg02( 6) or ( ex4_lzasub_gt02( 6) and ex4_lzasub_gg02( 8) );
+    ex4_lzasub_gg04( 5) <= ex4_lzasub_gg02( 5) or ( ex4_lzasub_gt02( 5) and ex4_lzasub_gg02( 7) );
+    ex4_lzasub_gg04( 4) <= ex4_lzasub_gg02( 4) or ( ex4_lzasub_gt02( 4) and ex4_lzasub_gg02( 6) );
+    ex4_lzasub_gg04( 3) <= ex4_lzasub_gg02( 3) or ( ex4_lzasub_gt02( 3) and ex4_lzasub_gg02( 5) );
+    ex4_lzasub_gg04( 2) <= ex4_lzasub_gg02( 2) or ( ex4_lzasub_gt02( 2) and ex4_lzasub_gg02( 4) );
+
+    ex4_lzasub_gt04(11) <= ex4_lzasub_gt02(11) ;
+    ex4_lzasub_gt04(10) <= ex4_lzasub_gt02(10) ;
+    ex4_lzasub_gt04( 9) <= ex4_lzasub_gg02( 9) or ( ex4_lzasub_gt02( 9) and ex4_lzasub_gt02(11) );
+    ex4_lzasub_gt04( 8) <= ex4_lzasub_gg02( 8) or ( ex4_lzasub_gt02( 8) and ex4_lzasub_gt02(10) );
+    ex4_lzasub_gt04( 7) <=                        ( ex4_lzasub_gt02( 7) and ex4_lzasub_gt02( 9) );
+    ex4_lzasub_gt04( 6) <=                        ( ex4_lzasub_gt02( 6) and ex4_lzasub_gt02( 8) );
+    ex4_lzasub_gt04( 5) <=                        ( ex4_lzasub_gt02( 5) and ex4_lzasub_gt02( 7) );
+    ex4_lzasub_gt04( 4) <=                        ( ex4_lzasub_gt02( 4) and ex4_lzasub_gt02( 6) );
+    ex4_lzasub_gt04( 3) <=                        ( ex4_lzasub_gt02( 3) and ex4_lzasub_gt02( 5) );
+    ex4_lzasub_gt04( 2) <=                        ( ex4_lzasub_gt02( 2) and ex4_lzasub_gt02( 4) );
+
+
+    ex4_lzasub_gg08(11) <= ex4_lzasub_gg04(11) ;
+    ex4_lzasub_gg08(10) <= ex4_lzasub_gg04(10) ;
+    ex4_lzasub_gg08( 9) <= ex4_lzasub_gg04( 9) ;
+    ex4_lzasub_gg08( 8) <= ex4_lzasub_gg04( 8) ;
+    ex4_lzasub_gg08( 7) <= ex4_lzasub_gg04( 7) or ( ex4_lzasub_gt04( 7) and ex4_lzasub_gg04(11) );
+    ex4_lzasub_gg08( 6) <= ex4_lzasub_gg04( 6) or ( ex4_lzasub_gt04( 6) and ex4_lzasub_gg04(10) );
+    ex4_lzasub_gg08( 5) <= ex4_lzasub_gg04( 5) or ( ex4_lzasub_gt04( 5) and ex4_lzasub_gg04( 9) );
+    ex4_lzasub_gg08( 4) <= ex4_lzasub_gg04( 4) or ( ex4_lzasub_gt04( 4) and ex4_lzasub_gg04( 8) );
+    ex4_lzasub_gg08( 3) <= ex4_lzasub_gg04( 3) or ( ex4_lzasub_gt04( 3) and ex4_lzasub_gg04( 7) );
+    ex4_lzasub_gg08( 2) <= ex4_lzasub_gg04( 2) or ( ex4_lzasub_gt04( 2) and ex4_lzasub_gg04( 6) );
+
+    ex4_lzasub_gt08(11) <= ex4_lzasub_gt04(11) ;
+    ex4_lzasub_gt08(10) <= ex4_lzasub_gt04(10) ;
+    ex4_lzasub_gt08( 9) <= ex4_lzasub_gt04( 9) ;
+    ex4_lzasub_gt08( 8) <= ex4_lzasub_gt04( 8) ;
+    ex4_lzasub_gt08( 7) <= ex4_lzasub_gg04( 7) or ( ex4_lzasub_gt04( 7) and ex4_lzasub_gt04(11) );
+    ex4_lzasub_gt08( 6) <= ex4_lzasub_gg04( 6) or ( ex4_lzasub_gt04( 6) and ex4_lzasub_gt04(10) );
+    ex4_lzasub_gt08( 5) <= ex4_lzasub_gg04( 5) or ( ex4_lzasub_gt04( 5) and ex4_lzasub_gt04( 9) );
+    ex4_lzasub_gt08( 4) <= ex4_lzasub_gg04( 4) or ( ex4_lzasub_gt04( 4) and ex4_lzasub_gt04( 8) );
+    ex4_lzasub_gt08( 3) <=                        ( ex4_lzasub_gt04( 3) and ex4_lzasub_gt04( 7) );
+    ex4_lzasub_gt08( 2) <=                        ( ex4_lzasub_gt04( 2) and ex4_lzasub_gt04( 6) );
+
+
+    ex4_lzasub_c0(11) <= ex4_lzasub_gg08(11) ; 
+    ex4_lzasub_c0(10) <= ex4_lzasub_gg08(10) ; 
+    ex4_lzasub_c0( 9) <= ex4_lzasub_gg08( 9) ; 
+    ex4_lzasub_c0( 8) <= ex4_lzasub_gg08( 8) ; 
+    ex4_lzasub_c0( 7) <= ex4_lzasub_gg08( 7) ; 
+    ex4_lzasub_c0( 6) <= ex4_lzasub_gg08( 6) ; 
+    ex4_lzasub_c0( 5) <= ex4_lzasub_gg08( 5) ; 
+    ex4_lzasub_c0( 4) <= ex4_lzasub_gg08( 4) ; 
+    ex4_lzasub_c0( 3) <= ex4_lzasub_gg08( 3) or ( ex4_lzasub_gt08( 3) and ex4_lzasub_gg08(11) ); 
+    ex4_lzasub_c0( 2) <= ex4_lzasub_gg08( 2) or ( ex4_lzasub_gt08( 2) and ex4_lzasub_gg08(10) ); 
+
+    ex4_lzasub_c1(11) <= ex4_lzasub_gt08(11) ; 
+    ex4_lzasub_c1(10) <= ex4_lzasub_gt08(10) ; 
+    ex4_lzasub_c1( 9) <= ex4_lzasub_gt08( 9) ; 
+    ex4_lzasub_c1( 8) <= ex4_lzasub_gt08( 8) ; 
+    ex4_lzasub_c1( 7) <= ex4_lzasub_gt08( 7) ; 
+    ex4_lzasub_c1( 6) <= ex4_lzasub_gt08( 6) ; 
+    ex4_lzasub_c1( 5) <= ex4_lzasub_gt08( 5) ; 
+    ex4_lzasub_c1( 4) <= ex4_lzasub_gt08( 4) ; 
+    ex4_lzasub_c1( 3) <= ex4_lzasub_gg08( 3) or ( ex4_lzasub_gt08( 3) and ex4_lzasub_gt08(11) ); 
+    ex4_lzasub_c1( 2) <= ex4_lzasub_gg08( 2) or ( ex4_lzasub_gt08( 2) and ex4_lzasub_gt08(10) ); 
+
+
+
+
+
+    ex4_lzasub_s0(1 to 11) <= ex4_lzasub_p(1 to 11) xor (ex4_lzasub_c0(2 to 11) & tidn) ;
+    ex4_lzasub_s1(1 to 11) <= ex4_lzasub_p(1 to 11) xor (ex4_lzasub_c1(2 to 11) & tiup) ;
+
+    ex4_lzasub_m1(1 to 11) <=
+         (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_m1_c12) ) or 
+         (ex4_lzasub_s1(1 to 11) and (1 to 11 =>     ex4_lzasub_m1_c12) );
+
+    ex4_lzasub_p0(1 to 11) <=
+         (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_p0_c12) ) or 
+         (ex4_lzasub_s1(1 to 11) and (1 to 11 =>     ex4_lzasub_p0_c12) ); 
+
+    ex4_lzasub_p1(1 to 11) <=
+         (ex4_lzasub_s0(1 to 11) and (1 to 11 => not ex4_lzasub_p1_c12) ) or 
+         (ex4_lzasub_s1(1 to 11) and (1 to 11 =>     ex4_lzasub_p1_c12) ); 
+
+
+
+    ex4_ovf_sum( 1) <=     ex4_sh_rgt_en_b xor not ex4_i_exp( 1);            
+    ex4_ovf_sum( 2) <=     ex4_sh_rgt_en_b xor not ex4_i_exp( 2);            
+    ex4_ovf_sum( 3) <=     ex4_sh_rgt_en_b xor     ex4_i_exp( 3);            
+    ex4_ovf_sum( 4) <=     ex4_sh_rgt_en_b xor     ex4_i_exp( 4) xor ex4_sp; 
+    ex4_ovf_sum( 5) <=     ex4_sh_rgt_en_b xor     ex4_i_exp( 5) xor ex4_sp; 
+    ex4_ovf_sum( 6) <= not ex4_lza_amt(0)  xor     ex4_i_exp( 6) xor ex4_sp; 
+    ex4_ovf_sum( 7) <= not ex4_lza_amt(1)  xor     ex4_i_exp( 7);            
+    ex4_ovf_sum( 8) <= not ex4_lza_amt(2)  xor     ex4_i_exp( 8);            
+    ex4_ovf_sum( 9) <= not ex4_lza_amt(3)  xor     ex4_i_exp( 9);            
+    ex4_ovf_sum(10) <= not ex4_lza_amt(4)  xor     ex4_i_exp(10);            
+    ex4_ovf_sum(11) <= not ex4_lza_amt(5)  xor     ex4_i_exp(11);            
+    ex4_ovf_sum(12) <= not ex4_lza_amt(6)  xor not ex4_i_exp(12);            
+    ex4_ovf_sum(13) <= not ex4_lza_amt(7)  xor     ex4_i_exp(13);            
+    
+    ex4_ovf_car( 1) <=      ex4_sh_rgt_en_b or  ex4_i_exp( 2);      
+    ex4_ovf_car( 2) <=      ex4_sh_rgt_en_b and ex4_i_exp( 3);      
+
+    ex4_ovf_car( 3) <= (    ex4_sp          and ex4_i_exp( 4) ) or  
+                       (    ex4_sh_rgt_en_b and ex4_i_exp( 4) ) or 
+                       (    ex4_sh_rgt_en_b and ex4_sp        ) ;
+
+    ex4_ovf_car( 4) <= (    ex4_sp          and ex4_i_exp( 5) ) or  
+                       (    ex4_sh_rgt_en_b and ex4_i_exp( 5) ) or 
+                       (    ex4_sh_rgt_en_b and ex4_sp        ) ;
+
+    ex4_ovf_car( 5) <= (not ex4_lza_amt(0)  and ex4_i_exp( 6) ) or  
+                       (not ex4_lza_amt(0)  and ex4_sp        ) or 
+                       (    ex4_sp          and ex4_i_exp( 6) ) ;
+    ex4_ovf_car( 6) <= not ex4_lza_amt(1)   and ex4_i_exp( 7);      
+    ex4_ovf_car( 7) <= not ex4_lza_amt(2)   and ex4_i_exp( 8);      
+    ex4_ovf_car( 8) <= not ex4_lza_amt(3)   and ex4_i_exp( 9);      
+    ex4_ovf_car( 9) <= not ex4_lza_amt(4)   and ex4_i_exp(10);      
+    ex4_ovf_car(10) <= not ex4_lza_amt(5)   and ex4_i_exp(11);      
+    ex4_ovf_car(11) <= not ex4_lza_amt(6)   or  ex4_i_exp(12);      
+    ex4_ovf_car(12) <= not ex4_lza_amt(7)   and ex4_i_exp(13);      
+
+
+
+    ex4_ovf_g(2 to 12) <= ex4_ovf_car(2 to 12) and ex4_ovf_sum(2 to 12);
+    ex4_ovf_t(2 to 12) <= ex4_ovf_car(2 to 12) or  ex4_ovf_sum(2 to 12);
+    ex4_ovf_p(1)       <= ex4_ovf_car(1)       xor ex4_ovf_sum(1) ;
+
+
+    ex4_ovf_m1_co12 <=  ex4_ovf_g(12);
+    ex4_ovf_p0_co12 <=  ex4_ovf_g(12) or (ex4_ovf_t(12) and  ex4_ovf_sum(13) );
+    ex4_ovf_p1_co12 <=  ex4_ovf_t(12);
+
+
+
+    ex4_ovf_g2_02t03 <=  ex4_ovf_g( 2) or (ex4_ovf_t( 2) and ex4_ovf_g( 3) );
+    ex4_ovf_g2_04t05 <=  ex4_ovf_g( 4) or (ex4_ovf_t( 4) and ex4_ovf_g( 5) );
+    ex4_ovf_g2_06t07 <=  ex4_ovf_g( 6) or (ex4_ovf_t( 6) and ex4_ovf_g( 7) );
+    ex4_ovf_g2_08t09 <=  ex4_ovf_g( 8) or (ex4_ovf_t( 8) and ex4_ovf_g( 9) );
+    ex4_ovf_g2_ci0   <=  ex4_ovf_g(10) or (ex4_ovf_t(10) and ex4_ovf_g(11) );
+    ex4_ovf_g2_ci1   <=  ex4_ovf_g(10) or (ex4_ovf_t(10) and ex4_ovf_t(11) );
+
+    ex4_ovf_t2_02t03 <=                   (ex4_ovf_t( 2) and ex4_ovf_t( 3) );
+    ex4_ovf_t2_04t05 <=                   (ex4_ovf_t( 4) and ex4_ovf_t( 5) );
+    ex4_ovf_t2_06t07 <=                   (ex4_ovf_t( 6) and ex4_ovf_t( 7) );
+    ex4_ovf_t2_08t09 <=                   (ex4_ovf_t( 8) and ex4_ovf_t( 9) );
+
+    ex4_ovf_g4_02t05 <= ex4_ovf_g2_02t03 or ( ex4_ovf_t2_02t03 and ex4_ovf_g2_04t05 );
+    ex4_ovf_g4_06t09 <= ex4_ovf_g2_06t07 or ( ex4_ovf_t2_06t07 and ex4_ovf_g2_08t09 );
+    ex4_ovf_g4_ci0   <= ex4_ovf_g2_ci0;
+    ex4_ovf_g4_ci1   <= ex4_ovf_g2_ci1;
+
+    ex4_ovf_t4_02t05 <=                     ( ex4_ovf_t2_02t03 and ex4_ovf_t2_04t05 );
+    ex4_ovf_t4_06t09 <=                     ( ex4_ovf_t2_06t07 and ex4_ovf_t2_08t09 );
+
+    ex4_ovf_g8_02t09 <= ex4_ovf_g4_02t05 or ( ex4_ovf_t4_02t05 and ex4_ovf_g4_06t09 );
+    ex4_ovf_g8_ci0   <= ex4_ovf_g4_ci0;
+    ex4_ovf_g8_ci1   <= ex4_ovf_g4_ci1;
+
+    ex4_ovf_t8_02t09 <=                     ( ex4_ovf_t4_02t05 and ex4_ovf_t4_06t09 );
+
+
+    ex4_ovf_ci0_02t11 <= ex4_ovf_g8_02t09 or (ex4_ovf_t8_02t09 and ex4_ovf_g8_ci0 );
+    ex4_ovf_ci1_02t11 <= ex4_ovf_g8_02t09 or (ex4_ovf_t8_02t09 and ex4_ovf_g8_ci1 );
+    
+
+    ex4_c2_m1 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_m1_co12) ) ;
+    ex4_c2_p0 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_p0_co12) ) ;
+    ex4_c2_p1 <= (ex4_ovf_ci0_02t11 or (ex4_ovf_ci1_02t11 and ex4_ovf_p1_co12) ) ;
+   
+    ex4_ovf_m1 <= not ex4_ovf_p(1) xor ex4_c2_m1;
+    ex4_ovf_p0 <= not ex4_ovf_p(1) xor ex4_c2_p0;
+    ex4_ovf_p1 <= not ex4_ovf_p(1) xor ex4_c2_p1;
+   
+   
+
+
+    ex4_unf_sum( 1) <= ex4_sh_rgt_en_b    xor     ex4_i_exp( 1) xor ex4_sp; 
+    ex4_unf_sum( 2) <= ex4_sh_rgt_en_b    xor     ex4_i_exp( 2) xor ex4_sp; 
+    ex4_unf_sum( 3) <= ex4_sh_rgt_en_b    xor     ex4_i_exp( 3) xor ex4_sp; 
+    ex4_unf_sum( 4) <= ex4_sh_rgt_en_b    xor     ex4_i_exp( 4);            
+    ex4_unf_sum( 5) <= ex4_sh_rgt_en_b    xor     ex4_i_exp( 5);            
+    ex4_unf_sum( 6) <= not ex4_lza_amt(0) xor     ex4_i_exp( 6) xor ex4_sp; 
+    ex4_unf_sum( 7) <= not ex4_lza_amt(1) xor     ex4_i_exp( 7);            
+    ex4_unf_sum( 8) <= not ex4_lza_amt(2) xor     ex4_i_exp( 8);            
+    ex4_unf_sum( 9) <= not ex4_lza_amt(3) xor     ex4_i_exp( 9);            
+    ex4_unf_sum(10) <= not ex4_lza_amt(4) xor     ex4_i_exp(10);            
+    ex4_unf_sum(11) <= not ex4_lza_amt(5) xor     ex4_i_exp(11);            
+    ex4_unf_sum(12) <= not ex4_lza_amt(6) xor     ex4_i_exp(12);            
+    ex4_unf_sum(13) <= not ex4_lza_amt(7) xor     ex4_i_exp(13);            
+    
+    ex4_unf_car( 1) <= ( ex4_sp            and  ex4_i_exp( 2) ) or      
+                       ( ex4_sh_rgt_en_b   and  ex4_i_exp( 2) ) or 
+                       ( ex4_sh_rgt_en_b   and  ex4_sp        ) ;
+    ex4_unf_car( 2) <= ( ex4_sp            and  ex4_i_exp( 3) ) or      
+                       ( ex4_sh_rgt_en_b   and  ex4_i_exp( 3) ) or 
+                       ( ex4_sh_rgt_en_b   and  ex4_sp        ) ;
+    ex4_unf_car( 3) <=  ex4_sh_rgt_en_b    and ex4_i_exp( 4)         ;  
+    ex4_unf_car( 4) <=  ex4_sh_rgt_en_b    and ex4_i_exp( 5)         ;  
+    ex4_unf_car( 5) <= (not ex4_lza_amt(0) and ex4_i_exp( 6) ) or       
+                       (not ex4_lza_amt(0) and ex4_sp        ) or 
+                       (    ex4_sp           and ex4_i_exp( 6) ) ;
+    ex4_unf_car( 6) <= not ex4_lza_amt(1)  and ex4_i_exp( 7);           
+    ex4_unf_car( 7) <= not ex4_lza_amt(2)  and ex4_i_exp( 8);           
+    ex4_unf_car( 8) <= not ex4_lza_amt(3)  and ex4_i_exp( 9);           
+    ex4_unf_car( 9) <= not ex4_lza_amt(4)  and ex4_i_exp(10);           
+    ex4_unf_car(10) <= not ex4_lza_amt(5)  and ex4_i_exp(11);           
+    ex4_unf_car(11) <= not ex4_lza_amt(6)  and ex4_i_exp(12);           
+    ex4_unf_car(12) <= not ex4_lza_amt(7)  and ex4_i_exp(13);           
+
+
+
+    ex4_unf_g(2 to 12) <= ex4_unf_car(2 to 12) and ex4_unf_sum(2 to 12);
+    ex4_unf_t(2 to 12) <= ex4_unf_car(2 to 12) or  ex4_unf_sum(2 to 12);
+    ex4_unf_p(1)       <= ex4_unf_car(1)       xor ex4_unf_sum(1)      ; 
+
+
+    ex4_unf_m1_co12 <=  ex4_unf_g(12);
+    ex4_unf_p0_co12 <=  ex4_unf_g(12) or (ex4_unf_t(12) and  ex4_unf_sum(13) );
+
+
+
+
+    ex4_unf_g2_02t03  <= ex4_unf_g( 2) or (ex4_unf_t( 2) and ex4_unf_g( 3) );
+    ex4_unf_g2_04t05  <= ex4_unf_g( 4) or (ex4_unf_t( 4) and ex4_unf_g( 5) );
+    ex4_unf_g2_06t07  <= ex4_unf_g( 6) or (ex4_unf_t( 6) and ex4_unf_g( 7) );
+    ex4_unf_g2_08t09  <= ex4_unf_g( 8) or (ex4_unf_t( 8) and ex4_unf_g( 9) );
+    ex4_unf_g2_10t11  <= ex4_unf_g(10) or (ex4_unf_t(10) and ex4_unf_g(11) );
+    ex4_unf_ci0_g2    <= ex4_unf_g(12) ;
+    ex4_unf_ci1_g2    <= ex4_unf_t(12) ;
+
+    ex4_unf_t2_02t03  <=                  (ex4_unf_t( 2) and ex4_unf_t( 3) );
+    ex4_unf_t2_04t05  <=                  (ex4_unf_t( 4) and ex4_unf_t( 5) );
+    ex4_unf_t2_06t07  <=                  (ex4_unf_t( 6) and ex4_unf_t( 7) );
+    ex4_unf_t2_08t09  <=                  (ex4_unf_t( 8) and ex4_unf_t( 9) );
+    ex4_unf_t2_10t11  <=                  (ex4_unf_t(10) and ex4_unf_t(11) );
+
+    ex4_unf_g4_02t05  <= ex4_unf_g2_02t03 or (ex4_unf_t2_02t03 and ex4_unf_g2_04t05 );
+    ex4_unf_g4_06t09  <= ex4_unf_g2_06t07 or (ex4_unf_t2_06t07 and ex4_unf_g2_08t09 );
+    ex4_unf_ci0_g4    <= ex4_unf_g2_10t11 or (ex4_unf_t2_10t11 and ex4_unf_ci0_g2 );
+    ex4_unf_ci1_g4    <= ex4_unf_g2_10t11 or (ex4_unf_t2_10t11 and ex4_unf_ci1_g2 );
+
+    ex4_unf_t4_02t05  <=                     (ex4_unf_t2_02t03 and ex4_unf_t2_04t05 );
+    ex4_unf_t4_06t09  <=                     (ex4_unf_t2_06t07 and ex4_unf_t2_08t09 );
+
+
+    ex4_unf_g8_02t09  <= ex4_unf_g4_02t05 or (ex4_unf_t4_02t05 and ex4_unf_g4_06t09 );
+    ex4_unf_ci0_g8    <= ex4_unf_ci0_g4;
+    ex4_unf_ci1_g8    <= ex4_unf_ci1_g4;
+
+    ex4_unf_t8_02t09  <=                     (ex4_unf_t4_02t05 and ex4_unf_t4_06t09 );
+
+    ex4_unf_ci0_02t11 <= ex4_unf_g8_02t09 or ( ex4_unf_t8_02t09 and ex4_unf_ci0_g8); 
+    ex4_unf_ci1_02t11 <= ex4_unf_g8_02t09 or ( ex4_unf_t8_02t09 and ex4_unf_ci1_g8); 
+
+
+    ex4_unf_c2_m1 <= (ex4_unf_ci0_02t11 or (ex4_unf_ci1_02t11 and ex4_unf_m1_co12) ) ;
+    ex4_unf_c2_p0 <= (ex4_unf_ci0_02t11 or (ex4_unf_ci1_02t11 and ex4_unf_p0_co12) ) ;
+   
+    ex4_unf_m1 <= ex4_unf_p(1) xor ex4_unf_c2_m1;
+    ex4_unf_p0 <= ex4_unf_p(1) xor ex4_unf_c2_p0;
+
+
+  
+   u_expo_p0_0: ex4_expo_p0_0_b(1 to 13) <= not(ex4_lzasub_m1(1 to 13)   and (1 to 13 =>     f_nrm_ex4_extra_shift) );
+   u_expo_p0_1: ex4_expo_p0_1_b(1 to 13) <= not(ex4_lzasub_p0(1 to 13)   and (1 to 13 => not f_nrm_ex4_extra_shift) ) ; 
+   u_expo_p0:   ex4_expo_p0(1 to 13)     <= not(ex4_expo_p0_0_b(1 to 13) and  ex4_expo_p0_1_b(1 to 13));
+   
+   u_expo_p1_0: ex4_expo_p1_0_b(1 to 13) <= not(ex4_lzasub_p0(1 to 13)   and (1 to 13 =>     f_nrm_ex4_extra_shift) );
+   u_expo_p1_1: ex4_expo_p1_1_b(1 to 13) <= not(ex4_lzasub_p1(1 to 13)   and (1 to 13 => not f_nrm_ex4_extra_shift) ) ; 
+   u_expo_p1:   ex4_expo_p1(1 to 13)     <= not(ex4_expo_p1_0_b(1 to 13) and  ex4_expo_p1_1_b(1 to 13));
+   
+   u_ovf_calc_0: ex4_ovf_calc_0_b        <= not(ex4_ovf_m1             and                 f_nrm_ex4_extra_shift  ) ;
+   u_ovf_calc_1: ex4_ovf_calc_1_b        <= not(ex4_ovf_p0             and             not f_nrm_ex4_extra_shift  ) ;
+   u_ovf_calc:   ex4_ovf_calc            <= not(ex4_ovf_calc_0_b       and  ex4_ovf_calc_1_b ) ;
+   
+   u_ovf_if_calc_0: ex4_ovf_if_calc_0_b  <= not(ex4_ovf_p0             and                 f_nrm_ex4_extra_shift  ) ;
+   u_ovf_if_calc_1: ex4_ovf_if_calc_1_b  <= not(ex4_ovf_p1             and             not f_nrm_ex4_extra_shift  ) ;
+   u_ovf_if_calc:   ex4_ovf_if_calc      <= not(ex4_ovf_if_calc_0_b    and  ex4_ovf_if_calc_1_b ) ;
+   
+   u_unf_calc_0: ex4_unf_calc_0_b        <= not(ex4_unf_m1             and                 f_nrm_ex4_extra_shift  ) ;
+   u_unf_calc_1: ex4_unf_calc_1_b        <= not(ex4_unf_p0             and             not f_nrm_ex4_extra_shift  ) ;
+   u_unf_calc:   ex4_unf_calc            <= not(ex4_unf_calc_0_b       and  ex4_unf_calc_1_b ) ;
+   
+
+
+
+  ex4_est_sp              <= ex4_sel_est and ex4_sp;
+
+  ex4_unf_tbl             <= f_pic_ex4_uf_en and  f_tbl_ex4_unf_expo ;
+  ex4_unf_tbl_spec_e      <= (ex4_unf_tbl and not ex4_est_sp and not f_pic_ex4_ue) or ex4_sel_k_part_e;
+  ex4_ov_en               <= f_pic_ex4_ov_en ;
+  ex4_ov_en_oe0           <= f_pic_ex4_ov_en and not f_pic_ex4_oe;
+  ex4_sel_ov_spec         <= f_pic_ex4_sel_ov_spec;
+  ex4_unf_en_nedge        <= f_pic_ex4_uf_en and not f_lza_ex4_no_lza_edge;
+  ex4_unf_ue0_nestsp      <= f_pic_ex4_uf_en and not f_lza_ex4_no_lza_edge and not f_pic_ex4_ue and not(ex4_est_sp);
+  ex4_sel_k_part_e        <= f_pic_ex4_spec_sel_k_e or  f_pic_ex4_to_int_ov_all ;
+  ex4_sel_k_part_f        <= f_pic_ex4_spec_sel_k_f or  f_pic_ex4_to_int_ov_all ;
+
+
+
+
+    ex5_urnd0_lat:  entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 13, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK             => ex5_lclk                  ,
+        D1CLK            => ex5_d1clk                 ,
+        D2CLK            => ex5_d2clk                 ,
+        SCANIN           => ex5_urnd0_si              ,                    
+        SCANOUT          => ex5_urnd0_so              ,                      
+        A1               => ex4_expo_p0_0_b(1 to 13)  ,   
+        A2               => ex4_expo_p0_1_b(1 to 13)  ,
+        QB(0 to 12)      => ex5_expo_p0(1 to 13)     );
+
+    ex5_urnd1_lat:  entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 13, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK             => ex5_lclk                  ,
+        D1CLK            => ex5_d1clk                 ,
+        D2CLK            => ex5_d2clk                 ,
+        SCANIN           => ex5_urnd1_si              ,                    
+        SCANOUT          => ex5_urnd1_so              ,                      
+        A1               => ex4_expo_p1_0_b(1 to 13)  ,   
+        A2               => ex4_expo_p1_1_b(1 to 13)  ,
+        QB(0 to 12)      => ex5_expo_p1(1 to 13)     );
+   
+    ex5_ovctl_lat:  entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 3, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map ( 
+        vd          =>  vdd                  ,
+        gd          =>  gnd                  ,
+        LCLK             => ex5_lclk                  ,
+        D1CLK            => ex5_d1clk                 ,
+        D2CLK            => ex5_d2clk                 ,
+        SCANIN           => ex5_ovctl_si              ,                    
+        SCANOUT          => ex5_ovctl_so              ,                      
+        A1(0)             => ex4_ovf_calc_0_b         ,
+        A1(1)             => ex4_ovf_if_calc_0_b      ,
+        A1(2)             => ex4_unf_calc_0_b         ,
+        A2(0)             => ex4_ovf_calc_1_b         ,
+        A2(1)             => ex4_ovf_if_calc_1_b      ,
+        A2(2)             => ex4_unf_calc_1_b         ,
+        QB(0)            => ex5_ovf_calc              ,
+        QB(1)            => ex5_ovf_if_calc           ,
+        QB(2)            => ex5_unf_calc             );
+
+    ex5_misc_lat:  tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, needs_sreset => 0) port map ( 
+        forcee => forcee,
+        delay_lclkr      => delay_lclkr(5)   ,
+        mpw1_b           => mpw1_b(5)        ,
+        mpw2_b           => mpw2_b(1)        ,
+        vd               => vdd,
+        gd               => gnd,
+        nclk             => nclk, 
+        thold_b          => thold_0_b,
+        sg               => sg_0, 
+        act              => ex4_act, 
+        scout            => ex5_misc_so  ,                      
+        scin             => ex5_misc_si  ,                    
+         din(0)             => ex4_unf_tbl             ,
+         din(1)             => ex4_unf_tbl_spec_e      ,
+         din(2)             => ex4_ov_en               ,
+         din(3)             => ex4_ov_en_oe0           ,
+         din(4)             => ex4_sel_ov_spec         ,
+         din(5)             => ex4_unf_en_nedge        ,
+         din(6)             => ex4_unf_ue0_nestsp      ,
+         din(7)             => ex4_sel_k_part_f        ,
+         din(8 to 12)       => ex4_ue1oe1_k(3 to 7)    ,
+        dout(0)             => ex5_unf_tbl             ,
+        dout(1)             => ex5_unf_tbl_spec_e      ,
+        dout(2)             => ex5_ov_en               ,
+        dout(3)             => ex5_ov_en_oe0           ,
+        dout(4)             => ex5_sel_ov_spec         ,
+        dout(5)             => ex5_unf_en_nedge        ,
+        dout(6)             => ex5_unf_ue0_nestsp      ,
+        dout(7)             => ex5_sel_k_part_f        ,
+        dout(8 to 12)       => ex5_ue1oe1_k(3 to 7)   );
+
+
+
+   f_eov_ex5_expo_p0(1 to 13) <= ex5_expo_p0(1 to 13) ;
+   f_eov_ex5_expo_p1(1 to 13) <= ex5_expo_p1(1 to 13) ;
+
+
+
+    
+    ex5_sel_ov_spec_b     <= not(                      ex5_sel_ov_spec    );
+    ex5_ovf_b             <= not( ex5_ovf_calc     and ex5_ov_en          );
+    ex5_ovf_if_b          <= not( ex5_ovf_if_calc  and ex5_ov_en          );
+    ex5_ovf_oe0_b         <= not( ex5_ovf_calc     and ex5_ov_en_oe0      );
+    ex5_ovf_if_oe0_b      <= not( ex5_ovf_if_calc  and ex5_ov_en_oe0      );
+    ex5_unf_b             <= not( ex5_unf_calc     and ex5_unf_en_nedge   );
+    ex5_unf_ue0_b         <= not( ex5_unf_calc     and ex5_unf_ue0_nestsp );
+    ex5_sel_k_part_f_b    <= not(                      ex5_sel_k_part_f   );
+    ex5_unf_tbl_spec_e_b  <= not(                      ex5_unf_tbl_spec_e );
+    ex5_unf_tbl_b         <= not(                      ex5_unf_tbl        );
+    
+    
+    f_eov_ex5_ovf_expo     <= not( ex5_ovf_b        and ex5_sel_ov_spec_b  );
+    f_eov_ex5_ovf_if_expo  <= not( ex5_ovf_if_b     and ex5_sel_ov_spec_b  );
+    f_eov_ex5_sel_k_f      <= not( ex5_ovf_oe0_b    and ex5_sel_k_part_f_b );                         
+    f_eov_ex5_sel_kif_f    <= not( ex5_ovf_if_oe0_b and ex5_sel_k_part_f_b );
+    f_eov_ex5_unf_expo     <= not( ex5_unf_b        and ex5_unf_tbl_b      );
+    f_eov_ex5_sel_k_e      <= not( ex5_unf_ue0_b    and ex5_unf_tbl_spec_e_b and ex5_ovf_oe0_b    );
+    f_eov_ex5_sel_kif_e    <= not( ex5_unf_ue0_b    and ex5_unf_tbl_spec_e_b and ex5_ovf_if_oe0_b ); 
+    
+
+    f_eov_ex5_expo_p0_ue1oe1(3 to 6) <= ex5_ue1oe1_p0_p(3 to 6) xor ex5_ue1oe1_p0_c(4 to 7); 
+    f_eov_ex5_expo_p0_ue1oe1(7)      <= ex5_ue1oe1_p0_p(7);
+
+    ex5_ue1oe1_p0_p(3 to 7) <= ex5_expo_p0(3 to 7) xor ex5_ue1oe1_k(3 to 7);
+    ex5_ue1oe1_p0_g(4 to 7) <= ex5_expo_p0(4 to 7) and ex5_ue1oe1_k(4 to 7);
+    ex5_ue1oe1_p0_t(4 to 6) <= ex5_expo_p0(4 to 6) or  ex5_ue1oe1_k(4 to 6);
+
+
+    ex5_ue1oe1_p0_g2_b(7) <= not( ex5_ue1oe1_p0_g(7) ) ;
+    ex5_ue1oe1_p0_g2_b(6) <= not( ex5_ue1oe1_p0_g(6) or (ex5_ue1oe1_p0_t(6)  and ex5_ue1oe1_p0_g(7) )  );
+    ex5_ue1oe1_p0_g2_b(5) <= not( ex5_ue1oe1_p0_g(5) ) ;
+    ex5_ue1oe1_p0_g2_b(4) <= not( ex5_ue1oe1_p0_g(4) or (ex5_ue1oe1_p0_t(4)  and ex5_ue1oe1_p0_g(5) )  );
+
+    ex5_ue1oe1_p0_t2_b(5) <= not(                                                ex5_ue1oe1_p0_t(5) )   ;
+    ex5_ue1oe1_p0_t2_b(4) <= not(                       (ex5_ue1oe1_p0_t(4)  and ex5_ue1oe1_p0_t(5) )  );
+
+    ex5_ue1oe1_p0_c(7) <= not( ex5_ue1oe1_p0_g2_b(7) );
+    ex5_ue1oe1_p0_c(6) <= not( ex5_ue1oe1_p0_g2_b(6) );
+    ex5_ue1oe1_p0_c(5) <= not( ex5_ue1oe1_p0_g2_b(5) and (ex5_ue1oe1_p0_t2_b(5)  or  ex5_ue1oe1_p0_g2_b(6) ) );
+    ex5_ue1oe1_p0_c(4) <= not( ex5_ue1oe1_p0_g2_b(4) and (ex5_ue1oe1_p0_t2_b(4)  or  ex5_ue1oe1_p0_g2_b(6) ) );
+
+
+    f_eov_ex5_expo_p1_ue1oe1(3 to 6) <= ex5_ue1oe1_p1_p(3 to 6) xor ex5_ue1oe1_p1_c(4 to 7); 
+    f_eov_ex5_expo_p1_ue1oe1(7)      <= ex5_ue1oe1_p1_p(7);
+
+    ex5_ue1oe1_p1_p(3 to 7) <= ex5_expo_p1(3 to 7) xor ex5_ue1oe1_k(3 to 7);
+    ex5_ue1oe1_p1_g(4 to 7) <= ex5_expo_p1(4 to 7) and ex5_ue1oe1_k(4 to 7);
+    ex5_ue1oe1_p1_t(4 to 6) <= ex5_expo_p1(4 to 6) or  ex5_ue1oe1_k(4 to 6);
+
+
+    ex5_ue1oe1_p1_g2_b(7) <= not( ex5_ue1oe1_p1_g(7) ) ;
+    ex5_ue1oe1_p1_g2_b(6) <= not( ex5_ue1oe1_p1_g(6) or (ex5_ue1oe1_p1_t(6)  and ex5_ue1oe1_p1_g(7) )  );
+    ex5_ue1oe1_p1_g2_b(5) <= not( ex5_ue1oe1_p1_g(5) ) ;
+    ex5_ue1oe1_p1_g2_b(4) <= not( ex5_ue1oe1_p1_g(4) or (ex5_ue1oe1_p1_t(4)  and ex5_ue1oe1_p1_g(5) )  );
+
+    ex5_ue1oe1_p1_t2_b(5) <= not(                                                ex5_ue1oe1_p1_t(5) )   ;
+    ex5_ue1oe1_p1_t2_b(4) <= not(                       (ex5_ue1oe1_p1_t(4)  and ex5_ue1oe1_p1_t(5) )  );
+
+    ex5_ue1oe1_p1_c(7) <= not( ex5_ue1oe1_p1_g2_b(7) );
+    ex5_ue1oe1_p1_c(6) <= not( ex5_ue1oe1_p1_g2_b(6) );
+    ex5_ue1oe1_p1_c(5) <= not( ex5_ue1oe1_p1_g2_b(5) and (ex5_ue1oe1_p1_t2_b(5)  or  ex5_ue1oe1_p1_g2_b(6) ) );
+    ex5_ue1oe1_p1_c(4) <= not( ex5_ue1oe1_p1_g2_b(4) and (ex5_ue1oe1_p1_t2_b(4)  or  ex5_ue1oe1_p1_g2_b(6) ) );
+
+
+
+
+    act_si  (0 to 4)        <= act_so        (1 to 4)  & f_eov_si ;
+    ex4_iexp_si  (0 to 15)  <= ex4_iexp_so   (1 to 15) & act_so  (0);
+    ex5_ovctl_si  (0 to 2)  <= ex5_ovctl_so  (1 to 2)  & ex4_iexp_so  (0);
+    ex5_misc_si   (0 to 12) <= ex5_misc_so   (1 to 12) & ex5_ovctl_so  (0);
+    ex5_urnd0_si  (0 to 12) <= ex5_urnd0_so  (1 to 12) & ex5_misc_so   (0);
+    ex5_urnd1_si  (0 to 12) <= ex5_urnd1_so  (1 to 12) & ex5_urnd0_so  (0);
+    f_eov_so                <= ex5_urnd1_so  (0);
+
+end; 
+  
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_add11.vhdl

@@ -0,0 +1,159 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+
+library ieee; 
+  use ieee.std_logic_1164.all ; 
+library ibm; 
+
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; 
+use support.power_logic_pkg.all;
+library tri; use tri.tri_latches_pkg.all;
+
+entity fuq_gst_add11 is
+  port(
+     a_b   :in  std_ulogic_vector(0 to 10);
+     b_b   :in  std_ulogic_vector(0 to 10);
+     s0    :out std_ulogic_vector(0 to 10)  
+
+ );
+
+
+
+
+end fuq_gst_add11;
+
+architecture fuq_gst_add11 of fuq_gst_add11 is
+
+  signal p1      :std_ulogic_vector(0 to 10);
+  signal g1      :std_ulogic_vector(1 to 10);
+  signal t1      :std_ulogic_vector(1 to  9);
+  signal g2_b    :std_ulogic_vector(1 to 10);
+  signal g4      :std_ulogic_vector(1 to 10);
+  signal g8_b    :std_ulogic_vector(1 to 10);
+  signal c16     :std_ulogic_vector(1 to 10);
+  signal t2_b    :std_ulogic_vector(1 to 8);
+  signal t4      :std_ulogic_vector(1 to 6);
+  signal t8_b    :std_ulogic_vector(1 to 2);
+
+
+
+
+
+
+begin
+
+
+u_p1:  p1(0 to 10) <=    ( a_b(0 to 10) xor b_b(0 to 10) );
+u_g1:  g1(1 to 10) <= not( a_b(1 to 10) or  b_b(1 to 10) );
+u_t1:  t1(1 to  9) <= not( a_b(1 to  9) and b_b(1 to  9) );
+
+
+ u_g2_01: g2_b(1)  <= not( g1(1)  or ( t1(1) and g1(2)  ) );
+ u_g2_02: g2_b(2)  <= not( g1(2)  or ( t1(2) and g1(3)  ) );
+ u_g2_03: g2_b(3)  <= not( g1(3)  or ( t1(3) and g1(4)  ) );
+ u_g2_04: g2_b(4)  <= not( g1(4)  or ( t1(4) and g1(5)  ) );
+ u_g2_05: g2_b(5)  <= not( g1(5)  or ( t1(5) and g1(6)  ) );
+ u_g2_06: g2_b(6)  <= not( g1(6)  or ( t1(6) and g1(7)  ) );
+ u_g2_07: g2_b(7)  <= not( g1(7)  or ( t1(7) and g1(8)  ) );
+ u_g2_08: g2_b(8)  <= not( g1(8)  or ( t1(8) and g1(9)  ) );
+ u_g2_09: g2_b(9)  <= not( g1(9)  or ( t1(9) and g1(10) ) ); 
+ u_g2_10: g2_b(10) <= not( g1(10) ); 
+
+ u_t2_01: t2_b(1)  <= not(             t1(1) and t1(2)    );
+ u_t2_02: t2_b(2)  <= not(             t1(2) and t1(3)    );
+ u_t2_03: t2_b(3)  <= not(             t1(3) and t1(4)    );
+ u_t2_04: t2_b(4)  <= not(             t1(4) and t1(5)    );
+ u_t2_05: t2_b(5)  <= not(             t1(5) and t1(6)    );
+ u_t2_06: t2_b(6)  <= not(             t1(6) and t1(7)    );
+ u_t2_07: t2_b(7)  <= not(             t1(7) and t1(8)    );
+ u_t2_08: t2_b(8)  <= not(             t1(8) and t1(9)    );
+
+
+
+ u_g4_01: g4(1)  <= not( g2_b(1)  and ( t2_b(1) or g2_b(3)  ) );
+ u_g4_02: g4(2)  <= not( g2_b(2)  and ( t2_b(2) or g2_b(4)  ) );
+ u_g4_03: g4(3)  <= not( g2_b(3)  and ( t2_b(3) or g2_b(5)  ) );
+ u_g4_04: g4(4)  <= not( g2_b(4)  and ( t2_b(4) or g2_b(6)  ) );
+ u_g4_05: g4(5)  <= not( g2_b(5)  and ( t2_b(5) or g2_b(7)  ) );
+ u_g4_06: g4(6)  <= not( g2_b(6)  and ( t2_b(6) or g2_b(8)  ) );
+ u_g4_07: g4(7)  <= not( g2_b(7)  and ( t2_b(7) or g2_b(9)  ) );
+ u_g4_08: g4(8)  <= not( g2_b(8)  and ( t2_b(8) or g2_b(10) ) );
+ u_g4_09: g4(9)  <= not( g2_b(9)  );
+ u_g4_10: g4(10) <= not( g2_b(10) );
+
+ u_t4_01: t4(1)  <= not(                t2_b(1) or t2_b(3)    );
+ u_t4_02: t4(2)  <= not(                t2_b(2) or t2_b(4)    );
+ u_t4_03: t4(3)  <= not(                t2_b(3) or t2_b(5)    );
+ u_t4_04: t4(4)  <= not(                t2_b(4) or t2_b(6)    );
+ u_t4_05: t4(5)  <= not(                t2_b(5) or t2_b(7)    );
+ u_t4_06: t4(6)  <= not(                t2_b(6) or t2_b(8)    );
+
+
+
+ u_g8_01: g8_b(1)  <= not( g4(1)  or  ( t4(1) and  g4(5)  ) );
+ u_g8_02: g8_b(2)  <= not( g4(2)  or  ( t4(2) and  g4(6)  ) );
+ u_g8_03: g8_b(3)  <= not( g4(3)  or  ( t4(3) and  g4(7)  ) );
+ u_g8_04: g8_b(4)  <= not( g4(4)  or  ( t4(4) and  g4(8)  ) );
+ u_g8_05: g8_b(5)  <= not( g4(5)  or  ( t4(5) and  g4(9)  ) );
+ u_g8_06: g8_b(6)  <= not( g4(6)  or  ( t4(6) and  g4(10) ) );
+ u_g8_07: g8_b(7)  <= not( g4(7)  );
+ u_g8_08: g8_b(8)  <= not( g4(8)  );
+ u_g8_09: g8_b(9)  <= not( g4(9)  );
+ u_g8_10: g8_b(10) <= not( g4(10) );
+
+ u_t8_01: t8_b(1)  <= not(              t4(1) and  t4(5)    );
+ u_t8_02: t8_b(2)  <= not(              t4(2) and  t4(6)    );
+          
+ u_c16_01: c16(1)  <= not( g8_b(1)  and ( t8_b(1) or  g8_b(9)  ) );
+ u_c16_02: c16(2)  <= not( g8_b(2)  and ( t8_b(2) or  g8_b(10) ) );
+ u_c16_03: c16(3)  <= not( g8_b(3)  );
+ u_c16_04: c16(4)  <= not( g8_b(4)  );
+ u_c16_05: c16(5)  <= not( g8_b(5)  );
+ u_c16_06: c16(6)  <= not( g8_b(6)  );
+ u_c16_07: c16(7)  <= not( g8_b(7)  );
+ u_c16_08: c16(8)  <= not( g8_b(8)  );
+ u_c16_09: c16(9)  <= not( g8_b(9)  );
+ u_c16_10: c16(10) <= not( g8_b(10) );
+          
+
+
+
+ s0(0 to 9) <= p1(0 to 9) xor c16(1 to 10);
+ s0(10)     <= p1(10) ;
+
+    
+end fuq_gst_add11     ;
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_inc19.vhdl

@@ -0,0 +1,178 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+
+library ieee; 
+  use ieee.std_logic_1164.all ; 
+library ibm; 
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; 
+use support.power_logic_pkg.all;
+
+library tri; use tri.tri_latches_pkg.all;
+
+
+entity fuq_gst_inc19 is
+  port(
+     a   :in  std_ulogic_vector(1 to 19);
+
+     o   :out std_ulogic_vector(1 to 19)   
+
+ );
+
+
+
+
+end fuq_gst_inc19;
+
+architecture fuq_gst_inc19 of fuq_gst_inc19 is
+
+ signal a_sum                       :std_ulogic_vector(01 to 19);  
+ signal a_cout_b                    :std_ulogic_vector(02 to 19);  
+ signal g2_b, g4, g8_b, g16         :std_ulogic_vector(02 to 19);
+
+ 
+
+begin
+
+
+
+g2_b(19) <= not( a(19)           );
+g2_b(18) <= not( a(18) and a(19) );
+g2_b(17) <= not( a(17) and a(18) );
+g2_b(16) <= not( a(16) and a(17) );
+g2_b(15) <= not( a(15) and a(16) );
+g2_b(14) <= not( a(14) and a(15) );
+g2_b(13) <= not( a(13) and a(14) );
+g2_b(12) <= not( a(12) and a(13) );
+g2_b(11) <= not( a(11) and a(12) );
+g2_b(10) <= not( a(10) and a(11) );
+g2_b( 9) <= not( a( 9) and a(10) );
+g2_b( 8) <= not( a( 8) and a( 9) );
+g2_b( 7) <= not( a( 7) and a( 8) );
+g2_b( 6) <= not( a( 6) and a( 7) );
+g2_b( 5) <= not( a( 5) and a( 6) );
+g2_b( 4) <= not( a( 4) and a( 5) );
+g2_b( 3) <= not( a( 3) and a( 4) );
+g2_b( 2) <= not( a( 2) and a( 3) );
+
+
+g4(19) <= not( g2_b(19) ) ;
+g4(18) <= not( g2_b(18) ) ;
+g4(17) <= not( g2_b(17) or g2_b(19) ) ;
+g4(16) <= not( g2_b(16) or g2_b(18) ) ;
+g4(15) <= not( g2_b(15) or g2_b(17) ) ;
+g4(14) <= not( g2_b(14) or g2_b(16) ) ;
+g4(13) <= not( g2_b(13) or g2_b(15) ) ;
+g4(12) <= not( g2_b(12) or g2_b(14) ) ;
+g4(11) <= not( g2_b(11) or g2_b(13) ) ;
+g4(10) <= not( g2_b(10) or g2_b(12) ) ;
+g4( 9) <= not( g2_b( 9) or g2_b(11) ) ;
+g4( 8) <= not( g2_b( 8) or g2_b(10) ) ;
+g4( 7) <= not( g2_b( 7) or g2_b( 9) ) ;
+g4( 6) <= not( g2_b( 6) or g2_b( 8) ) ;
+g4( 5) <= not( g2_b( 5) or g2_b( 7) ) ;
+g4( 4) <= not( g2_b( 4) or g2_b( 6) ) ;
+g4( 3) <= not( g2_b( 3) or g2_b( 5) ) ;
+g4( 2) <= not( g2_b( 2) or g2_b( 4) ) ;
+
+
+g8_b(19) <=  not( g4(19) ) ;
+g8_b(18) <=  not( g4(18) ) ;
+g8_b(17) <=  not( g4(17) ) ;
+g8_b(16) <=  not( g4(16) ) ;
+g8_b(15) <=  not( g4(15) and g4(19) ) ;
+g8_b(14) <=  not( g4(14) and g4(18) ) ;
+g8_b(13) <=  not( g4(13) and g4(17) ) ;
+g8_b(12) <=  not( g4(12) and g4(16) ) ;
+g8_b(11) <=  not( g4(11) and g4(15) ) ;
+g8_b(10) <=  not( g4(10) and g4(14) ) ;
+g8_b( 9) <=  not( g4( 9) and g4(13) ) ;
+g8_b( 8) <=  not( g4( 8) and g4(12) ) ;
+g8_b( 7) <=  not( g4( 7) and g4(11) ) ;
+g8_b( 6) <=  not( g4( 6) and g4(10) ) ;
+g8_b( 5) <=  not( g4( 5) and g4( 9) ) ;
+g8_b( 4) <=  not( g4( 4) and g4( 8) ) ;
+g8_b( 3) <=  not( g4( 3) and g4( 7) ) ;
+g8_b( 2) <=  not( g4( 2) and g4( 6) ) ;
+
+g16(19) <= not( g8_b(19) );
+g16(18) <= not( g8_b(18) );
+g16(17) <= not( g8_b(17) );
+g16(16) <= not( g8_b(16) );
+g16(15) <= not( g8_b(15) );
+g16(14) <= not( g8_b(14) );
+g16(13) <= not( g8_b(13) );
+g16(12) <= not( g8_b(12) );
+g16(11) <= not( g8_b(11) or g8_b(19) ) ;
+g16(10) <= not( g8_b(10) or g8_b(18) ) ;
+g16( 9) <= not( g8_b( 9) or g8_b(17) ) ;
+g16( 8) <= not( g8_b( 8) or g8_b(16) ) ;
+g16( 7) <= not( g8_b( 7) or g8_b(15) ) ;
+g16( 6) <= not( g8_b( 6) or g8_b(14) ) ;
+g16( 5) <= not( g8_b( 5) or g8_b(13) ) ;
+g16( 4) <= not( g8_b( 4) or g8_b(12) ) ;
+g16( 3) <= not( g8_b( 3) or g8_b(11) ) ;
+g16( 2) <= not( g8_b( 2) or g8_b(10) ) ;
+
+a_cout_b(19) <= not( g16(19) );
+a_cout_b(18) <= not( g16(18) );
+a_cout_b(17) <= not( g16(17) );
+a_cout_b(16) <= not( g16(16) );
+a_cout_b(15) <= not( g16(15) );
+a_cout_b(14) <= not( g16(14) );
+a_cout_b(13) <= not( g16(13) );
+a_cout_b(12) <= not( g16(12) );
+a_cout_b(11) <= not( g16(11) );
+a_cout_b(10) <= not( g16(10) );
+a_cout_b( 9) <= not( g16( 9) );
+a_cout_b( 8) <= not( g16( 8) );
+a_cout_b( 7) <= not( g16( 7) );
+a_cout_b( 6) <= not( g16( 6) );
+a_cout_b( 5) <= not( g16( 5) );
+a_cout_b( 4) <= not( g16( 4) );
+a_cout_b( 3) <= not( g16( 3) and g16(19) );
+a_cout_b( 2) <= not( g16( 2) and g16(18) );
+              
+
+
+a_sum(1 to 18) <= a(1 to 18);
+a_sum(19) <= not a(19);
+
+
+o(01 to 18) <= not( a_sum(01 to 18) xor a_cout_b(02 to 19) ); 
+o(19)       <= a_sum(19);                                     
+
+
+end fuq_gst_inc19; 
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_gst_loa.vhdl

@@ -0,0 +1,153 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+
+library ieee; 
+  use ieee.std_logic_1164.all ; 
+library ibm; 
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+library support; 
+use support.power_logic_pkg.all;
+
+library tri; use tri.tri_latches_pkg.all;
+
+
+entity fuq_gst_loa is
+  port(
+     a   :in  std_ulogic_vector(1 to 19);
+
+     shamt   :out std_ulogic_vector(0 to 4)   
+
+ );
+
+
+  
+end fuq_gst_loa;
+
+architecture fuq_gst_loa of fuq_gst_loa is
+
+   signal unused :std_ulogic;
+
+begin
+
+   unused <= a(19) ;
+
+
+
+
+
+
+shamt(0) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+		 and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13)
+		 and not a(14) and not a(15) and  a(19)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14)
+	 and not a(15) and  a(18)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14)
+	 and not a(15) and  a(17)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14)
+	 and not a(15) and  a(16));
+
+shamt(1) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(15)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(14)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(13)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(12)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(11)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(10)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(09)) or
+	(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
+	 and  a(08));
+
+shamt(2) <= (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
+	 and  a(15)) or
+	(not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
+	 and  a(14)) or
+	(not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
+	 and  a(13)) or
+	(not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
+	 and  a(12)) or
+	(not a(01) and not a(02) and not a(03) and  a(07)) or
+	(not a(01) and not a(02) and not a(03) and  a(06)) or
+	(not a(01) and not a(02) and not a(03) and  a(05)) or
+	(not a(01) and not a(02) and not a(03) and  a(04));
+
+shamt(3) <= (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
+	 and not a(16) and not a(17) and  a(19)) or
+	(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
+	 and not a(16) and not a(17) and  a(18)) or
+	(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
+	 and  a(15)) or
+	(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
+	 and  a(14)) or
+	(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and  a(11)) or
+	(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and  a(10)) or
+	(not a(01) and not a(04) and not a(05) and  a(07)) or
+	(not a(01) and not a(04) and not a(05) and  a(06)) or
+	(not a(01) and  a(03)) or
+	(not a(01) and  a(02));
+
+shamt(4) <= (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14)
+	 and not a(16) and not a(18) and  a(19)) or
+	(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14)
+	 and not a(16) and  a(17)) or
+	(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14)
+	 and  a(15)) or
+	(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and  a(13)) or
+	(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and  a(11)) or
+	(not a(02) and not a(04) and not a(06) and not a(08) and  a(09)) or
+	(not a(02) and not a(04) and not a(06) and  a(07)) or
+	(not a(02) and not a(04) and  a(05)) or
+	(not a(02) and  a(03)) or
+	( a(01));
+
+
+
+
+
+
+
+
+
+
+
+end fuq_gst_loa; 
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp.vhdl

@@ -0,0 +1,482 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+
+library ieee; use ieee.std_logic_1164.all ; 
+
+library ibm;
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+
+ENTITY fuq_hc16pp IS  PORT(
+     x           : IN  std_ulogic_vector(0 to 15);
+     y           : IN  std_ulogic_vector(0 to 15);
+     ci0         : IN  std_ulogic;
+     ci0_b       : IN  std_ulogic;
+     ci1         : IN  std_ulogic;
+     ci1_b       : IN  std_ulogic;
+     s0          : OUT std_ulogic_vector(0 to 15);
+     s1          : OUT std_ulogic_vector(0 to 15);
+     g16         : out std_ulogic;
+     t16         : out std_ulogic
+);
+
+
+
+END                                 fuq_hc16pp;
+
+ARCHITECTURE fuq_hc16pp OF fuq_hc16pp IS
+
+   signal g01_b, t01_b, p01_b, p01 :std_ulogic_vector(0 to 15);
+   signal g01od,   t01od      :std_ulogic_vector(0 to 7);
+   signal g02ev  , t02ev      :std_ulogic_vector(0 to 7);
+   signal g02ev_b , t02ev_b   :std_ulogic_vector(1 to 7);
+   signal g04ev,    t04ev     :std_ulogic_vector(1 to 7);
+   signal g08ev_b, t08ev_b    :std_ulogic_vector(1 to 7);
+   signal g16ev, t16ev        :std_ulogic_vector(1 to 7);
+   signal c0_b  ,    c1_b     :std_ulogic_vector(1 to 15);
+   signal s0_raw, s1_raw      :std_ulogic_vector(0 to 15);
+   signal s0_x_b, s0_y_b      :std_ulogic_vector(0 to 15);
+   signal s1_x_b, s1_y_b      :std_ulogic_vector(0 to 15);
+
+   signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic;
+   signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic;
+   signal glb_g08_e03  , glb_g08_e47  , glb_t08_e03  , glb_t08_e47   :std_ulogic;
+   signal glb_g16_e07_b, glb_t16_e07_b                               :std_ulogic;
+
+
+
+
+
+
+
+
+
+
+
+BEGIN
+
+
+  hc00_g01: g01_b( 0) <= not( x( 0) and y( 0) ); 
+  hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); 
+  hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); 
+  hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); 
+  hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); 
+  hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); 
+  hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); 
+  hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); 
+  hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); 
+  hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); 
+  hc10_g01: g01_b(10) <= not( x(10) and y(10) ); 
+  hc11_g01: g01_b(11) <= not( x(11) and y(11) ); 
+  hc12_g01: g01_b(12) <= not( x(12) and y(12) ); 
+  hc13_g01: g01_b(13) <= not( x(13) and y(13) ); 
+  hc14_g01: g01_b(14) <= not( x(14) and y(14) ); 
+  hc15_g01: g01_b(15) <= not( x(15) and y(15) ); 
+
+  hc00_t01: t01_b( 0) <= not( x( 0) or  y( 0) ); 
+  hc01_t01: t01_b( 1) <= not( x( 1) or  y( 1) ); 
+  hc02_t01: t01_b( 2) <= not( x( 2) or  y( 2) ); 
+  hc03_t01: t01_b( 3) <= not( x( 3) or  y( 3) ); 
+  hc04_t01: t01_b( 4) <= not( x( 4) or  y( 4) ); 
+  hc05_t01: t01_b( 5) <= not( x( 5) or  y( 5) ); 
+  hc06_t01: t01_b( 6) <= not( x( 6) or  y( 6) ); 
+  hc07_t01: t01_b( 7) <= not( x( 7) or  y( 7) ); 
+  hc08_t01: t01_b( 8) <= not( x( 8) or  y( 8) ); 
+  hc09_t01: t01_b( 9) <= not( x( 9) or  y( 9) ); 
+  hc10_t01: t01_b(10) <= not( x(10) or  y(10) ); 
+  hc11_t01: t01_b(11) <= not( x(11) or  y(11) ); 
+  hc12_t01: t01_b(12) <= not( x(12) or  y(12) ); 
+  hc13_t01: t01_b(13) <= not( x(13) or  y(13) ); 
+  hc14_t01: t01_b(14) <= not( x(14) or  y(14) ); 
+  hc15_t01: t01_b(15) <= not( x(15) or  y(15) ); 
+
+  hc00_p01: p01( 0) <=    ( x( 0) xor y( 0) ); 
+  hc01_p01: p01( 1) <=    ( x( 1) xor y( 1) ); 
+  hc02_p01: p01( 2) <=    ( x( 2) xor y( 2) ); 
+  hc03_p01: p01( 3) <=    ( x( 3) xor y( 3) ); 
+  hc04_p01: p01( 4) <=    ( x( 4) xor y( 4) ); 
+  hc05_p01: p01( 5) <=    ( x( 5) xor y( 5) ); 
+  hc06_p01: p01( 6) <=    ( x( 6) xor y( 6) ); 
+  hc07_p01: p01( 7) <=    ( x( 7) xor y( 7) ); 
+  hc08_p01: p01( 8) <=    ( x( 8) xor y( 8) ); 
+  hc09_p01: p01( 9) <=    ( x( 9) xor y( 9) ); 
+  hc10_p01: p01(10) <=    ( x(10) xor y(10) ); 
+  hc11_p01: p01(11) <=    ( x(11) xor y(11) ); 
+  hc12_p01: p01(12) <=    ( x(12) xor y(12) ); 
+  hc13_p01: p01(13) <=    ( x(13) xor y(13) ); 
+  hc14_p01: p01(14) <=    ( x(14) xor y(14) ); 
+  hc15_p01: p01(15) <=    ( x(15) xor y(15) ); 
+
+  hc00_p01b: p01_b( 0) <= not( p01( 0) ); 
+  hc01_p01b: p01_b( 1) <= not( p01( 1) ); 
+  hc02_p01b: p01_b( 2) <= not( p01( 2) ); 
+  hc03_p01b: p01_b( 3) <= not( p01( 3) ); 
+  hc04_p01b: p01_b( 4) <= not( p01( 4) ); 
+  hc05_p01b: p01_b( 5) <= not( p01( 5) ); 
+  hc06_p01b: p01_b( 6) <= not( p01( 6) ); 
+  hc07_p01b: p01_b( 7) <= not( p01( 7) ); 
+  hc08_p01b: p01_b( 8) <= not( p01( 8) ); 
+  hc09_p01b: p01_b( 9) <= not( p01( 9) ); 
+  hc10_p01b: p01_b(10) <= not( p01(10) ); 
+  hc11_p01b: p01_b(11) <= not( p01(11) ); 
+  hc12_p01b: p01_b(12) <= not( p01(12) ); 
+  hc13_p01b: p01_b(13) <= not( p01(13) ); 
+  hc14_p01b: p01_b(14) <= not( p01(14) ); 
+  hc15_p01b: p01_b(15) <= not( p01(15) ); 
+
+
+  hc01_g01o: g01od(0) <= not g01_b( 1);
+  hc03_g01o: g01od(1) <= not g01_b( 3);
+  hc05_g01o: g01od(2) <= not g01_b( 5);
+  hc07_g01o: g01od(3) <= not g01_b( 7);
+  hc09_g01o: g01od(4) <= not g01_b( 9);
+  hc11_g01o: g01od(5) <= not g01_b(11);
+  hc13_g01o: g01od(6) <= not g01_b(13);
+  hc15_g01o: g01od(7) <= not g01_b(15);
+
+  hc01_t01o: t01od(0) <= not t01_b( 1);
+  hc03_t01o: t01od(1) <= not t01_b( 3);
+  hc05_t01o: t01od(2) <= not t01_b( 5);
+  hc07_t01o: t01od(3) <= not t01_b( 7);
+  hc09_t01o: t01od(4) <= not t01_b( 9);
+  hc11_t01o: t01od(5) <= not t01_b(11);
+  hc13_t01o: t01od(6) <= not t01_b(13);
+  hc15_t01o: t01od(7) <= not t01_b(15);
+
+
+
+  
+
+ hc14_g02:  g02ev(7) <= not( ( t01_b(14) or g01_b(15) ) and g01_b(14) );
+ hc12_g02:  g02ev(6) <= not( ( t01_b(12) or g01_b(13) ) and g01_b(12) );
+ hc10_g02:  g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) );
+ hc08_g02:  g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) );
+ hc06_g02:  g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) );
+ hc04_g02:  g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) );
+ hc02_g02:  g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) );
+ hc00_g02:  g02ev(0) <= not( ( t01_b( 0) or g01_b( 1) ) and g01_b( 0) );
+                                                            
+ hc14_t02:  t02ev(7) <= not( ( t01_b(14) or t01_b(15) ) and g01_b(14) );
+ hc12_t02:  t02ev(6) <= not(   t01_b(12) or t01_b(13)                 );
+ hc10_t02:  t02ev(5) <= not(   t01_b(10) or t01_b(11)                 );
+ hc08_t02:  t02ev(4) <= not(   t01_b( 8) or t01_b( 9)                 );
+ hc06_t02:  t02ev(3) <= not(   t01_b( 6) or t01_b( 7)                 );
+ hc04_t02:  t02ev(2) <= not(   t01_b( 4) or t01_b( 5)                 );
+ hc02_t02:  t02ev(1) <= not(   t01_b( 2) or t01_b( 3)                 );
+ hc00_t02:  t02ev(0) <= not(   t01_b( 0) or t01_b( 1)                 );
+
+ hc14_g02b:  g02ev_b(7) <= not( g02ev(7) ); 
+ hc12_g02b:  g02ev_b(6) <= not( g02ev(6) ); 
+ hc10_g02b:  g02ev_b(5) <= not( g02ev(5) ); 
+ hc08_g02b:  g02ev_b(4) <= not( g02ev(4) ); 
+ hc06_g02b:  g02ev_b(3) <= not( g02ev(3) ); 
+ hc04_g02b:  g02ev_b(2) <= not( g02ev(2) ); 
+ hc02_g02b:  g02ev_b(1) <= not( g02ev(1) ); 
+                                                            
+ hc14_t02b:  t02ev_b(7) <= not( t02ev(7) ); 
+ hc12_t02b:  t02ev_b(6) <= not( t02ev(6) ); 
+ hc10_t02b:  t02ev_b(5) <= not( t02ev(5) ); 
+ hc08_t02b:  t02ev_b(4) <= not( t02ev(4) ); 
+ hc06_t02b:  t02ev_b(3) <= not( t02ev(3) ); 
+ hc04_t02b:  t02ev_b(2) <= not( t02ev(2) ); 
+ hc02_t02b:  t02ev_b(1) <= not( t02ev(1) ); 
+
+
+ u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0)      or  ( t02ev(0)      and g02ev(1)      ) );
+ u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2)      or  ( t02ev(2)      and g02ev(3)      ) ); 
+ u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4)      or  ( t02ev(4)      and g02ev(5)      ) ); 
+ u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6)      or  ( t02ev(6)      and g02ev(7)      ) ); 
+ u_glb_t04_e01: glb_t04_e01_b <= not(                     t02ev(0)      and t02ev(1)        );
+ u_glb_t04_e23: glb_t04_e23_b <= not(                     t02ev(2)      and t02ev(3)        ); 
+ u_glb_t04_e45: glb_t04_e45_b <= not(                     t02ev(4)      and t02ev(5)        ); 
+ u_glb_t04_e67: glb_t04_e67_b <= not( g02ev(6)      or  ( t02ev(6)      and t02ev(7)      ) ); 
+
+ u_glb_g08_e03: glb_g08_e03   <= not( glb_g04_e01_b and ( glb_t04_e01_b or  glb_g04_e23_b ) );
+ u_glb_g08_e47: glb_g08_e47   <= not( glb_g04_e45_b and ( glb_t04_e45_b or  glb_g04_e67_b ) ); 
+ u_glb_t08_e03: glb_t08_e03   <= not(                     glb_t04_e01_b or  glb_t04_e23_b   );
+ u_glb_t08_e47: glb_t08_e47   <= not( glb_g04_e45_b and ( glb_t04_e45_b or  glb_t04_e67_b ) ); 
+
+ u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03   or  ( glb_t08_e03   and glb_g08_e47   ) );
+ u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03   or  ( glb_t08_e03   and glb_t08_e47   ) );
+
+ u_g16o:        g16           <= not( glb_g16_e07_b );
+ u_t16o:        t16           <= not( glb_t16_e07_b );
+
+
+
+ hc14_g04:  g04ev(7) <= not( g02ev_b(7)                                  );
+ hc12_g04:  g04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or  g02ev_b(7))  );
+ hc10_g04:  g04ev(5) <= not( g02ev_b(5) and (t02ev_b(5) or  g02ev_b(6))  );
+ hc08_g04:  g04ev(4) <= not( g02ev_b(4) and (t02ev_b(4) or  g02ev_b(5))  );
+ hc06_g04:  g04ev(3) <= not( g02ev_b(3) and (t02ev_b(3) or  g02ev_b(4))  );
+ hc04_g04:  g04ev(2) <= not( g02ev_b(2) and (t02ev_b(2) or  g02ev_b(3))  );
+ hc02_g04:  g04ev(1) <= not( g02ev_b(1) and (t02ev_b(1) or  g02ev_b(2))  );
+
+
+ hc14_t04:  t04ev(7) <= not( t02ev_b(7)                                  );
+ hc12_t04:  t04ev(6) <= not( g02ev_b(6) and (t02ev_b(6) or  t02ev_b(7))  );
+ hc10_t04:  t04ev(5) <= not(                 t02ev_b(5) or  t02ev_b(6)   );
+ hc08_t04:  t04ev(4) <= not(                 t02ev_b(4) or  t02ev_b(5)   );
+ hc06_t04:  t04ev(3) <= not(                 t02ev_b(3) or  t02ev_b(4)   );
+ hc04_t04:  t04ev(2) <= not(                 t02ev_b(2) or  t02ev_b(3)   );
+ hc02_t04:  t04ev(1) <= not(                 t02ev_b(1) or  t02ev_b(2)   );
+
+
+
+ hc14_g08:  g08ev_b(7) <= not( g04ev(7)                             );
+ hc12_g08:  g08ev_b(6) <= not( g04ev(6)                             );
+ hc10_g08:  g08ev_b(5) <= not( g04ev(5) or  (t04ev(5) and g04ev(7)) );
+ hc08_g08:  g08ev_b(4) <= not( g04ev(4) or  (t04ev(4) and g04ev(6)) );
+ hc06_g08:  g08ev_b(3) <= not( g04ev(3) or  (t04ev(3) and g04ev(5)) );
+ hc04_g08:  g08ev_b(2) <= not( g04ev(2) or  (t04ev(2) and g04ev(4)) );
+ hc02_g08:  g08ev_b(1) <= not( g04ev(1) or  (t04ev(1) and g04ev(3)) );
+
+
+ hc14_t08:  t08ev_b(7) <= not( t04ev(7)                             );
+ hc12_t08:  t08ev_b(6) <= not( t04ev(6)                             );
+ hc10_t08:  t08ev_b(5) <= not( g04ev(5) or  (t04ev(5) and t04ev(7)) );
+ hc08_t08:  t08ev_b(4) <= not( g04ev(4) or  (t04ev(4) and t04ev(6)) );
+ hc06_t08:  t08ev_b(3) <= not(               t04ev(3) and t04ev(5)  );
+ hc04_t08:  t08ev_b(2) <= not(               t04ev(2) and t04ev(4)  );
+ hc02_t08:  t08ev_b(1) <= not(               t04ev(1) and t04ev(3)  );
+
+
+
+ hc14_g16: g16ev(7) <= not( g08ev_b(7)                                 );
+ hc12_g16: g16ev(6) <= not( g08ev_b(6)                                 );
+ hc10_g16: g16ev(5) <= not( g08ev_b(5)                                 );
+ hc08_g16: g16ev(4) <= not( g08ev_b(4)                                 );
+ hc06_g16: g16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or  g08ev_b(7)) ); 
+ hc04_g16: g16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or  g08ev_b(6)) ); 
+ hc02_g16: g16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or  g08ev_b(5)) ); 
+
+ hc14_t16: t16ev(7) <= not( t08ev_b(7)                                 );
+ hc12_t16: t16ev(6) <= not( t08ev_b(6)                                 );
+ hc10_t16: t16ev(5) <= not( t08ev_b(5)                                 );
+ hc08_t16: t16ev(4) <= not( t08ev_b(4)                                 );
+ hc06_t16: t16ev(3) <= not( g08ev_b(3) and (t08ev_b(3) or  t08ev_b(7)) ); 
+ hc04_t16: t16ev(2) <= not( g08ev_b(2) and (t08ev_b(2) or  t08ev_b(6)) ); 
+ hc02_t16: t16ev(1) <= not( g08ev_b(1) and (t08ev_b(1) or  t08ev_b(5)) ); 
+
+
+                                                     
+ hc14_c0:  c0_b(14) <= not(                g16ev(7)                 );
+ hc12_c0:  c0_b(12) <= not(                g16ev(6)                 );
+ hc10_c0:  c0_b(10) <= not(                g16ev(5)                 );
+ hc08_c0:  c0_b( 8) <= not(                g16ev(4)                 );
+ hc06_c0:  c0_b( 6) <= not(                g16ev(3)                 );
+ hc04_c0:  c0_b( 4) <= not(                g16ev(2)                 );
+ hc02_c0:  c0_b( 2) <= not(                g16ev(1)                 );
+
+ hc14_c1:  c1_b(14) <= not(                t16ev(7)                 );
+ hc12_c1:  c1_b(12) <= not(                t16ev(6)                 );
+ hc10_c1:  c1_b(10) <= not(                t16ev(5)                 );
+ hc08_c1:  c1_b( 8) <= not(                t16ev(4)                 );
+ hc06_c1:  c1_b( 6) <= not(                t16ev(3)                 );
+ hc04_c1:  c1_b( 4) <= not(                t16ev(2)                 );
+ hc02_c1:  c1_b( 2) <= not(                t16ev(1)                 );
+
+ hc15_c0:  c0_b(15) <= not(                              g01od(7));
+ hc13_c0:  c0_b(13) <= not( (t01od(6) and g16ev(7))  or  g01od(6));
+ hc11_c0:  c0_b(11) <= not( (t01od(5) and g16ev(6))  or  g01od(5));
+ hc09_c0:  c0_b( 9) <= not( (t01od(4) and g16ev(5))  or  g01od(4));
+ hc07_c0:  c0_b( 7) <= not( (t01od(3) and g16ev(4))  or  g01od(3));
+ hc05_c0:  c0_b( 5) <= not( (t01od(2) and g16ev(3))  or  g01od(2));
+ hc03_c0:  c0_b( 3) <= not( (t01od(1) and g16ev(2))  or  g01od(1));
+ hc01_c0:  c0_b( 1) <= not( (t01od(0) and g16ev(1))  or  g01od(0));
+
+ hc15_c1:  c1_b(15) <= not(  t01od(7)                            );
+ hc13_c1:  c1_b(13) <= not( (t01od(6) and t16ev(7)) or  g01od(6) );
+ hc11_c1:  c1_b(11) <= not( (t01od(5) and t16ev(6)) or  g01od(5) );
+ hc09_c1:  c1_b( 9) <= not( (t01od(4) and t16ev(5)) or  g01od(4) );
+ hc07_c1:  c1_b( 7) <= not( (t01od(3) and t16ev(4)) or  g01od(3) );
+ hc05_c1:  c1_b( 5) <= not( (t01od(2) and t16ev(3)) or  g01od(2) );
+ hc03_c1:  c1_b( 3) <= not( (t01od(1) and t16ev(2)) or  g01od(1) );
+ hc01_c1:  c1_b( 1) <= not( (t01od(0) and t16ev(1)) or  g01od(0) );
+
+
+ hc00_s0r:  s0_raw( 0) <=    ( p01_b( 0) xor c0_b( 1) );
+ hc01_s0r:  s0_raw( 1) <=    ( p01_b( 1) xor c0_b( 2) );
+ hc02_s0r:  s0_raw( 2) <=    ( p01_b( 2) xor c0_b( 3) );
+ hc03_s0r:  s0_raw( 3) <=    ( p01_b( 3) xor c0_b( 4) );
+ hc04_s0r:  s0_raw( 4) <=    ( p01_b( 4) xor c0_b( 5) );
+ hc05_s0r:  s0_raw( 5) <=    ( p01_b( 5) xor c0_b( 6) );
+ hc06_s0r:  s0_raw( 6) <=    ( p01_b( 6) xor c0_b( 7) );
+ hc07_s0r:  s0_raw( 7) <=    ( p01_b( 7) xor c0_b( 8) );
+ hc08_s0r:  s0_raw( 8) <=    ( p01_b( 8) xor c0_b( 9) );
+ hc09_s0r:  s0_raw( 9) <=    ( p01_b( 9) xor c0_b(10) );
+ hc10_s0r:  s0_raw(10) <=    ( p01_b(10) xor c0_b(11) );
+ hc11_s0r:  s0_raw(11) <=    ( p01_b(11) xor c0_b(12) );
+ hc12_s0r:  s0_raw(12) <=    ( p01_b(12) xor c0_b(13) );
+ hc13_s0r:  s0_raw(13) <=    ( p01_b(13) xor c0_b(14) );
+ hc14_s0r:  s0_raw(14) <=    ( p01_b(14) xor c0_b(15) );
+ hc15_s0r:  s0_raw(15) <= not  p01_b(15);
+
+ hc00_s1r:  s1_raw( 0) <=    ( p01_b( 0) xor c1_b( 1) );
+ hc01_s1r:  s1_raw( 1) <=    ( p01_b( 1) xor c1_b( 2) );
+ hc02_s1r:  s1_raw( 2) <=    ( p01_b( 2) xor c1_b( 3) );
+ hc03_s1r:  s1_raw( 3) <=    ( p01_b( 3) xor c1_b( 4) );
+ hc04_s1r:  s1_raw( 4) <=    ( p01_b( 4) xor c1_b( 5) );
+ hc05_s1r:  s1_raw( 5) <=    ( p01_b( 5) xor c1_b( 6) );
+ hc06_s1r:  s1_raw( 6) <=    ( p01_b( 6) xor c1_b( 7) );
+ hc07_s1r:  s1_raw( 7) <=    ( p01_b( 7) xor c1_b( 8) );
+ hc08_s1r:  s1_raw( 8) <=    ( p01_b( 8) xor c1_b( 9) );
+ hc09_s1r:  s1_raw( 9) <=    ( p01_b( 9) xor c1_b(10) );
+ hc10_s1r:  s1_raw(10) <=    ( p01_b(10) xor c1_b(11) );
+ hc11_s1r:  s1_raw(11) <=    ( p01_b(11) xor c1_b(12) );
+ hc12_s1r:  s1_raw(12) <=    ( p01_b(12) xor c1_b(13) );
+ hc13_s1r:  s1_raw(13) <=    ( p01_b(13) xor c1_b(14) );
+ hc14_s1r:  s1_raw(14) <=    ( p01_b(14) xor c1_b(15) );
+ hc15_s1r:  s1_raw(15) <= not  s0_raw(15);
+
+
+
+ 
+ hc00_s0x:  s0_x_b( 0) <= not( s0_raw( 0) and ci0_b      );
+ hc00_s0y:  s0_y_b( 0) <= not( s1_raw( 0) and ci0        );
+ hc00_s1x:  s1_x_b( 0) <= not( s0_raw( 0) and ci1_b      );
+ hc00_s1y:  s1_y_b( 0) <= not( s1_raw( 0) and ci1        );
+ hc00_s0:   s0    ( 0) <= not( s0_x_b( 0) and s0_y_b( 0) );
+ hc00_s1:   s1    ( 0) <= not( s1_x_b( 0) and s1_y_b( 0) );
+
+ hc01_s0x:  s0_x_b( 1) <= not( s0_raw( 1) and ci0_b      );
+ hc01_s0y:  s0_y_b( 1) <= not( s1_raw( 1) and ci0        );
+ hc01_s1x:  s1_x_b( 1) <= not( s0_raw( 1) and ci1_b      );
+ hc01_s1y:  s1_y_b( 1) <= not( s1_raw( 1) and ci1        );
+ hc01_s0:   s0    ( 1) <= not( s0_x_b( 1) and s0_y_b( 1) );
+ hc01_s1:   s1    ( 1) <= not( s1_x_b( 1) and s1_y_b( 1) );
+
+ hc02_s0x:  s0_x_b( 2) <= not( s0_raw( 2) and ci0_b      );
+ hc02_s0y:  s0_y_b( 2) <= not( s1_raw( 2) and ci0        );
+ hc02_s1x:  s1_x_b( 2) <= not( s0_raw( 2) and ci1_b      );
+ hc02_s1y:  s1_y_b( 2) <= not( s1_raw( 2) and ci1        );
+ hc02_s0:   s0    ( 2) <= not( s0_x_b( 2) and s0_y_b( 2) );
+ hc02_s1:   s1    ( 2) <= not( s1_x_b( 2) and s1_y_b( 2) );
+
+ hc03_s0x:  s0_x_b( 3) <= not( s0_raw( 3) and ci0_b      );
+ hc03_s0y:  s0_y_b( 3) <= not( s1_raw( 3) and ci0        );
+ hc03_s1x:  s1_x_b( 3) <= not( s0_raw( 3) and ci1_b      );
+ hc03_s1y:  s1_y_b( 3) <= not( s1_raw( 3) and ci1        );
+ hc03_s0:   s0    ( 3) <= not( s0_x_b( 3) and s0_y_b( 3) );
+ hc03_s1:   s1    ( 3) <= not( s1_x_b( 3) and s1_y_b( 3) );
+
+ hc04_s0x:  s0_x_b( 4) <= not( s0_raw( 4) and ci0_b      );
+ hc04_s0y:  s0_y_b( 4) <= not( s1_raw( 4) and ci0        );
+ hc04_s1x:  s1_x_b( 4) <= not( s0_raw( 4) and ci1_b      );
+ hc04_s1y:  s1_y_b( 4) <= not( s1_raw( 4) and ci1        );
+ hc04_s0:   s0    ( 4) <= not( s0_x_b( 4) and s0_y_b( 4) );
+ hc04_s1:   s1    ( 4) <= not( s1_x_b( 4) and s1_y_b( 4) );
+
+ hc05_s0x:  s0_x_b( 5) <= not( s0_raw( 5) and ci0_b      );
+ hc05_s0y:  s0_y_b( 5) <= not( s1_raw( 5) and ci0        );
+ hc05_s1x:  s1_x_b( 5) <= not( s0_raw( 5) and ci1_b      );
+ hc05_s1y:  s1_y_b( 5) <= not( s1_raw( 5) and ci1        );
+ hc05_s0:   s0    ( 5) <= not( s0_x_b( 5) and s0_y_b( 5) );
+ hc05_s1:   s1    ( 5) <= not( s1_x_b( 5) and s1_y_b( 5) );
+
+ hc06_s0x:  s0_x_b( 6) <= not( s0_raw( 6) and ci0_b      );
+ hc06_s0y:  s0_y_b( 6) <= not( s1_raw( 6) and ci0        );
+ hc06_s1x:  s1_x_b( 6) <= not( s0_raw( 6) and ci1_b      );
+ hc06_s1y:  s1_y_b( 6) <= not( s1_raw( 6) and ci1        );
+ hc06_s0:   s0    ( 6) <= not( s0_x_b( 6) and s0_y_b( 6) );
+ hc06_s1:   s1    ( 6) <= not( s1_x_b( 6) and s1_y_b( 6) );
+
+ hc07_s0x:  s0_x_b( 7) <= not( s0_raw( 7) and ci0_b      );
+ hc07_s0y:  s0_y_b( 7) <= not( s1_raw( 7) and ci0        );
+ hc07_s1x:  s1_x_b( 7) <= not( s0_raw( 7) and ci1_b      );
+ hc07_s1y:  s1_y_b( 7) <= not( s1_raw( 7) and ci1        );
+ hc07_s0:   s0    ( 7) <= not( s0_x_b( 7) and s0_y_b( 7) );
+ hc07_s1:   s1    ( 7) <= not( s1_x_b( 7) and s1_y_b( 7) );
+
+ hc08_s0x:  s0_x_b( 8) <= not( s0_raw( 8) and ci0_b      );
+ hc08_s0y:  s0_y_b( 8) <= not( s1_raw( 8) and ci0        );
+ hc08_s1x:  s1_x_b( 8) <= not( s0_raw( 8) and ci1_b      );
+ hc08_s1y:  s1_y_b( 8) <= not( s1_raw( 8) and ci1        );
+ hc08_s0:   s0    ( 8) <= not( s0_x_b( 8) and s0_y_b( 8) );
+ hc08_s1:   s1    ( 8) <= not( s1_x_b( 8) and s1_y_b( 8) );
+
+ hc09_s0x:  s0_x_b( 9) <= not( s0_raw( 9) and ci0_b      );
+ hc09_s0y:  s0_y_b( 9) <= not( s1_raw( 9) and ci0        );
+ hc09_s1x:  s1_x_b( 9) <= not( s0_raw( 9) and ci1_b      );
+ hc09_s1y:  s1_y_b( 9) <= not( s1_raw( 9) and ci1        );
+ hc09_s0:   s0    ( 9) <= not( s0_x_b( 9) and s0_y_b( 9) );
+ hc09_s1:   s1    ( 9) <= not( s1_x_b( 9) and s1_y_b( 9) );
+
+ hc10_s0x:  s0_x_b(10) <= not( s0_raw(10) and ci0_b      );
+ hc10_s0y:  s0_y_b(10) <= not( s1_raw(10) and ci0        );
+ hc10_s1x:  s1_x_b(10) <= not( s0_raw(10) and ci1_b      );
+ hc10_s1y:  s1_y_b(10) <= not( s1_raw(10) and ci1        );
+ hc10_s0:   s0    (10) <= not( s0_x_b(10) and s0_y_b(10) );
+ hc10_s1:   s1    (10) <= not( s1_x_b(10) and s1_y_b(10) );
+
+ hc11_s0x:  s0_x_b(11) <= not( s0_raw(11) and ci0_b      );
+ hc11_s0y:  s0_y_b(11) <= not( s1_raw(11) and ci0        );
+ hc11_s1x:  s1_x_b(11) <= not( s0_raw(11) and ci1_b      );
+ hc11_s1y:  s1_y_b(11) <= not( s1_raw(11) and ci1        );
+ hc11_s0:   s0    (11) <= not( s0_x_b(11) and s0_y_b(11) );
+ hc11_s1:   s1    (11) <= not( s1_x_b(11) and s1_y_b(11) );
+
+ hc12_s0x:  s0_x_b(12) <= not( s0_raw(12) and ci0_b      );
+ hc12_s0y:  s0_y_b(12) <= not( s1_raw(12) and ci0        );
+ hc12_s1x:  s1_x_b(12) <= not( s0_raw(12) and ci1_b      );
+ hc12_s1y:  s1_y_b(12) <= not( s1_raw(12) and ci1        );
+ hc12_s0:   s0    (12) <= not( s0_x_b(12) and s0_y_b(12) );
+ hc12_s1:   s1    (12) <= not( s1_x_b(12) and s1_y_b(12) );
+
+ hc13_s0x:  s0_x_b(13) <= not( s0_raw(13) and ci0_b      );
+ hc13_s0y:  s0_y_b(13) <= not( s1_raw(13) and ci0        );
+ hc13_s1x:  s1_x_b(13) <= not( s0_raw(13) and ci1_b      );
+ hc13_s1y:  s1_y_b(13) <= not( s1_raw(13) and ci1        );
+ hc13_s0:   s0    (13) <= not( s0_x_b(13) and s0_y_b(13) );
+ hc13_s1:   s1    (13) <= not( s1_x_b(13) and s1_y_b(13) );
+
+ hc14_s0x:  s0_x_b(14) <= not( s0_raw(14) and ci0_b      );
+ hc14_s0y:  s0_y_b(14) <= not( s1_raw(14) and ci0        );
+ hc14_s1x:  s1_x_b(14) <= not( s0_raw(14) and ci1_b      );
+ hc14_s1y:  s1_y_b(14) <= not( s1_raw(14) and ci1        );
+ hc14_s0:   s0    (14) <= not( s0_x_b(14) and s0_y_b(14) );
+ hc14_s1:   s1    (14) <= not( s1_x_b(14) and s1_y_b(14) );
+
+ hc15_s0x:  s0_x_b(15) <= not( s0_raw(15) and ci0_b      );
+ hc15_s0y:  s0_y_b(15) <= not( s1_raw(15) and ci0        );
+ hc15_s1x:  s1_x_b(15) <= not( s0_raw(15) and ci1_b      );
+ hc15_s1y:  s1_y_b(15) <= not( s1_raw(15) and ci1        );
+ hc15_s0:   s0    (15) <= not( s0_x_b(15) and s0_y_b(15) );
+ hc15_s1:   s1    (15) <= not( s1_x_b(15) and s1_y_b(15) );
+
+
+END; 
+
+
+
+
+

rel/build/ip_user/a2x_axi/a2x_axi/src/work/fuq_hc16pp_lsb.vhdl

@@ -0,0 +1,325 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+library ieee; use ieee.std_logic_1164.all ; 
+library ibm; 
+library support; 
+  use ibm.std_ulogic_support.all; 
+  use ibm.std_ulogic_function_support.all; 
+  use ibm.std_ulogic_ao_support.all; 
+  use ibm.std_ulogic_mux_support.all; 
+
+ENTITY fuq_hc16pp_lsb IS  PORT(
+     x           : IN  std_ulogic_vector(0 to 13);
+     y           : IN  std_ulogic_vector(0 to 12);
+     s0          : OUT std_ulogic_vector(0 to 13);
+     s1          : OUT std_ulogic_vector(0 to 13);
+     g16         : out std_ulogic;
+     t16         : out std_ulogic
+);
+
+
+END                                 fuq_hc16pp_lsb;
+
+ARCHITECTURE fuq_hc16pp_lsb OF fuq_hc16pp_lsb IS
+
+  constant tiup : std_ulogic := '1';
+  constant tidn : std_ulogic := '0';
+
+
+   signal g01_b :std_ulogic_vector(0 to 12);
+   signal t01_b, p01_b, p01 :std_ulogic_vector(0 to 13);
+
+   signal  g01od    :std_ulogic_vector(0 to 5);
+   signal  t01od    :std_ulogic_vector(0 to 6);
+
+
+   signal g02ev  , t02ev      :std_ulogic_vector(0 to 6);
+   signal g02ev_b, t02ev_b    :std_ulogic_vector(1 to 6);
+   signal g04ev  , t04ev      :std_ulogic_vector(1 to 6);
+   signal g08ev_b, t08ev_b    :std_ulogic_vector(1 to 6);
+   signal g16ev  , t16ev      :std_ulogic_vector(1 to 6);
+   signal c0_b                :std_ulogic_vector(1 to 12);
+   signal c1_b                :std_ulogic_vector(1 to 13);
+
+   signal glb_g04_e01_b, glb_g04_e23_b, glb_g04_e45_b, glb_g04_e67_b :std_ulogic;
+   signal glb_t04_e01_b, glb_t04_e23_b, glb_t04_e45_b, glb_t04_e67_b :std_ulogic;
+   signal glb_g08_e03  , glb_g08_e47  , glb_t08_e03  , glb_t08_e47   :std_ulogic;
+   signal glb_g16_e07_b, glb_t16_e07_b                               :std_ulogic;
+
+
+
+ 
+BEGIN
+
+
+  hc00_g01: g01_b( 0) <= not( x( 0) and y( 0) ); 
+  hc01_g01: g01_b( 1) <= not( x( 1) and y( 1) ); 
+  hc02_g01: g01_b( 2) <= not( x( 2) and y( 2) ); 
+  hc03_g01: g01_b( 3) <= not( x( 3) and y( 3) ); 
+  hc04_g01: g01_b( 4) <= not( x( 4) and y( 4) ); 
+  hc05_g01: g01_b( 5) <= not( x( 5) and y( 5) ); 
+  hc06_g01: g01_b( 6) <= not( x( 6) and y( 6) ); 
+  hc07_g01: g01_b( 7) <= not( x( 7) and y( 7) ); 
+  hc08_g01: g01_b( 8) <= not( x( 8) and y( 8) ); 
+  hc09_g01: g01_b( 9) <= not( x( 9) and y( 9) ); 
+  hc10_g01: g01_b(10) <= not( x(10) and y(10) ); 
+  hc11_g01: g01_b(11) <= not( x(11) and y(11) ); 
+  hc12_g01: g01_b(12) <= not( x(12) and y(12) ); 
+
+  hc00_t01: t01_b( 0) <= not( x( 0) or  y( 0) ); 
+  hc01_t01: t01_b( 1) <= not( x( 1) or  y( 1) ); 
+  hc02_t01: t01_b( 2) <= not( x( 2) or  y( 2) ); 
+  hc03_t01: t01_b( 3) <= not( x( 3) or  y( 3) ); 
+  hc04_t01: t01_b( 4) <= not( x( 4) or  y( 4) ); 
+  hc05_t01: t01_b( 5) <= not( x( 5) or  y( 5) ); 
+  hc06_t01: t01_b( 6) <= not( x( 6) or  y( 6) ); 
+  hc07_t01: t01_b( 7) <= not( x( 7) or  y( 7) ); 
+  hc08_t01: t01_b( 8) <= not( x( 8) or  y( 8) ); 
+  hc09_t01: t01_b( 9) <= not( x( 9) or  y( 9) ); 
+  hc10_t01: t01_b(10) <= not( x(10) or  y(10) ); 
+  hc11_t01: t01_b(11) <= not( x(11) or  y(11) ); 
+  hc12_t01: t01_b(12) <= not( x(12) or  y(12) ); 
+  hc13_t01: t01_b(13) <= not( x(13)           ); 
+
+  hc00_p01: p01( 0) <=    ( x( 0) xor y( 0) ); 
+  hc01_p01: p01( 1) <=    ( x( 1) xor y( 1) ); 
+  hc02_p01: p01( 2) <=    ( x( 2) xor y( 2) ); 
+  hc03_p01: p01( 3) <=    ( x( 3) xor y( 3) ); 
+  hc04_p01: p01( 4) <=    ( x( 4) xor y( 4) ); 
+  hc05_p01: p01( 5) <=    ( x( 5) xor y( 5) ); 
+  hc06_p01: p01( 6) <=    ( x( 6) xor y( 6) ); 
+  hc07_p01: p01( 7) <=    ( x( 7) xor y( 7) ); 
+  hc08_p01: p01( 8) <=    ( x( 8) xor y( 8) ); 
+  hc09_p01: p01( 9) <=    ( x( 9) xor y( 9) ); 
+  hc10_p01: p01(10) <=    ( x(10) xor y(10) ); 
+  hc11_p01: p01(11) <=    ( x(11) xor y(11) ); 
+  hc12_p01: p01(12) <=    ( x(12) xor y(12) ); 
+  hc13_p01: p01(13) <= not p01_b(13) ;
+
+  hc00_p01b: p01_b( 0) <= not( p01( 0) ); 
+  hc01_p01b: p01_b( 1) <= not( p01( 1) ); 
+  hc02_p01b: p01_b( 2) <= not( p01( 2) ); 
+  hc03_p01b: p01_b( 3) <= not( p01( 3) ); 
+  hc04_p01b: p01_b( 4) <= not( p01( 4) ); 
+  hc05_p01b: p01_b( 5) <= not( p01( 5) ); 
+  hc06_p01b: p01_b( 6) <= not( p01( 6) ); 
+  hc07_p01b: p01_b( 7) <= not( p01( 7) ); 
+  hc08_p01b: p01_b( 8) <= not( p01( 8) ); 
+  hc09_p01b: p01_b( 9) <= not( p01( 9) ); 
+  hc10_p01b: p01_b(10) <= not( p01(10) ); 
+  hc11_p01b: p01_b(11) <= not( p01(11) ); 
+  hc12_p01b: p01_b(12) <= not( p01(12) ); 
+  hc13_p01b: p01_b(13) <= not( x(13)           ); 
+
+  hc01_g01o: g01od(0) <= not g01_b( 1);
+  hc03_g01o: g01od(1) <= not g01_b( 3);
+  hc05_g01o: g01od(2) <= not g01_b( 5);
+  hc07_g01o: g01od(3) <= not g01_b( 7);
+  hc09_g01o: g01od(4) <= not g01_b( 9);
+  hc11_g01o: g01od(5) <= not g01_b(11);
+ 
+  hc01_t01o: t01od(0) <= not t01_b( 1);
+  hc03_t01o: t01od(1) <= not t01_b( 3);
+  hc05_t01o: t01od(2) <= not t01_b( 5);
+  hc07_t01o: t01od(3) <= not t01_b( 7);
+  hc09_t01o: t01od(4) <= not t01_b( 9);
+  hc11_t01o: t01od(5) <= not t01_b(11);
+  hc13_t01o: t01od(6) <= not t01_b(13);
+
+  
+
+  hc12_g02: g02ev(6) <= not(                                g01_b(12) );
+  hc10_g02: g02ev(5) <= not( ( t01_b(10) or g01_b(11) ) and g01_b(10) );
+  hc08_g02: g02ev(4) <= not( ( t01_b( 8) or g01_b( 9) ) and g01_b( 8) );
+  hc06_g02: g02ev(3) <= not( ( t01_b( 6) or g01_b( 7) ) and g01_b( 6) );
+  hc04_g02: g02ev(2) <= not( ( t01_b( 4) or g01_b( 5) ) and g01_b( 4) );
+  hc02_g02: g02ev(1) <= not( ( t01_b( 2) or g01_b( 3) ) and g01_b( 2) );
+  hc00_g02: g02ev(0) <= not( ( t01_b( 0) or g01_b( 1) ) and g01_b( 0) );
+
+  hc12_t02: t02ev(6) <= not( ( t01_b(12) or t01_b(13) ) and g01_b(12) );
+  hc10_t02: t02ev(5) <= not( ( t01_b(10) or t01_b(11) )               );
+  hc08_t02: t02ev(4) <= not( ( t01_b( 8) or t01_b( 9) )               );
+  hc06_t02: t02ev(3) <= not( ( t01_b( 6) or t01_b( 7) )               );
+  hc04_t02: t02ev(2) <= not( ( t01_b( 4) or t01_b( 5) )               );
+  hc02_t02: t02ev(1) <= not( ( t01_b( 2) or t01_b( 3) )               );
+  hc00_t02: t02ev(0) <= not( ( t01_b( 0) or t01_b( 1) )               );
+
+ hc12_g02b:  g02ev_b(6) <= not( g02ev(6) ); 
+ hc10_g02b:  g02ev_b(5) <= not( g02ev(5) ); 
+ hc08_g02b:  g02ev_b(4) <= not( g02ev(4) ); 
+ hc06_g02b:  g02ev_b(3) <= not( g02ev(3) ); 
+ hc04_g02b:  g02ev_b(2) <= not( g02ev(2) ); 
+ hc02_g02b:  g02ev_b(1) <= not( g02ev(1) ); 
+                                                            
+ hc12_t02b:  t02ev_b(6) <= not( t02ev(6) ); 
+ hc10_t02b:  t02ev_b(5) <= not( t02ev(5) ); 
+ hc08_t02b:  t02ev_b(4) <= not( t02ev(4) ); 
+ hc06_t02b:  t02ev_b(3) <= not( t02ev(3) ); 
+ hc04_t02b:  t02ev_b(2) <= not( t02ev(2) ); 
+ hc02_t02b:  t02ev_b(1) <= not( t02ev(1) ); 
+
+
+ u_glb_g04_e01: glb_g04_e01_b <= not( g02ev(0)      or  ( t02ev(0)      and g02ev(1)      ) );
+ u_glb_g04_e23: glb_g04_e23_b <= not( g02ev(2)      or  ( t02ev(2)      and g02ev(3)      ) ); 
+ u_glb_g04_e45: glb_g04_e45_b <= not( g02ev(4)      or  ( t02ev(4)      and g02ev(5)      ) ); 
+ u_glb_g04_e67: glb_g04_e67_b <= not( g02ev(6)                                              ); 
+ u_glb_t04_e01: glb_t04_e01_b <= not(                     t02ev(0)      and t02ev(1)        );
+ u_glb_t04_e23: glb_t04_e23_b <= not(                     t02ev(2)      and t02ev(3)        ); 
+ u_glb_t04_e45: glb_t04_e45_b <= not(                     t02ev(4)      and t02ev(5)        ); 
+ u_glb_t04_e67: glb_t04_e67_b <= not(                     t02ev(6)                          ); 
+
+ u_glb_g08_e03: glb_g08_e03   <= not( glb_g04_e01_b and ( glb_t04_e01_b or  glb_g04_e23_b ) );
+ u_glb_g08_e47: glb_g08_e47   <= not( glb_g04_e45_b and ( glb_t04_e45_b or  glb_g04_e67_b ) ); 
+ u_glb_t08_e03: glb_t08_e03   <= not(                     glb_t04_e01_b or  glb_t04_e23_b   );
+ u_glb_t08_e47: glb_t08_e47   <= not( glb_g04_e45_b and ( glb_t04_e45_b or  glb_t04_e67_b ) ); 
+
+ u_glb_g16_e07: glb_g16_e07_b <= not( glb_g08_e03   or  ( glb_t08_e03   and glb_g08_e47   ) );
+ u_glb_t16_e07: glb_t16_e07_b <= not( glb_g08_e03   or  ( glb_t08_e03   and glb_t08_e47   ) );
+
+ u_g16o:        g16           <= not( glb_g16_e07_b );
+ u_t16o:        t16           <= not( glb_t16_e07_b );
+
+
+  hc12_g04: g04ev  (6) <= not(                                 g02ev_b(6)  );
+  hc10_g04: g04ev  (5) <= not( (t02ev_b(5) or  g02ev_b(6)) and g02ev_b(5)  );
+  hc08_g04: g04ev  (4) <= not( (t02ev_b(4) or  g02ev_b(5)) and g02ev_b(4)  );
+  hc06_g04: g04ev  (3) <= not( (t02ev_b(3) or  g02ev_b(4)) and g02ev_b(3)  );
+  hc04_g04: g04ev  (2) <= not( (t02ev_b(2) or  g02ev_b(3)) and g02ev_b(2)  );
+  hc02_g04: g04ev  (1) <= not( (t02ev_b(1) or  g02ev_b(2)) and g02ev_b(1)  );
+
+                                                          
+  hc12_t04: t04ev  (6) <= not(  t02ev_b(6)                                 );
+  hc10_t04: t04ev  (5) <= not( (t02ev_b(5) or  t02ev_b(6)) and g02ev_b(5)  );
+  hc08_t04: t04ev  (4) <= not(  t02ev_b(4) or  t02ev_b(5)                  );
+  hc06_t04: t04ev  (3) <= not(  t02ev_b(3) or  t02ev_b(4)                  );
+  hc04_t04: t04ev  (2) <= not(  t02ev_b(2) or  t02ev_b(3)                  );
+  hc02_t04: t04ev  (1) <= not(  t02ev_b(1) or  t02ev_b(2)                  );
+
+
+
+  hc12_g08: g08ev_b(6) <= not( g04ev  (6)                                 );
+  hc10_g08: g08ev_b(5) <= not( g04ev  (5)                                 );
+  hc08_g08: g08ev_b(4) <= not( g04ev  (4) or  (t04ev  (4) and g04ev  (6)) );
+  hc06_g08: g08ev_b(3) <= not( g04ev  (3) or  (t04ev  (3) and g04ev  (5)) );
+  hc04_g08: g08ev_b(2) <= not( g04ev  (2) or  (t04ev  (2) and g04ev  (4)) );
+  hc02_g08: g08ev_b(1) <= not( g04ev  (1) or  (t04ev  (1) and g04ev  (3)) );
+
+
+  hc12_t08: t08ev_b(6) <= not( t04ev  (6)                                 );
+  hc10_t08: t08ev_b(5) <= not( t04ev  (5)                                 );
+  hc08_t08: t08ev_b(4) <= not( g04ev  (4) or  (t04ev  (4) and t04ev  (6)) );
+  hc06_t08: t08ev_b(3) <= not( g04ev  (3) or  (t04ev  (3) and t04ev  (5)) );
+  hc04_t08: t08ev_b(2) <= not(                 t04ev  (2) and t04ev  (4)  );
+  hc02_t08: t08ev_b(1) <= not(                 t04ev  (1) and t04ev  (3)  );
+
+
+
+  hc12_g16: g16ev  (6) <= not(                                 g08ev_b(6) );
+  hc10_g16: g16ev  (5) <= not(                                 g08ev_b(5) );
+  hc08_g16: g16ev  (4) <= not(                                 g08ev_b(4) );
+  hc06_g16: g16ev  (3) <= not(                                 g08ev_b(3) ); 
+  hc04_g16: g16ev  (2) <= not( (t08ev_b(2) or  g08ev_b(6)) and g08ev_b(2) ); 
+  hc02_g16: g16ev  (1) <= not( (t08ev_b(1) or  g08ev_b(5)) and g08ev_b(1) ); 
+
+                                                          
+  hc12_t16: t16ev  (6) <= not(                                 t08ev_b(6) );
+  hc10_t16: t16ev  (5) <= not(                                 t08ev_b(5) );
+  hc08_t16: t16ev  (4) <= not(                                 t08ev_b(4) );
+  hc06_t16: t16ev  (3) <= not(                                 t08ev_b(3) );
+  hc04_t16: t16ev  (2) <= not( (t08ev_b(2) or  t08ev_b(6)) and g08ev_b(2) ); 
+  hc02_t16: t16ev  (1) <= not( (t08ev_b(1) or  t08ev_b(5)) and g08ev_b(1) ); 
+
+
+
+  hc12_c0: c0_b(12) <= not(                g16ev  (6)                 );
+  hc10_c0: c0_b(10) <= not(                g16ev  (5)                 );
+  hc08_c0: c0_b( 8) <= not(                g16ev  (4)                 );
+  hc06_c0: c0_b( 6) <= not(                g16ev  (3)                 );
+  hc04_c0: c0_b( 4) <= not(                g16ev  (2)                 );
+  hc02_c0: c0_b( 2) <= not(                g16ev  (1)                 );
+                                                     
+  hc12_c1: c1_b(12) <= not(                t16ev  (6)                 );
+  hc10_c1: c1_b(10) <= not(                t16ev  (5)                 );
+  hc08_c1: c1_b( 8) <= not(                t16ev  (4)                 );
+  hc06_c1: c1_b( 6) <= not(                t16ev  (3)                 );
+  hc04_c1: c1_b( 4) <= not(                t16ev  (2)                 );
+  hc02_c1: c1_b( 2) <= not(                t16ev  (1)                 );
+
+  hc11_c0: c0_b(11) <= not( (t01od(5) and g16ev  (6))  or  g01od(5));
+  hc09_c0: c0_b( 9) <= not( (t01od(4) and g16ev  (5))  or  g01od(4));
+  hc07_c0: c0_b( 7) <= not( (t01od(3) and g16ev  (4))  or  g01od(3));
+  hc05_c0: c0_b( 5) <= not( (t01od(2) and g16ev  (3))  or  g01od(2));
+  hc03_c0: c0_b( 3) <= not( (t01od(1) and g16ev  (2))  or  g01od(1));
+  hc01_c0: c0_b( 1) <= not( (t01od(0) and g16ev  (1))  or  g01od(0));
+                                                          
+  hc13_c1: c1_b(13) <= not(                                t01od(6));
+  hc11_c1: c1_b(11) <= not( (t01od(5) and t16ev  (6))  or  g01od(5));
+  hc09_c1: c1_b( 9) <= not( (t01od(4) and t16ev  (5))  or  g01od(4));
+  hc07_c1: c1_b( 7) <= not( (t01od(3) and t16ev  (4))  or  g01od(3));
+  hc05_c1: c1_b( 5) <= not( (t01od(2) and t16ev  (3))  or  g01od(2));
+  hc03_c1: c1_b( 3) <= not( (t01od(1) and t16ev  (2))  or  g01od(1));
+  hc01_c1: c1_b( 1) <= not( (t01od(0) and t16ev  (1))  or  g01od(0));
+
+
+  hc00_s0: s0( 0) <=    ( p01_b( 0) xor c0_b( 1) );
+  hc01_s0: s0( 1) <=    ( p01_b( 1) xor c0_b( 2) );
+  hc02_s0: s0( 2) <=    ( p01_b( 2) xor c0_b( 3) );
+  hc03_s0: s0( 3) <=    ( p01_b( 3) xor c0_b( 4) );
+  hc04_s0: s0( 4) <=    ( p01_b( 4) xor c0_b( 5) );
+  hc05_s0: s0( 5) <=    ( p01_b( 5) xor c0_b( 6) );
+  hc06_s0: s0( 6) <=    ( p01_b( 6) xor c0_b( 7) );
+  hc07_s0: s0( 7) <=    ( p01_b( 7) xor c0_b( 8) );
+  hc08_s0: s0( 8) <=    ( p01_b( 8) xor c0_b( 9) );
+  hc09_s0: s0( 9) <=    ( p01_b( 9) xor c0_b(10) );
+  hc10_s0: s0(10) <=    ( p01_b(10) xor c0_b(11) );
+  hc11_s0: s0(11) <=    ( p01_b(11) xor c0_b(12) );
+  hc12_s0: s0(12) <= not( p01_b(12)            );
+  hc13_s0: s0(13) <= not( p01_b(13)            );
+
+  hc00_s1: s1( 0) <=    ( p01_b( 0) xor c1_b( 1) );
+  hc01_s1: s1( 1) <=    ( p01_b( 1) xor c1_b( 2) );
+  hc02_s1: s1( 2) <=    ( p01_b( 2) xor c1_b( 3) );
+  hc03_s1: s1( 3) <=    ( p01_b( 3) xor c1_b( 4) );
+  hc04_s1: s1( 4) <=    ( p01_b( 4) xor c1_b( 5) );
+  hc05_s1: s1( 5) <=    ( p01_b( 5) xor c1_b( 6) );
+  hc06_s1: s1( 6) <=    ( p01_b( 6) xor c1_b( 7) );
+  hc07_s1: s1( 7) <=    ( p01_b( 7) xor c1_b( 8) );
+  hc08_s1: s1( 8) <=    ( p01_b( 8) xor c1_b( 9) );
+  hc09_s1: s1( 9) <=    ( p01_b( 9) xor c1_b(10) );
+  hc10_s1: s1(10) <=    ( p01_b(10) xor c1_b(11) );
+  hc11_s1: s1(11) <=    ( p01_b(11) xor c1_b(12) );
+  hc12_s1: s1(12) <=    ( p01_b(12) xor c1_b(13) );
+  hc13_s1: s1(13) <= not( p01(13)              );
+
+
+END; 
+
+
+