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83 lines
3.6 KiB
VHDL
83 lines
3.6 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity xuq_spr_dvccmp is
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generic(
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regsize : integer := 64);
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port(
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en : in std_ulogic;
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en00 : in std_ulogic := '1';
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cmp : in std_ulogic_vector(8-regsize/8 to 7);
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dvcm : in std_ulogic_vector(0 to 1);
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dvcbe : in std_ulogic_vector(8-regsize/8 to 7);
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dvc_cmpr : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_spr_dvccmp;
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architecture xuq_spr_dvccmp of xuq_spr_dvccmp is
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signal cmp_mask_or,cmp_mask_and : std_ulogic_vector(8-regsize/8 to 7);
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signal cmp_and,cmp_or,cmp_andor : std_ulogic;
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begin
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cmp_mask_or <= gate((cmp or not dvcbe),or_reduce(dvcbe));
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cmp_mask_and <= (cmp and dvcbe);
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cmp_and <= and_reduce(cmp_mask_or);
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cmp_or <= or_reduce(cmp_mask_and);
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cmp_andor_gen32 : if regsize = 32 generate
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cmp_andor <= (and_reduce(cmp_mask_or(4 to 5)) and or_reduce(dvcbe(4 to 5))) or
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(and_reduce(cmp_mask_or(6 to 7)) and or_reduce(dvcbe(6 to 7)));
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end generate;
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cmp_andor_gen64 : if regsize = 64 generate
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cmp_andor <= (and_reduce(cmp_mask_or(0 to 1)) and or_reduce(dvcbe(0 to 1))) or
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(and_reduce(cmp_mask_or(2 to 3)) and or_reduce(dvcbe(2 to 3))) or
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(and_reduce(cmp_mask_or(4 to 5)) and or_reduce(dvcbe(4 to 5))) or
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(and_reduce(cmp_mask_or(6 to 7)) and or_reduce(dvcbe(6 to 7)));
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end generate;
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with dvcm(0 to 1) select
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dvc_cmpr <= en and en00 when "00",
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en and cmp_and when "01",
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en and cmp_or when "10",
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en and cmp_andor when others;
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end architecture xuq_spr_dvccmp;
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