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438 lines
13 KiB
VHDL
438 lines
13 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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LIBRARY ieee; USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY ibm;
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USE ibm.std_ulogic_support.all;
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USE ibm.std_ulogic_unsigned.all;
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USE ibm.std_ulogic_function_support.all;
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LIBRARY support;
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USE support.power_logic_pkg.all;
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LIBRARY tri; USE tri.tri_latches_pkg.all;
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LIBRARY clib;
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entity xuq_alu_mult_boothrow is
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port(
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s_neg : in std_ulogic;
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s_x : in std_ulogic;
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s_x2 : in std_ulogic;
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sign_bit_adj : in std_ulogic;
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x : in std_ulogic_vector(0 to 31);
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q : out std_ulogic_vector(0 to 32);
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hot_one : out std_ulogic;
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_alu_mult_boothrow;
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architecture xuq_alu_mult_boothrow of xuq_alu_mult_boothrow is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal left : std_ulogic_vector(1 to 32);
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begin
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u00: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => sign_bit_adj,
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RIGHT => left(1),
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LEFT => open,
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Q => q(0));
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u01: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(0),
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RIGHT => left(2),
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LEFT => left(1),
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Q => q(1));
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u02: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(1),
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RIGHT => left(3),
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LEFT => left(2),
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Q => q(2));
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u03: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(2),
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RIGHT => left(4),
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LEFT => left(3),
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Q => q(3));
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u04: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(3),
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RIGHT => left(5),
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LEFT => left(4),
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Q => q(4));
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u05: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(4),
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RIGHT => left(6),
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LEFT => left(5),
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Q => q(5));
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u06: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(5),
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RIGHT => left(7),
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LEFT => left(6),
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Q => q(6));
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u07: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(6),
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RIGHT => left(8),
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LEFT => left(7),
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Q => q(7));
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u08: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(7),
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RIGHT => left(9),
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LEFT => left(8),
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Q => q(8));
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u09: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(8),
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RIGHT => left(10),
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LEFT => left(9),
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Q => q(9));
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u10: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(9),
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RIGHT => left(11),
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LEFT => left(10),
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Q => q(10));
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u11: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(10),
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RIGHT => left(12),
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LEFT => left(11),
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Q => q(11));
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u12: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(11),
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RIGHT => left(13),
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LEFT => left(12),
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Q => q(12));
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u13: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(12),
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RIGHT => left(14),
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LEFT => left(13),
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Q => q(13));
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u14: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(13),
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RIGHT => left(15),
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LEFT => left(14),
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Q => q(14));
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u15: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(14),
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RIGHT => left(16),
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LEFT => left(15),
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Q => q(15));
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u16: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(15),
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RIGHT => left(17),
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LEFT => left(16),
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Q => q(16));
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u17: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(16),
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RIGHT => left(18),
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LEFT => left(17),
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Q => q(17));
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u18: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(17),
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RIGHT => left(19),
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LEFT => left(18),
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Q => q(18));
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u19: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(18),
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RIGHT => left(20),
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LEFT => left(19),
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Q => q(19));
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u20: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(19),
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RIGHT => left(21),
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LEFT => left(20),
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Q => q(20));
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u21: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(20),
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RIGHT => left(22),
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LEFT => left(21),
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Q => q(21));
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u22: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(21),
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RIGHT => left(23),
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LEFT => left(22),
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Q => q(22));
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u23: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(22),
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RIGHT => left(24),
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LEFT => left(23),
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Q => q(23));
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u24: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(23),
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RIGHT => left(25),
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LEFT => left(24),
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Q => q(24));
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u25: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(24),
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RIGHT => left(26),
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LEFT => left(25),
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Q => q(25));
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u26: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(25),
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RIGHT => left(27),
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LEFT => left(26),
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Q => q(26));
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u27: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(26),
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RIGHT => left(28),
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LEFT => left(27),
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Q => q(27));
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u28: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(27),
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RIGHT => left(29),
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LEFT => left(28),
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Q => q(28));
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u29: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(28),
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RIGHT => left(30),
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LEFT => left(29),
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Q => q(29));
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u30: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
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SX2 => s_x2,
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X => x(29),
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RIGHT => left(31),
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LEFT => left(30),
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Q => q(30));
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u31: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
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vd => vdd,
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gd => gnd,
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sneg => s_neg,
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SX => s_x,
|
||
|
SX2 => s_x2,
|
||
|
X => x(30),
|
||
|
RIGHT => left(32),
|
||
|
LEFT => left(31),
|
||
|
Q => q(31));
|
||
|
|
||
|
u32: entity clib.c_prism_bthmx generic map( btr => "BTHMX_X1_A12TH" ) port map(
|
||
|
vd => vdd,
|
||
|
gd => gnd,
|
||
|
sneg => s_neg,
|
||
|
SX => s_x,
|
||
|
SX2 => s_x2,
|
||
|
X => x(31),
|
||
|
RIGHT => s_neg,
|
||
|
LEFT => left(32),
|
||
|
Q => q(32));
|
||
|
|
||
|
|
||
|
u33: hot_one <= s_neg and (s_x or s_x2) ;
|
||
|
end;
|
||
|
|