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297 lines
12 KiB
VHDL
297 lines
12 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri, work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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library clib ;
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entity xuq_agen_cmp is port(
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x_b :in std_ulogic_vector(53 to 63) ;
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y_b :in std_ulogic_vector(53 to 63) ;
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z :in std_ulogic_vector(53 to 57) ;
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inv1_val_b :in std_ulogic;
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ex1_cache_acc_b :in std_ulogic;
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dir_ig_57_b :in std_ulogic;
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rel3_val :in std_ulogic;
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way :in std_ulogic_vector(0 to 7);
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ary_write_act_01 :out std_ulogic ;
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ary_write_act_23 :out std_ulogic ;
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ary_write_act_45 :out std_ulogic ;
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ary_write_act_67 :out std_ulogic ;
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ary_write_act :out std_ulogic_vector(0 to 3);
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match_oth :out std_ulogic ;
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vdd :inout power_logic;
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gnd :inout power_logic
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);
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END xuq_agen_cmp;
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ARCHITECTURE xuq_agen_cmp OF xuq_agen_cmp IS
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal unused_car :std_ulogic;
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signal sum :std_ulogic_vector(0 to 4);
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signal car :std_ulogic_vector(0 to 3);
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signal x :std_ulogic_vector(0 to 4);
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signal y :std_ulogic_vector(0 to 4);
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signal z_b :std_ulogic_vector(0 to 4);
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signal g1 :std_ulogic_vector(4 to 10);
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signal t1 :std_ulogic_vector(4 to 9);
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signal g_4_b :std_ulogic;
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signal g_4e :std_ulogic;
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signal t_4e_b :std_ulogic;
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signal t_4e :std_ulogic;
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signal g_5t7_0_b :std_ulogic;
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signal g_5t7_1_b :std_ulogic;
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signal g_5t7_2_b :std_ulogic;
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signal g_5t7 :std_ulogic;
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signal t_5t7_b :std_ulogic;
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signal t_5t7 :std_ulogic;
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signal g_8t10_0_b :std_ulogic;
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signal g_8t10_1_b :std_ulogic;
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signal g_8t10_2_b :std_ulogic;
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signal g_8t10 :std_ulogic;
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signal g_4t10_0_b :std_ulogic;
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signal g_4t10_1_b :std_ulogic;
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signal g_4t10_2_b :std_ulogic;
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signal g_4t10 :std_ulogic;
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signal dir_ig_57 :std_ulogic;
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signal xorcmp :std_ulogic_vector(0 to 3);
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signal ulp_0_b :std_ulogic;
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signal ulp_1_b :std_ulogic;
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signal ulp :std_ulogic;
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signal enable_part :std_ulogic;
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signal gp1_a_b :std_ulogic;
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signal gp2_a_b :std_ulogic;
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signal gp12_a :std_ulogic;
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signal gp3 :std_ulogic;
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signal match_arr_b :std_ulogic;
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signal match :std_ulogic;
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signal rel3_val_01 :std_ulogic;
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signal rel3_val_23 :std_ulogic;
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signal rel3_val_45 :std_ulogic;
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signal rel3_val_67 :std_ulogic;
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signal match_lv0_i0 :std_ulogic;
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signal match_lv1_i0_b :std_ulogic;
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signal match_lv1_i1_b :std_ulogic;
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signal ary_write_act_01_b :std_ulogic;
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signal ary_write_act_45_b :std_ulogic;
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signal ary_write_act_23_b :std_ulogic;
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signal ary_write_act_67_b :std_ulogic;
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signal ary_write_act_cpy :std_ulogic_vector(0 to 3);
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BEGIN
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dir_ig_57 <= not dir_ig_57_b ;
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u_x1_0: x(0) <= not x_b(53) ;
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u_x1_1: x(1) <= not x_b(54) ;
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u_x1_2: x(2) <= not x_b(55) ;
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u_x1_3: x(3) <= not x_b(56) ;
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u_x1_4: x(4) <= not x_b(57) ;
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u_y1_0: y(0) <= not y_b(53) ;
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u_y1_1: y(1) <= not y_b(54) ;
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u_y1_2: y(2) <= not y_b(55) ;
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u_y1_3: y(3) <= not y_b(56) ;
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u_y1_4: y(4) <= not y_b(57) ;
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u_z1_0: z_b(0) <= not( z(53) );
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u_z1_1: z_b(1) <= not( z(54) );
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u_z1_2: z_b(2) <= not( z(55) );
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u_z1_3: z_b(3) <= not( z(56) );
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u_z1_4: z_b(4) <= not( z(57) );
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u_g1_4: g1(4) <= not( x_b(57) or y_b(57) );
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u_g1_5: g1(5) <= not( x_b(58) or y_b(58) );
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u_g1_6: g1(6) <= not( x_b(59) or y_b(59) );
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u_g1_7: g1(7) <= not( x_b(60) or y_b(60) );
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u_g1_8: g1(8) <= not( x_b(61) or y_b(61) );
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u_g1_9: g1(9) <= not( x_b(62) or y_b(62) );
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u_g1_10: g1(10) <= not( x_b(63) or y_b(63) );
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u_t1_4: t1(4) <= not( x_b(57) and y_b(57) );
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u_t1_5: t1(5) <= not( x_b(58) and y_b(58) );
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u_t1_6: t1(6) <= not( x_b(59) and y_b(59) );
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u_t1_7: t1(7) <= not( x_b(60) and y_b(60) );
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u_t1_8: t1(8) <= not( x_b(61) and y_b(61) );
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u_t1_9: t1(9) <= not( x_b(62) and y_b(62) );
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u_ac_csa_0: entity clib.c_prism_csa32 port map(
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vd => vdd,
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gd => gnd,
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a => x(0) ,
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b => y(0) ,
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c => z_b(0) ,
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sum => sum(0) ,
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car => unused_car );
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u_ac_csa_1: entity clib.c_prism_csa32 port map(
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vd => vdd,
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gd => gnd,
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a => x(1) ,
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b => y(1) ,
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c => z_b(1) ,
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sum => sum(1) ,
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car => car(0) );
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u_ac_csa_2: entity clib.c_prism_csa32 port map(
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vd => vdd,
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gd => gnd,
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a => x(2) ,
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b => y(2) ,
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c => z_b(2) ,
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sum => sum(2) ,
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car => car(1) );
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u_ac_csa_3: entity clib.c_prism_csa32 port map(
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vd => vdd,
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gd => gnd,
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a => x(3) ,
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b => y(3) ,
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c => z_b(3) ,
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sum => sum(3) ,
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car => car(2) );
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u_ac_csa_4: entity clib.c_prism_csa32 port map(
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vd => vdd,
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gd => gnd,
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a => x(4) ,
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b => y(4) ,
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c => z_b(4) ,
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sum => sum(4) ,
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car => car(3) );
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u_g_4: g_4_b <= not( g1(4) );
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u_g_4e: g_4e <= not( g_4_b or dir_ig_57_b);
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u_t_4: t_4e_b <= not( t1(4) or dir_ig_57_b);
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u_t_4e: t_4e <= not( t_4e_b );
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u_g_5t7_0: g_5t7_0_b <= not( g1(5) );
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u_g_5t7_1: g_5t7_1_b <= not( t1(5) and g1(6) );
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u_g_5t7_2: g_5t7_2_b <= not( t1(5) and t1(6) and g1(7) );
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u_g_5t7: g_5t7 <= not( g_5t7_0_b and g_5t7_1_b and g_5t7_2_b );
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u_t_5t7_0: t_5t7_b <= not( t1(5) and t1(6) and t1(7) );
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u_t_5t7: t_5t7 <= not( t_5t7_b );
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u_g_8t10_0: g_8t10_0_b <= not( g1(8) );
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u_g_8t10_1: g_8t10_1_b <= not( t1(8) and g1(9) );
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u_g_8t10_2: g_8t10_2_b <= not( t1(8) and t1(9) and g1(10) );
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u_g_8t10: g_8t10 <= not( g_8t10_0_b and g_8t10_1_b and g_8t10_2_b );
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u_g_4t10_0: g_4t10_0_b <= not( g_4e ) ;
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u_g_4t10_1: g_4t10_1_b <= not( t_4e and g_5t7 ) ;
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u_g_4t10_2: g_4t10_2_b <= not( t_4e and t_5t7 and g_8t10 ) ;
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u_g_4t10: g_4t10 <= not( g_4t10_0_b and g_4t10_1_b and g_4t10_2_b );
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u_xorcmp_0: xorcmp(0) <= sum(0) xor car(0) ;
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u_xorcmp_1: xorcmp(1) <= sum(1) xor car(1) ;
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u_xorcmp_2: xorcmp(2) <= sum(2) xor car(2) ;
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u_xorcmp_3: xorcmp(3) <= sum(3) xor car(3) ;
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u_ulp_0: ulp_0_b <= not( sum(3) and dir_ig_57 );
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u_ulp_1: ulp_1_b <= not( sum(4) and dir_ig_57_b );
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u_ulp: ulp <= not( ulp_0_b and ulp_1_b );
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u_en_part: enable_part <= not( inv1_val_b and ex1_cache_acc_b );
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u_gp1_a: gp1_a_b <= not( xorcmp(0) and xorcmp(1) and xorcmp(2) );
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u_gp2_a: gp2_a_b <= not( enable_part and ( xorcmp(3) or dir_ig_57 ) );
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u_gp12_a: gp12_a <= not( gp1_a_b or gp2_a_b );
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u_gp3: gp3 <= ulp xor g_4t10 ;
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u_match_a: match_arr_b <= not( gp12_a and gp3 );
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u_match_i: match <= not( match_arr_b );
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match_oth <= match ;
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rel3_val_01 <= rel3_val and ( way(0) or way(1) );
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rel3_val_23 <= rel3_val and ( way(2) or way(3) );
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rel3_val_45 <= rel3_val and ( way(4) or way(5) );
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rel3_val_67 <= rel3_val and ( way(6) or way(7) );
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u_match_lv0_i0: match_lv0_i0 <= not( match_arr_b );
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u_match_lv1_i0: match_lv1_i0_b <= not( match_lv0_i0 );
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u_match_lv1_i1: match_lv1_i1_b <= not( match_lv0_i0 );
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u_wact_01b: ary_write_act_01_b <= not( match_lv1_i0_b and rel3_val_01 ) ;
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u_wact_45b: ary_write_act_45_b <= not( match_lv1_i0_b and rel3_val_45 ) ;
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u_wact_23b: ary_write_act_23_b <= not( match_lv1_i1_b and rel3_val_23 ) ;
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u_wact_67b: ary_write_act_67_b <= not( match_lv1_i1_b and rel3_val_67 ) ;
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u_wact_01: ary_write_act_01 <= not( ary_write_act_01_b ) ;
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u_wact_45: ary_write_act_45 <= not( ary_write_act_45_b ) ;
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u_wact_23: ary_write_act_23 <= not( ary_write_act_23_b ) ;
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u_wact_67: ary_write_act_67 <= not( ary_write_act_67_b ) ;
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u_wact: ary_write_act_cpy <= not (ary_write_act_01_b & ary_write_act_23_b & ary_write_act_45_b & ary_write_act_67_b);
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ary_write_act <= ary_write_act_cpy;
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END;
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