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335 lines
12 KiB
VHDL
335 lines
12 KiB
VHDL
3 years ago
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-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity xuq_agen is
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generic( expand_type : integer := 2 );
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port(
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x :in std_ulogic_vector(0 to 63) ;
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y :in std_ulogic_vector(0 to 63) ;
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snoop_addr :in std_ulogic_vector(0 to 51) ;
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snoop_sel :in std_ulogic ;
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binv_val :in std_ulogic ;
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mode64 :in std_ulogic ;
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dir_ig_57_b :in std_ulogic ;
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sum_non_erat :out std_ulogic_vector(0 to 63) ;
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sum :out std_ulogic_vector(0 to 51) ;
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sum_arr_dir01 :out std_ulogic_vector(53 to 57) ;
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sum_arr_dir23 :out std_ulogic_vector(53 to 57) ;
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sum_arr_dir45 :out std_ulogic_vector(53 to 57) ;
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sum_arr_dir67 :out std_ulogic_vector(53 to 57) ;
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z :in std_ulogic_vector(53 to 57) ;
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way :in std_ulogic_vector(0 to 7) ;
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inv1_val_b :in std_ulogic ;
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ex1_cache_acc_b :in std_ulogic ;
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rel3_val :in std_ulogic ;
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ary_write_act_01 :out std_ulogic ;
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ary_write_act_23 :out std_ulogic ;
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ary_write_act_45 :out std_ulogic ;
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ary_write_act_67 :out std_ulogic ;
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ary_write_act :out std_ulogic_vector(0 to 3) ;
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match_oth :out std_ulogic ;
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vdd :inout power_logic;
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gnd :inout power_logic
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);
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end xuq_agen;
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architecture xuq_agen of xuq_agen is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal sum_int, sum_non_erat_b :std_ulogic_vector(0 to 51);
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signal sum_0 :std_ulogic_vector(0 to 51);
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signal sum_1 :std_ulogic_vector(0 to 51);
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signal g08 :std_ulogic_vector(1 to 7);
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signal t08 :std_ulogic_vector(1 to 6);
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signal c64_b :std_ulogic_vector(1 to 7);
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signal x_b, y_b :std_ulogic_vector(0 to 63);
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signal addr_sel, addr_nsel, addr_sel_64, addr_nsel_64 :std_ulogic;
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signal sum_arr :std_ulogic_vector(53 to 57);
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signal sum_arr_lv1_0_b :std_ulogic_vector(53 to 57);
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signal sum_arr_lv1_1_b :std_ulogic_vector(53 to 57);
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begin
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addr_nsel_64 <= mode64 and not (snoop_sel and not binv_val) ;
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addr_nsel <= not (snoop_sel and not binv_val) ;
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addr_sel_64 <= (snoop_sel and not binv_val) ;
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addr_sel <= (snoop_sel and not binv_val) ;
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u_xi: x_b(0 to 63) <= not( x(0 to 63) );
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u_yi: y_b(0 to 63) <= not( y(0 to 63) );
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loc_0: entity work.xuq_agen_loca(xuq_agen_loca) port map(
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addr_sel => addr_sel_64 ,
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addr_nsel => addr_nsel_64 ,
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addr(0 to 7) => snoop_addr(0 to 7) ,
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x_b(0 to 7) => x_b(0 to 7) ,
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y_b(0 to 7) => y_b(0 to 7) ,
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sum_0(0 to 7) => sum_0(0 to 7) ,
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sum_1(0 to 7) => sum_1(0 to 7) );
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loc_1: entity work.xuq_agen_loca(xuq_agen_loca) port map(
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addr_sel => addr_sel_64 ,
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addr_nsel => addr_nsel_64 ,
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addr(0 to 7) => snoop_addr(8 to 15) ,
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x_b(0 to 7) => x_b(8 to 15) ,
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y_b(0 to 7) => y_b(8 to 15) ,
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sum_0(0 to 7) => sum_0(8 to 15) ,
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sum_1(0 to 7) => sum_1(8 to 15) );
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loc_2: entity work.xuq_agen_loca(xuq_agen_loca) port map(
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addr_sel => addr_sel_64 ,
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addr_nsel => addr_nsel_64 ,
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addr(0 to 7) => snoop_addr(16 to 23) ,
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x_b(0 to 7) => x_b(16 to 23) ,
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y_b(0 to 7) => y_b(16 to 23) ,
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sum_0(0 to 7) => sum_0(16 to 23) ,
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sum_1(0 to 7) => sum_1(16 to 23) );
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loc_3: entity work.xuq_agen_loca(xuq_agen_loca) port map(
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addr_sel => addr_sel_64 ,
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addr_nsel => addr_nsel_64 ,
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addr(0 to 7) => snoop_addr(24 to 31) ,
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x_b(0 to 7) => x_b(24 to 31) ,
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y_b(0 to 7) => y_b(24 to 31) ,
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sum_0(0 to 7) => sum_0(24 to 31) ,
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sum_1(0 to 7) => sum_1(24 to 31) );
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loc_4: entity work.xuq_agen_loca(xuq_agen_loca) port map(
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addr_sel => addr_sel ,
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addr_nsel => addr_nsel ,
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addr(0 to 7) => snoop_addr(32 to 39) ,
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x_b(0 to 7) => x_b(32 to 39) ,
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y_b(0 to 7) => y_b(32 to 39) ,
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sum_0(0 to 7) => sum_0(32 to 39) ,
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sum_1(0 to 7) => sum_1(32 to 39) );
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loc_5: entity work.xuq_agen_loca(xuq_agen_loca) port map(
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addr_sel => addr_sel ,
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addr_nsel => addr_nsel ,
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addr(0 to 7) => snoop_addr(40 to 47) ,
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x_b(0 to 7) => x_b(40 to 47) ,
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y_b(0 to 7) => y_b(40 to 47) ,
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sum_0(0 to 7) => sum_0(40 to 47) ,
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sum_1(0 to 7) => sum_1(40 to 47) );
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loc_6: entity work.xuq_agen_locae(xuq_agen_locae) port map(
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addr_sel => addr_sel ,
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addr_nsel => addr_nsel ,
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addr(0 to 3) => snoop_addr(48 to 51) ,
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x_b(0 to 7) => x_b(48 to 55) ,
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y_b(0 to 7) => y_b(48 to 55) ,
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sum_0(0 to 3) => sum_0(48 to 51) ,
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sum_1(0 to 3) => sum_1(48 to 51) );
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gclc_1: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map(
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x_b(0 to 7) => x_b(8 to 15) ,
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y_b(0 to 7) => y_b(8 to 15) ,
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g08 => g08(1) ,
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t08 => t08(1) );
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gclc_2: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map(
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x_b(0 to 7) => x_b(16 to 23) ,
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y_b(0 to 7) => y_b(16 to 23) ,
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g08 => g08(2) ,
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t08 => t08(2) );
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gclc_3: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map(
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x_b(0 to 7) => x_b(24 to 31) ,
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y_b(0 to 7) => y_b(24 to 31) ,
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g08 => g08(3) ,
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t08 => t08(3) );
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gclc_4: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map(
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x_b(0 to 7) => x_b(32 to 39) ,
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y_b(0 to 7) => y_b(32 to 39) ,
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g08 => g08(4) ,
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t08 => t08(4) );
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gclc_5: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map(
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x_b(0 to 7) => x_b(40 to 47) ,
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y_b(0 to 7) => y_b(40 to 47) ,
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g08 => g08(5) ,
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t08 => t08(5) );
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gclc_6: entity work.xuq_agen_glbloc(xuq_agen_glbloc) port map(
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x_b(0 to 7) => x_b(48 to 55) ,
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y_b(0 to 7) => y_b(48 to 55) ,
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g08 => g08(6) ,
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t08 => t08(6) );
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gclc_7: entity work.xuq_agen_glbloc_lsb(xuq_agen_glbloc_lsb) port map(
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x_b(0 to 7) => x_b(56 to 63) ,
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y_b(0 to 7) => y_b(56 to 63) ,
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g08 => g08(7) );
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gc: entity work.xuq_agen_glbglb(xuq_agen_glbglb) port map(
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g08(1 to 7) => g08(1 to 7) ,
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t08(1 to 6) => t08(1 to 6) ,
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c64_b(1 to 7) => c64_b(1 to 7) );
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fm_0: entity work.xuq_agen_csmux(xuq_agen_csmux) port map(
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ci_b => c64_b(1) ,
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sum_0(0 to 7) => sum_0 (0 to 7) ,
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sum_1(0 to 7) => sum_1 (0 to 7) ,
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sum (0 to 7) => sum_int (0 to 7) );
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fm_1: entity work.xuq_agen_csmux(xuq_agen_csmux) port map(
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ci_b => c64_b(2) ,
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sum_0(0 to 7) => sum_0 (8 to 15) ,
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sum_1(0 to 7) => sum_1 (8 to 15) ,
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sum (0 to 7) => sum_int (8 to 15) );
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fm_2: entity work.xuq_agen_csmux(xuq_agen_csmux) port map(
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ci_b => c64_b(3) ,
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sum_0(0 to 7) => sum_0 (16 to 23) ,
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sum_1(0 to 7) => sum_1 (16 to 23) ,
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sum (0 to 7) => sum_int (16 to 23) );
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fm_3: entity work.xuq_agen_csmux(xuq_agen_csmux) port map(
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ci_b => c64_b(4) ,
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sum_0(0 to 7) => sum_0 (24 to 31) ,
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sum_1(0 to 7) => sum_1 (24 to 31) ,
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sum (0 to 7) => sum_int (24 to 31) );
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fm_4: entity work.xuq_agen_csmux(xuq_agen_csmux) port map(
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ci_b => c64_b(5) ,
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sum_0(0 to 7) => sum_0 (32 to 39) ,
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sum_1(0 to 7) => sum_1 (32 to 39) ,
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sum (0 to 7) => sum_int (32 to 39) );
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fm_5: entity work.xuq_agen_csmux(xuq_agen_csmux) port map(
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ci_b => c64_b(6) ,
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sum_0(0 to 7) => sum_0 (40 to 47) ,
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sum_1(0 to 7) => sum_1 (40 to 47) ,
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sum (0 to 7) => sum_int (40 to 47) );
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fm_6: entity work.xuq_agen_csmuxe(xuq_agen_csmuxe) port map(
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ci_b => c64_b(7) ,
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sum_0(0 to 3) => sum_0 (48 to 51) ,
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sum_1(0 to 3) => sum_1 (48 to 51) ,
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sum (0 to 3) => sum_int (48 to 51) );
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kog: entity work.xuq_agen_lo(xuq_agen_lo) port map(
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dir_ig_57_b => dir_ig_57_b ,
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x_b (0 to 11) => x_b (52 to 63) ,
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y_b (0 to 11) => y_b (52 to 63) ,
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sum (0 to 11) => sum_non_erat(52 to 63) ,
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sum_arr(1 to 5) => sum_arr (53 to 57) );
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u_non_b: sum_non_erat_b(0 to 51) <= not( sum_int(0 to 51) );
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u_non: sum_non_erat (0 to 51) <= not( sum_non_erat_b(0 to 51) );
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sum(0 to 51) <= sum_int(0 to 51) ;
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u_sum_lv1_1: sum_arr_lv1_1_b(53 to 57) <= not( sum_arr (53 to 57) );
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u_sum_lv2_0: sum_arr_dir01(53 to 57) <= not( sum_arr_lv1_1_b(53 to 57) );
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u_sum_lv2_1: sum_arr_dir45(53 to 57) <= not( sum_arr_lv1_1_b(53 to 57) );
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u_sum_lv1_0: sum_arr_lv1_0_b(53 to 57) <= not( sum_arr (53 to 57) );
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u_sum_lv2_2: sum_arr_dir23(53 to 57) <= not( sum_arr_lv1_0_b(53 to 57) );
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u_sum_lv2_3: sum_arr_dir67(53 to 57) <= not( sum_arr_lv1_0_b(53 to 57) );
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agcmp: entity work.xuq_agen_cmp(xuq_agen_cmp) port map(
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x_b(53 to 63) => x_b(53 to 63) ,
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y_b(53 to 63) => y_b(53 to 63) ,
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z (53 to 57) => z (53 to 57) ,
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inv1_val_b => inv1_val_b ,
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ex1_cache_acc_b => ex1_cache_acc_b ,
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dir_ig_57_b => dir_ig_57_b ,
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rel3_val => rel3_val ,
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way(0 to 7) => way(0 to 7) ,
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ary_write_act_01 => ary_write_act_01 ,
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ary_write_act_23 => ary_write_act_23 ,
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ary_write_act_45 => ary_write_act_45 ,
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ary_write_act_67 => ary_write_act_67 ,
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ary_write_act => ary_write_act ,
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match_oth => match_oth ,
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vdd => vdd ,
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gnd => gnd);
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end;
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