Add meeting minutes May 12 2022

Todd Rosedahl 2 years ago
parent 7bdb464334
commit e91b95fee8

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title: Meeting Minutes 2022-05-12
date: 2022-05-12
- toddrosedahl,ibm
- toshaanbharvani,vantosh
- timansell,google
- karolgugala,antmicro
- lukeleighton,libresocproject
- daisukeoka,daisukeoka
- mohanrao,mohanrao
draft: false

# LibreBMC SIG Meeting

Meeting date: 12 May 2022
Access link:
Meeting ID: 91597478078

# Call to Order

### Anti-trust Reminder

This is a reminder that all OpenPOWER Foundation activities are subject to strict compliance with the OpenPOWER Foundations Antitrust Guidelines. Each individual participant and attendee at this meeting is responsible for knowing the contents of the Antitrust Guidelines, and for complying with the Antitrust Guidelines. Copies of the Antitrust Guidelines are available at: [Antitrust Guidelines](

### Meeting Recording

Meeting is being recorded


## Introduction

New faces so some introductions

- Luke Leighton (Libre-SOC)
- Daisuke Oka. Testing framework to port Intel Intrisics to OpenPOWER
- Link to Daisuike's talk at the OPF summit
- Mohan Rao. Analog and mixed signal Integrity

## New News

Any update?

## Hardware Update

* Lattice ECP5 version of DC-SCM
* Still missing ethernet Phys, but they do have the ECP5. Covid outbreak stopped chips.

* Xilinx Artix 7 version of DC-SCM?
* Did we end up building any hardware? **We have 10 or so**

* New hardware versions?
* Lattice Nexus line board? Lattice previously seem interested in funding this?
* Xilinx Artix Ultrascale?

## Bringup

* AntMicro has all the HW it needs to do bring-up on the AC922.
* Antmicro is going to attempt to replicate the Aussie results and then use these instructions as a start of the README
* **IBM did extend the loaner out another 60days**
* **Update on bringup progress**
* Have the DC-SCM card installed, have microwatt running
* No smoke
* Can read/write GPIOs at stand-by
* Have not yet been able to boot the system
* **Can Antmicro send a DC-SCM card to Toshaan so he can do some bringup**
* **Todd would need to send the interposer from Rochester**

## OCP DC-SCM 2.0 Working Group -- Meets bi-weekly

* **Todd** to run a call with Google and some other key players to discuss our common direction for the 3.0 standard. **Still WIP.** Trying to define the functions/areas that we need to go after. Lots of moving parts here in the industry.
* **Functions we are considering for 3.0**
* Full system design -- define the pin use cases specifically
* Define a minimum connector size exploiting LTPI for most signals
* MCU 8080. IDE bus protocol. Flexbus by Freescale. Industry Standard for 50yrs. XT/AT. ISA. PC104.
* Consider looking at that
* Asynch, interrupt driven
* How many pins?
* which can be reduced in pincount by only using 8-bit data, less IRQ, less DMA. (IDE was only 44?)
* DCM-SCM hot plug definition
* 1 to N DC-SCM to HPM
* Out-band Redfish control / In-band WIP
* Redundant Power pin definition
* Consider multiple enet connectors

## Conference Report follow ups

* Nothing new yet. Working on setting up meetings with Microsoft and ASPEED near term.

## Communication / Collaboration

* Still seem to be issues with sending iCal meeting invites.
* Seems to add to the calendar, but puts in limited information
* **Update?**
* Calendar invite :

* Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.

## Gateware


* Any progress on getting used?
* Any progress on making sure that MicroWatt works inside LiteX?
* **Todd to follow up on the progress on these**

## Simulation

* Renode looks like a good option for a simulation environment for LibreBMC.
* **Todd** to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. **WIP**
## Soft Cores

* OPF is funding an FPGA optimized POWER soft core
* Target was "VexRISCV" resource usage and performance. **Todd to schedule a readout at a future meeting**

## Toolchain


## Software


## FPGA Usage Barriers

* List of opens (potential barriers) for using FPGAs as BMCs **Update here?**
* Cost --
* Projection is that will be cost competitive
* Some things require an external chip
* video driver, but could be added later
* Soft Error Rates -- **Munir** to follow up
* Hard fails roughly the same as an ASIC
* Looks like Xilinx SER FIT is reasonable (<200).
* And detectable and fixable with an image reload
* **Lattice to provide data on FIT rates and recovery design**
* **Performance? 8X slower than an ASPEED?**
* **Information from Lattice**
* much faster to BMC to boot. 2min for ASPEED. 5sec for FGPA
* This is mostly a function of the BMC stack, the ASPEED vs FPGA, so potentially not Apples to Apples (ASPEED vs FPGA)
* **Lattice to provide some information on this performance comparisons to ASPEED**
* **Opening up of LTPI is under consideration (MIT)**
* Image size
* **Todd to schedule for next meeting AUS time**
* 85,000 latches ECP5
* New chips coming. See last week's minutes
* How to optimize image space?
* **Next meeting this time talk about microwatt so that lattice can help optimize**
* our CI results are here

## Project Ideas -- Running list of areas where we could use help

* **Near term project ideas -- things that could be worked on now**
* **Todd/Toshaan to get a page going on the OPF web page that we can point people to. Ideally something like the LibreSOC web page**
* All on Git
* Uses ikikiwiki (supports markdown, images, html)
* OPF uses HugoCMS (markdown, html, images, json)
* Have Kanban Cards or Git Issues linked?
* Documentation will need more details
* **Todd/Toshaan to get a page up and an outline for what we want to show. Look at the Libre-soc web site**

* Linux-on-Litex-VexRiscV => Linux-on-Litex-Microwatt (/cc Anton)
* There is a demo showing linux running on VexRiscV
* Replicate this demo using Microwatt
* This can be now and questions asked/answered in the open
* Ask questions on github or on IRC #litex channel on Libera
* Add emulation of LPC peripheral to Renode (/cc Piotr)
* Questions asked/answered github
* Karol/Piotr can help as well directly
* Documentation (/cc all)
* Get a working litex configuration for microwatt
* microwatt is an option in litex, but it is not complete. Need the interrupt controller working and linux booting
* Need to just try booting linux, see what breaks,and fix it
* Joel Stanley would be a contact
* Add CI so we know when litex breaks
* See FPGA CI from Antmicro
* See work from Carl Karsten <> -
* **Could point students to Carl**
* See recent work from Enjoy Digital -
* We have an ecosystem of :micropython, u-boot, linux.
* All work, but only in specific configs. Documenting and testing those configurations would be a good project.
* Could use Zephyr
* Define a boot loader for microwatt
* Make it work across configurations (arty, orangecrab)
* Add Full OpenBMC support for the AC922
* Fork the Witherspoon OpenBMC and run it -- see what breaks

* Add Full Litex FPGA support (I2C, FSI, etc) More than just bit banging:
* Tim did this in the past -->
a. PCIe -
b. I2C/I3C -
c. USB -
d. FSI (uses I3C)
e. GPIOs -
f. LPC -- We have the gateware, but need integration with Litex
g. Ethernet -
h. Refclock
j. JTAG -
k. DDR -
l. SPI -

* **Mid-term ideas -- things that need more definition**

* Include the firmware into the CI infrastructure
* Need LiteX-Hub support and integration
* Add more FPGA boards supports
* Get it running on Raspbery PI
* Linux on LiteX VexRISCV like repository
* An example for just running a POWER Linux system on as many FPGA development boards as possible?
* -- >30 boards supported...
* Repository exists -

* Improving Ethernet performance.

* **Further Project Ideas from Tim:**
* It would be great to get help with getting GHDL into conda-eda
* It would be great to get help with adding POWER support into conda-eda
* It would be great to investigate "EDA Containers" for usage with LiteX

## Workgroup Collaboration Tools

* [Meeting Minutes](
* Meeting invites are still not seeming to get mailed?
* Long term TODO : Need to make the system actually sends emails with ical attachments. It will take awhile to make this work. Rather we should have interested parties import the cal and get notifications.
* [WebSys Document](

- OPF Discuss (with calendar and link to chat)

- Slack / IRC / Mattermost
#librebmc on libera (namespace)

- OPF Files

- OPF Discuss

- OPF GIT repository
Will be mirrored to github and gitlab

- OPF Kanban (linked with chat)

## Community Involvement

* Options for not needing an AC922
* FPGA on both sides (emulating the HPM)
* Raptor has such a board that has an FPGA on both sides
* Can just use QEMU and simulate the AC922 side
* How do we generate more activity/interest
* Engage Universities -- **There are interested universities**
* Todd to start a list of universities and contacts **New direction here. Todd/Toshaan to make an OPF page "Education Page" that points to these projects as well as the OpenPOWER curriculum being developed. Then we can all point our education contacts to that page. No need to list them here**
* Need clear work breakdown. **We have this for some projects.**
* Need Mentors. **True for Interns/MLH/etc, but many projects can be supported in the open**
* Offer badges/certificates
* Offer Bounties
* Major League Hacking Interships
* Start end of May.
* Need to sign up by end of March
* Must have sponsors to guide students and hold office hours
* **We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors**
* To use MLH, We need BoD (Board of Directors) approval
* **Need work items clearly identified and easily understood**
* Documentation -- We need build instructions, readmes, etc
* Need someone replicate the FPGA/OpenBMC load from scratch
* Then document the process for others to follow so they can replicate the results
* Build all pieces -- Core, peripherals, OpenBMC,etc
* **Antmicro working this**

* Need official OpenBMC project and a makefile, bitbake/etc

* Need the project broken down into manageable pieces

* It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.
* **I did see an offer of help for a logo. I will follow up. TBD**

## Goals -- Need timelines on these -- WIP
* Tasks defined and project broken down
* Able to generate a bitstream for an FPGA using fully open source toolchain.
* Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
* Someone seriously starting to do a real (non-development) LibreBMC deployment.
* Fully functional Gateware and OpenBMC code stack for AC922
* Determine the performance/size

## Next Meeting

{{< localdatetime date="2022-05-25" time="22:00" >}}