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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions & limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make & use the physical chip.
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// Wordline decodes
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// Two versions:
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// 12-in -> 64 one-hot (all selects, 1 comp used)
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// 11-in -> 32 one-hot (half selects, 2 comps used)
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`timescale 1 ps / 1 ps
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module wordlines_comp_32 (
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input rd0_c_na0,
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input rd0_c_a0,
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input rd0_na1_na2,
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input rd0_na1_a2,
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input rd0_a1_na2,
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input rd0_a1_a2,
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input rd0_xa3,
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input rd0_na4_na5,
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input rd0_na4_a5,
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input rd0_a4_na5,
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input rd0_a4_a5,
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output [0:31] rwl0_0,
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output [0:31] rwl0_1,
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input rd1_c_na0,
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input rd1_c_a0,
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input rd1_na1_na2,
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input rd1_na1_a2,
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input rd1_a1_na2,
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input rd1_a1_a2,
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input rd1_xa3,
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input rd1_na4_na5,
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input rd1_na4_a5,
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input rd1_a4_na5,
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input rd1_a4_a5,
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output [0:31] rwl1_0,
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output [0:31] rwl1_1,
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input wr0_c_na0,
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input wr0_c_a0,
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input wr0_na1_na2,
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input wr0_na1_a2,
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input wr0_a1_na2,
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input wr0_a1_a2,
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input wr0_xa3,
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input wr0_na4_na5,
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input wr0_na4_a5,
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input wr0_a4_na5,
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input wr0_a4_a5,
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output [0:31] wwl0_0,
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output [0:31] wwl0_1
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);
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wire [0:31] rwl0;
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wire [0:31] rwl1;
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wire [0:31] wwl0;
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// 64 wordlines per port
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// if center sel is a0, 00:31 to left, 32:63 to right
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// if center sel is a3, xxx0xx to left, xxx1xx to right
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decode_wordlines_32 rd0 (
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.c_na0(rd0_c_na0),
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.c_a0(rd0_c_a0),
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.na1_na2(rd0_na1_na2),
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.na1_a2(rd0_na1_a2),
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.a1_na2(rd0_a1_na2),
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.a1_a2(rd0_a1_a2),
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.xa3(rd0_xa3),
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.na4_na5(rd0_na4_na5),
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.na4_a5(rd0_na4_a5),
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.a4_na5(rd0_a4_na5),
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.a4_a5(rd0_a4_a5),
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.wl(rwl0)
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);
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decode_wordlines_32 rd1 (
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.c_na0(rd1_c_na0),
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.c_a0(rd1_c_a0),
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.na1_na2(rd1_na1_na2),
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.na1_a2(rd1_na1_a2),
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.a1_na2(rd1_a1_na2),
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.a1_a2(rd1_a1_a2),
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.xa3(rd1_xa3),
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.na4_na5(rd1_na4_na5),
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.na4_a5(rd1_na4_a5),
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.a4_na5(rd1_a4_na5),
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.a4_a5(rd1_a4_a5),
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.wl(rwl1)
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);
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decode_wordlines_32 wr0 (
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.c_na0(wr0_c_na0),
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.c_a0(wr0_c_a0),
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.na1_na2(wr0_na1_na2),
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.na1_a2(wr0_na1_a2),
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.a1_na2(wr0_a1_na2),
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.a1_a2(wr0_a1_a2),
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.xa3(wr0_xa3),
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.na4_na5(wr0_na4_na5),
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.na4_a5(wr0_na4_a5),
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.a4_na5(wr0_a4_na5),
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.a4_a5(wr0_a4_a5),
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.wl(wwl0)
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);
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// add level for up/dn?
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assign rwl0_0 = rwl0;
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assign rwl0_1 = rwl0;
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assign rwl1_0 = rwl1;
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assign rwl1_1 = rwl1;
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assign wwl0_0 = wwl0;
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assign wwl0_1 = wwl0;
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endmodule
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