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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Predecode of 6 address bits into 4 one hot encodings
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`timescale 1 ns / 1 ns
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module predecode (
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strobe,
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enable,
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address,
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// 12 predecoded address lines 2 - 4 - 2 - 4 one hot encoding
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c_na0, // clock and not address(0)
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c_a0, // clock and address(0)
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na1_na2,// not address(1) and not address(2)
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na1_a2, // not address(1) and address(2)
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a1_na2, // address(1) and not address(2)
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a1_a2, // address(1) and address(2)
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na3, // not address(3)
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a3, // address(3)
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na4_na5,// not address(4) and not address(5)
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na4_a5, // not address(4) address(5)
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a4_na5, // address(4) and not address(5)
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a4_a5 // address(4) and address(5)
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);
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input strobe;
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input enable;
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input [0:5] address;
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output c_na0;
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output c_a0;
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output na1_na2;
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output na1_a2;
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output a1_na2;
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output a1_a2; // address(1) and address(2)
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output na3; // not address(3)
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output a3; // address(3)
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output na4_na5;// not address(4) and not address(5)
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output na4_a5; // not address(4) address(5)
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output a4_na5; // address(4) and not address(5)
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output a4_a5; // address(4) and address(5)
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wire clock_enable;
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wire [0:5] inv_address;
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wire n_c_na0;
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wire n_c_a0;
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wire n_na1_na2;
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wire n_na1_a2;
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wire n_a1_na2;
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wire n_a1_a2;
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wire n_na4_na5;
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wire n_na4_a5;
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wire n_a4_na5;
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wire n_a4_a5;
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// and read or write enable with clock
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// does this need to be SSB placed?
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assign clock_enable = strobe & enable;
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assign inv_address[0] = (~(address[0]));
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assign inv_address[1] = (~(address[1]));
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assign inv_address[2] = (~(address[2]));
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assign inv_address[3] = (~(address[3]));
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assign inv_address[4] = (~(address[4]));
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assign inv_address[5] = (~(address[5]));
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// A(0) address predecode and gating with clock
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assign c_na0 = clock_enable & inv_address[0];
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assign c_a0 = clock_enable & address[0];
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// A(1:2) address predecode
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assign na1_na2 = inv_address[1] & inv_address[2];
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assign na1_a2 = inv_address[1] & address[2];
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assign a1_na2 = address[1] & inv_address[2];
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assign a1_a2 = address[1] & address[2];
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// A(3) address predecode
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assign na3 = inv_address[3];
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assign a3 = address[3];
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// A(4:5) address predecode
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assign na4_na5 = inv_address[4] & inv_address[5];
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assign na4_a5 = inv_address[4] & address[5];
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assign a4_na5 = address[4] & inv_address[5];
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assign a4_a5 = address[4] & address[5];
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endmodule
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