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54 lines
1.1 KiB
Plaintext
54 lines
1.1 KiB
Plaintext
# sdr ra
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# make -f Makefile.icarus build # rebuild and sim and fst
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# make -f Makefile.icarus run # sim and fst
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# make -f Makefile.icarus # sim
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#COCOTB_LOG_LEVEL=DEBUG
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#GPI_EXTRA=vpi
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#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM
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#SIM_BUILD ?= build
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SIM ?= icarus
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# options
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#COCOTB_HDL_TIMEUNIT ?= 1ns
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#COCOTB_HDL_TIMEPRECISION ?= 1ps
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#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM
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# icarus
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#
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VERILOG_COMMON = src/array
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VERILOG_ROOT = src/array_shard
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# CFGINIT
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# only no delay works as-is in cycle sim
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# 00000000 : disable delay
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# 00000001 : enable delay, sdr
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# 00000003 : enable delay, ddr
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#
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#COMPILE_ARGS = -y$(VERILOG_ROOT) -y$(VERILOG_COMMON) -DGENMODE=1 -DCFGINIT=1
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COMPILE_ARGS = -y$(VERILOG_ROOT) -y$(VERILOG_COMMON) -DGENMODE=1
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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VERILOG_SOURCES = ./tb_ra_64x72_2r1w.v $(VERILOG_ROOT)/sky130_hd.v
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TOPLEVEL = tb_ra_64x72_2r1w
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# python test
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MODULE = tb_ra_64x72
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TESTCASE = tb
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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build: clean sim fst
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run: sim fst
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fst:
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vcd2fst tb_ra_64x72.vcd tb_ra_64x72.fst
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rm tb_ra_64x72.vcd
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