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// © IBM Corp. 2021
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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`timescale 1 ns / 1 ns
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`include "defines.v"
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`include "../toysram.vh"
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// control macro
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// does stuff
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module control #(
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parameter ADDR_MASK = 'h0000F000,
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parameter CFG_ADDR = 'h0000E000, // offset within RAx_ADDR
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parameter BIST_ADDR = 'h0000F000, // offset within RAx_ADDR
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parameter CFG0_ADDR = 'h00000000,
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parameter CFG0_INIT = 'h00000001
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)(
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`ifdef USE_POWER_PINS
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inout vccd1,
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inout vssd1
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`endif
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input clk,
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input rst,
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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input ctl_cmd_val,
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input ra0_cmd_val,
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input [31:0] cmd_adr,
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input cmd_we,
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input [3:0] cmd_sel,
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input [31:0] cmd_dat,
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output rd_ack,
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output [31:0] rd_dat,
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output ra0_clk,
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output ra0_rst,
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output ra0_cfg_wr,
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input [31:0] ra0_cfg_rdat,
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output [31:0] ra0_cfg_wdat,
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output [31:0] ra0_bist_ctl,
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input [31:0] ra0_bist_status,
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output ra0_r0_enb,
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output [4:0] ra0_r0_adr,
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input [31:0] ra0_r0_dat,
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output ra0_r1_enb,
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output [4:0] ra0_r1_adr,
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input [31:0] ra0_r1_dat,
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output ra0_w0_enb,
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output [4:0] ra0_w0_adr,
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output [31:0] ra0_w0_dat
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);
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reg [31:0] cfg0_q;
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wire [31:0] cfg0_d;
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reg [4:0] seq_q;
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wire [4:0] seq_d;
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reg [2:0] rd_wait_q;
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wire [2:0] rd_wait_d;
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reg [127:0] scan_reg_q;
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wire [127:0] scan_reg_d;
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wire ra0_bist_rd;
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wire adr_bist;
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wire adr_config;
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wire special;
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wire rd_start;
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wire [1:0] rd_type;
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wire [2:0] rdata_sel;
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wire rd_data;
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wire test_enable;
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wire scan_clk;
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wire scan_di;
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wire scan_do;
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wire [16:0] scan_config;
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wire io_ra0_clk;
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wire io_ra0_rst;
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wire io_ra0_r0_enb;
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wire io_ra0_r1_enb;
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wire io_ra0_w0_enb;
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wire [4:0] io_ra0_r0_adr;
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wire [4:0] io_ra0_r1_adr;
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wire [4:0] io_ra0_w0_adr;
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wire [31:0] io_ra0_w0_dat;
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// FF
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always @(posedge clk) begin
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if (rst) begin
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seq_q <= 'hFF;
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cfg0_q <= CFG0_INIT;
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rd_wait_q <= 0;
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end else begin
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seq_q <= seq_d;
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cfg0_q <= cfg0_d;
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rd_wait_q <= rd_wait_d;
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end
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end
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always @(posedge scan_clk) begin
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begin
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if (test_enable == 'b1) begin
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scan_reg_q <= {scan_reg_q[126:0], scan_di};
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end
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end
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end
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always @(posedge io_ra0_clk) begin
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if (test_enable == 'b1) begin
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scan_reg_q[122:91] <= {ra0_r0_dat};
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scan_reg_q[85:54] <= {ra0_r1_dat};
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end
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end
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// GPIO
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//
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// Scan Controls
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// test enable
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// scan_clk
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// scan_di
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// scan_do
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//
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// Scan Config
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// * have a way to single-step on-chip clk so can use it plus scan?
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//
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// Array Controls
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// ra_clk
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// ra_rst
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// ra_r0_enb
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// ra_r1_enb
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// ra_w0_enb
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//
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//
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// Scannable RA0 Reg
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// ra0_r0_adr
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// ra0_r0_dat
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// ra0_r1_adr
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// ra0_r1_dat
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// ra0_w0_adr
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// ra0_w0_dat
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//
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//
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// Array Read/Write
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// 1. scan in adr/dat reg
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// 2. activate ra_clk and ra_xx_enb for port control (n cycles)
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// 3. scan out adr/dat reg
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//
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//
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// * not enough I/O to do full-speed reads/writes through I/O; enough for addresses, and could have data gen/chk logic for data
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assign test_enable = io_in[0];
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assign scan_clk = io_in[1];
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assign scan_di = io_in[2];
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assign io_out[3] = scan_do;
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assign io_ra0_clk = io_in[4];
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assign io_ra0_rst = io_in[5];
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assign io_ra0_r0_enb = io_in[6];
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assign io_ra0_r1_enb = io_in[7];
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assign io_ra0_w0_enb = io_in[8];
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//assign io_oeb = '{`MPRJ_IO_PADS'('h0000000000000008)};
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assign io_oeb = ~'h0000000000000008;
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assign io_ra0_r0_adr = scan_reg_q[127:123];
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//assign io_ra0_r0_dat = scan_reg_q[122:91]; // loaded by io_ra0_clk
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assign io_ra0_r1_adr = scan_reg_q[90:86];
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//assign io_ra0_r1_dat = scan_reg_q[85:54]; // loaded by io_ra0_clk
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assign io_ra0_w0_adr = scan_reg_q[53:49];
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assign io_ra0_w0_dat = scan_reg_q[48:17];
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assign scan_config = scan_reg_q[16:0];
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assign scan_do = scan_reg_q[127];
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// Internal Routing
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// CFG0
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// 31:03 Reserved
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// 02:00 Read Data Wait Cycles (after cmd cycle)
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assign cfg0_d = ctl_cmd_val & cmd_we & ((cmd_adr & ~ADDR_MASK) == CFG0_ADDR) ? cmd_dat : cfg0_q;
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// Array Routing
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assign adr_bist = (cmd_adr & ADDR_MASK) == (BIST_ADDR & ADDR_MASK);
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assign adr_config = (cmd_adr & ADDR_MASK) == (CFG_ADDR & ADDR_MASK);
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assign special = adr_bist | adr_config;
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assign ra0_bist_ctl = ra0_cmd_val & cmd_we & adr_bist ? cmd_dat : 'h00000000;
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assign ra0_bist_rd = ra0_cmd_val & ~cmd_we & adr_bist;
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assign ra0_cfg_wr = ra0_cmd_val & cmd_we & adr_config;
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assign ra0_cfg_wdat = cmd_dat;
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// reads can use r0, r1, or both; if both, return either both hi or both lo data
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assign rd_type = cmd_adr[15:14]; // port addr 14 bits
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// or send test_enable and test_clk/rst to array
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assign ra0_clk = test_enable ? io_ra0_clk : clk;
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assign ra0_rst = test_enable ? io_ra0_rst : rst;
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assign ra0_r0_enb = test_enable ? io_ra0_r0_enb : ra0_cmd_val & ~special & ~cmd_we & (rd_type[0] | ~rd_type[1]);
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assign ra0_r1_enb = test_enable ? io_ra0_r1_enb : ra0_cmd_val & ~special & ~cmd_we & (rd_type[0] | rd_type[1]);
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assign ra0_r0_adr = test_enable ? io_ra0_r0_adr : cmd_adr[4:0]; // adr=row
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assign ra0_r1_adr = test_enable ? io_ra0_r1_adr : rd_type == 'b01 ? cmd_adr[4:0] : cmd_adr[10:6]; // adr=row
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assign ra0_w0_enb = test_enable ? io_ra0_w0_enb : ra0_cmd_val & cmd_we & cmd_sel[0]; // sel=port
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assign ra0_w0_adr = test_enable ? io_ra0_w0_adr : cmd_adr[4:0]; // adr=row
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assign ra0_w0_dat = test_enable ? io_ra0_w0_dat : cmd_dat; //
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// Command Sequencer
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// rd_data in 1+ cycs; all reads use same timing
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//tbl cmdseq
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//n seq_q seq_d
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//n | ctl_cmd_val | rd_start
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//n | |ra0_cmd_val | | rd_ack
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//n | ||cmd_we | | | rdata_sel
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//n | ||| rd_type | | | |
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//n | ||| | adr_bist | | | |
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//n | ||| | |adr_config | | | |
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//n | ||| | || rd_data | | | |
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//n | ||| | || | | | | |
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//n | ||| | || | | | | |
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//n | ||| | || | | | | |
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//b 43210 ||| 10 || | 43210 | | 210
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//t iiiii iii ii ii i ooooo o o ooo
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//*------------------------------------------------
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//* Idle ******************************************
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//s 11111 00- -- -- - 11111 0 0 000 * ...zzz..zzzzz....
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//s 11111 1-1 -- -- - 11111 0 0 000 * write ctl
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//s 11111 -11 -- -- - 11111 0 0 000 * write ra
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//s 11111 1-0 -- 00 - 00001 1 0 000 * rd ctl cfg
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//s 11111 1-0 -- 1- - 00010 1 0 000 * rd bist
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//s 11111 1-0 -- -1 - 00011 1 0 000 * rd cfg
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//s 11111 -10 00 -- - 00100 1 0 000 * rd r0
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//s 11111 -10 01 -- - 00101 1 0 000 * rd r1
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//s 11111 -10 10 -- - 00110 1 0 000 * rd r0+r1 lo
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//s 11111 -10 11 -- - 00111 1 0 000 * rd r0_r1 hi
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//* Read CTL **************************************
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//s 00001 --- -- -- 0 00001 0 0 100
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//s 00001 --- -- -- 1 11111 0 1 100
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//* Read BIST *************************************
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//s 00010 --- -- -- 0 00010 0 0 101
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//s 00010 --- -- -- 1 11111 0 1 101
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//* Read CFG **************************************
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//s 00011 --- -- -- 0 00011 0 0 110
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//s 00011 --- -- -- 1 11111 0 1 110
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//* Read R0 ***************************************
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//s 00100 --- -- -- 0 00100 0 0 000
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//s 00100 --- -- -- 1 11111 0 1 000
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//* Read R1 ***************************************
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//s 00101 --- -- -- 0 00101 0 0 001
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//s 00101 --- -- -- 1 11111 0 1 001
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//* Read R0+R1 Lo *********************************
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//s 00110 --- -- -- 0 00110 0 0 010
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//s 00110 --- -- -- 1 11111 0 1 010
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//* Read R0+R1 Hi *********************************
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//s 00111 --- -- -- 0 00111 0 0 011
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//s 00111 --- -- -- 1 11111 0 1 011
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//*------------------------------------------------
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//tbl cmdseq_d
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// use same timing for ra accesses and others
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assign rd_wait_d = rd_start ? cfg0_q[2:0] :
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(rd_wait_q != 0) ? rd_wait_q - 1 :
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rd_wait_q;
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assign rd_data = rd_wait_q == 0;
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assign rd_dat = rdata_sel == 'b000 ? ra0_r0_dat :
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rdata_sel == 'b001 ? ra0_r1_dat :
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rdata_sel == 'b010 ? {ra0_r1_dat[15:0],ra0_r0_dat[15:0]} :
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rdata_sel == 'b011 ? {ra0_r1_dat[31:16],ra0_r0_dat[31:16]} :
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rdata_sel == 'b100 ? cfg0_q :
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rdata_sel == 'b101 ? ra0_bist_status :
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rdata_sel == 'b110 ? ra0_cfg_rdat :
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'hFFFFFFFF;
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// Generated...
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//vtable cmdseq
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assign seq_d[4] =
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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assign seq_d[3] =
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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assign seq_d[2] =
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & ~rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & ~rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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assign seq_d[1] =
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_bist) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_config) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & ~rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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assign seq_d[0] =
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~ctl_cmd_val & ~ra0_cmd_val) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & cmd_we) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & ~adr_bist & ~adr_config) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_config) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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assign rd_start =
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & ~adr_bist & ~adr_config) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_bist) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ctl_cmd_val & ~cmd_we & adr_config) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & ~rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & ~rd_type[1] & rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & ~rd_type[0]) +
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(seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ra0_cmd_val & ~cmd_we & rd_type[1] & rd_type[0]);
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assign rd_ack =
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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assign rdata_sel[2] =
|
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
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|
assign rdata_sel[1] =
|
|
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
|
|
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(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
|
|
|
assign rdata_sel[0] =
|
|
|
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & ~rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0] & rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~rd_data) +
|
|
|
(~seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & rd_data);
|
|
|
//vtable cmdseq
|
|
|
|
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|
endmodule
|