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224 lines
7.8 KiB
Markdown
224 lines
7.8 KiB
Markdown
<!---
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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-->
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A quick documentation of the Caravel memory map and operation
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---------------------------------------------------------------
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Caravel pinout:
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---------------
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vddio 3.3V supply for all I/O and ESD
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vssio Ground for all I/O and ESD
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vdda 3.3V supply for management area
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vssa Ground for management area
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vccd 1.8V supply for management area
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vssd Digital ground for management area
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vdda1 3.3V supply for user area 1
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vdda2 3.3V supply for user area 2
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vssa1 Ground for user area 1
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vssa2 Ground for user area 2
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vccd1 1.8 supply for user area 1
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vccd2 1.8 supply for user area 2
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vssd1 Digital ground for user area 1
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vssd2 Digital ground for user area 2
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clock Master clock input
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gpio 1 bit, mainly used for external LDO control of user power supply
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mprj_io 32 bits general purpose programmable digital or analog I/O
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resetb Master reset (sense inverted) input
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flash_csb SPI flash controller chip select (sense inverted)
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flash_clk SPI flash controller clock
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flash_io0 SPI flash controller data out
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flash_io1 SPI flash controller data in
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Special-use pins for the management SoC:
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----------------------------------------
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On power-up, the "mprj_io" GPIO are under complete control of the managment
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SoC. The first 8 user GPIO are special-purpose pads with dedicated functions
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for the management SoC:
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mprj_io[0] JTAG I/O
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mprj_io[1] SDO, housekeeping SPI
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mprj_io[2] SDI, housekeeping SPI
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mprj_io[3] CSB, housekeeping SPI
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mprj_io[4] SCK, housekeeping SPI
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mprj_io[5] Rx, UART
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mprj_io[6] Tx, UART
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mprj_io[7] IRQ
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The next 4 user GPIO are designed to be used with an SPI flash controller in
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the user space. They allow the four pins to be overridden by the housekeeping
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SPI to access the SPI flash in pass-through mode.
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mprj_io[8] user flash CSB
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mprj_io[9] user flash SCK
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mprj_io[10] user flash IO0
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mprj_io[11] user flash IO1
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The last 2 GPIO pins can be used by the management SoC to drive the SPI flash
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io2 and io3 pins for quad and DDR access, although they are set as inputs by
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default and whenever the SPI flash is not in quad mode:
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mprj_io[36] SPI flash io2
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mprj_io[37] SPI flash io3
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The user may additionally use any available GPIO for the SPI flash IO2 and IO3
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lines; the pass-through mode only uses the basic 4-pin SPI mode.
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All of the special-use pins are configured through a memory-mapped region. But
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to avoid a large number of wires in the user space to reach all of the GPIO
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pad controls, each user GPIO pad has a corresponding local control block. The
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control block holds the configuration data for the corresponding pad. This
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configuration data is a mirror of the data in the memory-mapped region, and is
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loaded by a "transfer" bit in another memory-mapped register. In addition to
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all of the static control bits for the GPIO, each block contains a single bit
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that specifies whether that pad is under the control of the user or the management
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area. All pins are configured from the management area. However, the configuration
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of static control bits leaves three dynamic signals: input, output, and output
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enable. One set of these three signals is available to the user when the pad is
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under user control. The other set of these three signals is available to the
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management SoC. Again, to reduce wiring, only the two pads for JTAG and the
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housekeeping SDO have all three pins under control of the SoC; the remaining
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pads have a single wire to the management SoC which is either an input wire
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or an output wire, depending on how the control signals for the pad are set.
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This setup gives a simplified view of the pad to the user: For digital
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applications, the user can treat the pad as a simple bidirectional digital
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pad with an output enable to switch between output and input functions.
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The user can set the output enable line high or low for a static input or
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output function. The user will also have access to the ESD-protected
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pad connections for analog signals, and can connect to the VDDA domain
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input digital signal if needed.
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Memory map:
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-----------
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The Caravel memory map is as follows:
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SRAM: 0000 0000
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Flash: Config: 1000 0000
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UART: Clock divider: 2000 0000
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Data: 2000 0004
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Enable 2000 0008
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GPIO: Data: 2100 0000
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Output enable: 2100 0004
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Pullup 2100 0008
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Pulldown 2100 000c
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Counter 1: Config: 2200 0000
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Value: 2200 0004
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Data: 2200 0008
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Counter 2: Config: 2300 0000
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Value: 2300 0004
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Data: 2300 0008
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SPI master: Config: 2400 0000
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Data: 2400 0004
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Logic analyzer: Data 0: 2500 0000
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Data 1: 2500 0004
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Data 2: 2500 0008
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Data 3: 2500 000c
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Enable 0: 2500 0010
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Enable 1: 2500 0014
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Enable 2: 2500 0018
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Enable 3: 2500 001c
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Project ctrl: Data (L): 2600 0000
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Data (H): 2600 0004
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Transfer: 2600 0008
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I/O Config: 2600 000c
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to 2600 009c
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Power Config: 2600 00a0
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to 2600 0130
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Flash ctrl: Config: 2D00 0000
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System: PLL out: 2F00 0000
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Trap out: 2F00 0004
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IRQ7 source: 2F00 0008
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User area base: 3000 0000
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Crossbar: QSPI control 8000 0000
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Storage area 9000 0000
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Any slave 1 a000 0000
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Any slave 2 b000 0000
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Project I/O Control:
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---------------------
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Configuration bits per I/O (13 bits for each GPIO pad):
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Global Default
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Bits 12-10: digital mode (3 bits) 001
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Bit 9: voltage trip point select 0
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Bit 8: slow slew select 0
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Bit 7: analog bus polarity 0
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Bit 6: analog bus select 0
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Bit 5: analog bus enable 0
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Bit 4: IB mode select 0
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Bit 3: input disable 0
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Bit 2: holdover value 0
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Bit 1: output disable 1
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Bit 0: management control enable 1
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Default I/O modes:
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------------------
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mprj_io[0] JTAG I/O 110 0 0 0 0 0 0 0 0 0 1
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mprj_io[1] SDO, housekeeping SPI 110 0 0 0 0 0 0 0 0 0 1
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all others: 001 0 0 0 0 0 0 0 0 1 1
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Standard GPIO output configuration:
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mprj_io[6] Tx, UART 110 0 0 0 0 0 0 1 0 0 1
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Standard GPIO input configuration:
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mprj_io[*] 001 0 0 0 0 0 0 0 0 1 1
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Standard GPIO input configuration with pullup:
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mprj_io[*] 010 0 0 0 0 0 0 0 0 1 1
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Standard GPIO input configuration with pulldown:
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mprj_io[*] 011 0 0 0 0 0 0 0 0 1 1
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Specifically:
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JTAG and SDO are set to output. The output enable configure bit
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is a don't-care, since the output enable line is directly controlled
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by the module (JTAG or housekeeping SPI, respectively).
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All other I/O are set as input mode only, with output disabled.
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Tx is set to input like the others; before enabling the UART
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from a program in flash, the I/O must be set to an output configuration.
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Note that the standard input configurations with pull-up and pull-down
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require that "out" be set 1 or 0, respectively; since the I/O are
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designed with minimal wiring, there is only one wire for input and
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output, so the wire is used for input in these cases, and special
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signal handling is done locally to set the value of "out" equal to
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~dm[0]. This is a (minor) restriction on the available I/O modes.
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Other possible modes are open-drain (for I2C), weak drive strength
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output (5k up + down), and analog mode (digital disabled)
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