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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Behavioral for 16x12 toysram subarray
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`timescale 1 ps / 1 ps
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module toysram_16x12 (
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input [0:15] RWL0,
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input [0:15] RWL1,
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input [0:15] WWL,
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output [0:11] RBL0,
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output [0:11] RBL1,
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input [0:11] WBL,
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input [0:11] WBLb
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);
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reg [0:11] mem_00;
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reg [0:11] mem_01;
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reg [0:11] mem_02;
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reg [0:11] mem_03;
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reg [0:11] mem_04;
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reg [0:11] mem_05;
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reg [0:11] mem_06;
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reg [0:11] mem_07;
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reg [0:11] mem_08;
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reg [0:11] mem_09;
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reg [0:11] mem_10;
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reg [0:11] mem_11;
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reg [0:11] mem_12;
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reg [0:11] mem_13;
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reg [0:11] mem_14;
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reg [0:11] mem_15;
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// word-select
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assign RBL0 = (mem_00 & {12{RWL0[0]}}) |
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(mem_01 & {12{RWL0[1]}}) |
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(mem_02 & {12{RWL0[2]}}) |
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(mem_03 & {12{RWL0[3]}}) |
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(mem_04 & {12{RWL0[4]}}) |
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(mem_05 & {12{RWL0[5]}}) |
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(mem_06 & {12{RWL0[6]}}) |
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(mem_07 & {12{RWL0[7]}}) |
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(mem_08 & {12{RWL0[8]}}) |
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(mem_09 & {12{RWL0[9]}}) |
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(mem_10 & {12{RWL0[10]}}) |
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(mem_11 & {12{RWL0[11]}}) |
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(mem_12 & {12{RWL0[12]}}) |
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(mem_13 & {12{RWL0[13]}}) |
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(mem_14 & {12{RWL0[14]}}) |
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(mem_15 & {12{RWL0[15]}});
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assign RBL1 = (mem_00 & {12{RWL1[0]}}) |
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(mem_01 & {12{RWL1[1]}}) |
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(mem_02 & {12{RWL1[2]}}) |
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(mem_03 & {12{RWL1[3]}}) |
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(mem_04 & {12{RWL1[4]}}) |
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(mem_05 & {12{RWL1[5]}}) |
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(mem_06 & {12{RWL1[6]}}) |
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(mem_07 & {12{RWL1[7]}}) |
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(mem_08 & {12{RWL1[8]}}) |
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(mem_09 & {12{RWL1[9]}}) |
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(mem_10 & {12{RWL1[10]}}) |
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(mem_11 & {12{RWL1[11]}}) |
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(mem_12 & {12{RWL1[12]}}) |
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(mem_13 & {12{RWL1[13]}}) |
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(mem_14 & {12{RWL1[14]}}) |
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(mem_15 & {12{RWL1[15]}});
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always @(posedge WWL[0]) begin
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#10; mem_00 <= ~WBLb;
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end
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always @(posedge WWL[1]) begin
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#10; mem_01 <= ~WBLb;
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end
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always @(posedge WWL[2]) begin
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#10; mem_02 <= ~WBLb;
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end
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always @(posedge WWL[3]) begin
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#10; mem_03 <= ~WBLb;
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end
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always @(posedge WWL[4]) begin
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#10; mem_04 <= ~WBLb;
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end
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always @(posedge WWL[5]) begin
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#10; mem_05 <= ~WBLb;
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end
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always @(posedge WWL[6]) begin
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#10; mem_06 <= ~WBLb;
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end
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always @(posedge WWL[7]) begin
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#10; mem_07 <= ~WBLb;
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end
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always @(posedge WWL[8]) begin
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#10; mem_08 <= ~WBLb;
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end
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always @(posedge WWL[9]) begin
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#10; mem_09 <= ~WBLb;
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end
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always @(posedge WWL[10]) begin
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#10; mem_10 <= ~WBLb;
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end
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always @(posedge WWL[11]) begin
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#10; mem_11 <= ~WBLb;
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end
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always @(posedge WWL[12]) begin
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#10; mem_12 <= ~WBLb;
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end
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always @(posedge WWL[13]) begin
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#10; mem_13 <= ~WBLb;
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end
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always @(posedge WWL[14]) begin
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#10; mem_14 <= ~WBLb;
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end
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always @(posedge WWL[15]) begin
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#10; mem_15 <= ~WBLb;
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end
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// assert errors (multiwrite, etc.)
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endmodule |