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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Behavioral for 16x12 toysram subarray
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`timescale 1 ps / 1 ps
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module toysram_32x12 (
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input [0:31] RWL0,
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input [0:31] RWL1,
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input [0:31] WWL,
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output [0:11] RBL0,
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output [0:11] RBL1,
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input [0:11] WBL,
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input [0:11] WBLb
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);
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reg [0:11] mem_00;
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reg [0:11] mem_01;
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reg [0:11] mem_02;
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reg [0:11] mem_03;
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reg [0:11] mem_04;
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reg [0:11] mem_05;
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reg [0:11] mem_06;
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reg [0:11] mem_07;
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reg [0:11] mem_08;
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reg [0:11] mem_09;
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reg [0:11] mem_10;
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reg [0:11] mem_11;
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reg [0:11] mem_12;
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reg [0:11] mem_13;
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reg [0:11] mem_14;
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reg [0:11] mem_15;
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reg [0:11] mem_16;
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reg [0:11] mem_17;
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reg [0:11] mem_18;
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reg [0:11] mem_19;
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reg [0:11] mem_20;
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reg [0:11] mem_21;
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reg [0:11] mem_22;
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reg [0:11] mem_23;
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reg [0:11] mem_24;
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reg [0:11] mem_25;
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reg [0:11] mem_26;
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reg [0:11] mem_27;
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reg [0:11] mem_28;
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reg [0:11] mem_29;
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reg [0:11] mem_30;
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reg [0:11] mem_31;
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// word-select
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// the local eval is done between subarray pairs, and bits are positive going out
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assign RBL0 = ((mem_00 & {12{RWL0[0]}}) | (mem_16 & {12{RWL0[16]}})) |
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((mem_01 & {12{RWL0[1]}}) | (mem_17 & {12{RWL0[17]}})) |
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((mem_02 & {12{RWL0[2]}}) | (mem_18 & {12{RWL0[18]}})) |
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((mem_03 & {12{RWL0[3]}}) | (mem_19 & {12{RWL0[19]}})) |
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((mem_04 & {12{RWL0[4]}}) | (mem_20 & {12{RWL0[20]}})) |
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((mem_05 & {12{RWL0[5]}}) | (mem_21 & {12{RWL0[21]}})) |
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((mem_06 & {12{RWL0[6]}}) | (mem_22 & {12{RWL0[22]}})) |
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((mem_07 & {12{RWL0[7]}}) | (mem_23 & {12{RWL0[23]}})) |
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((mem_08 & {12{RWL0[8]}}) | (mem_24 & {12{RWL0[24]}})) |
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((mem_09 & {12{RWL0[9]}}) | (mem_25 & {12{RWL0[25]}})) |
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((mem_10 & {12{RWL0[10]}}) | (mem_26 & {12{RWL0[26]}})) |
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((mem_11 & {12{RWL0[11]}}) | (mem_27 & {12{RWL0[27]}})) |
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((mem_12 & {12{RWL0[12]}}) | (mem_28 & {12{RWL0[28]}})) |
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((mem_13 & {12{RWL0[13]}}) | (mem_29 & {12{RWL0[29]}})) |
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((mem_14 & {12{RWL0[14]}}) | (mem_30 & {12{RWL0[30]}})) |
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((mem_15 & {12{RWL0[15]}}) | (mem_31 & {12{RWL0[31]}}));
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assign RBL1 = ((mem_00 & {12{RWL1[0]}}) | (mem_16 & {12{RWL1[16]}})) |
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((mem_01 & {12{RWL1[1]}}) | (mem_17 & {12{RWL1[17]}})) |
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((mem_02 & {12{RWL1[2]}}) | (mem_18 & {12{RWL1[18]}})) |
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((mem_03 & {12{RWL1[3]}}) | (mem_19 & {12{RWL1[19]}})) |
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((mem_04 & {12{RWL1[4]}}) | (mem_20 & {12{RWL1[20]}})) |
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((mem_05 & {12{RWL1[5]}}) | (mem_21 & {12{RWL1[21]}})) |
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((mem_06 & {12{RWL1[6]}}) | (mem_22 & {12{RWL1[22]}})) |
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((mem_07 & {12{RWL1[7]}}) | (mem_23 & {12{RWL1[23]}})) |
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((mem_08 & {12{RWL1[8]}}) | (mem_24 & {12{RWL1[24]}})) |
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((mem_09 & {12{RWL1[9]}}) | (mem_25 & {12{RWL1[25]}})) |
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((mem_10 & {12{RWL1[10]}}) | (mem_26 & {12{RWL1[26]}})) |
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((mem_11 & {12{RWL1[11]}}) | (mem_27 & {12{RWL1[27]}})) |
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((mem_12 & {12{RWL1[12]}}) | (mem_28 & {12{RWL1[28]}})) |
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((mem_13 & {12{RWL1[13]}}) | (mem_29 & {12{RWL1[29]}})) |
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((mem_14 & {12{RWL1[14]}}) | (mem_30 & {12{RWL1[30]}})) |
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((mem_15 & {12{RWL1[15]}}) | (mem_31 & {12{RWL1[31]}}));
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always @(posedge WWL[0]) begin
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mem_00 <= WBL | ~WBLb;
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end
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always @(posedge WWL[1]) begin
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mem_01 <= WBL | ~WBLb;
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end
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always @(posedge WWL[2]) begin
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mem_02 <= WBL | ~WBLb;
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end
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always @(posedge WWL[3]) begin
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mem_03 <= WBL | ~WBLb;
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end
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always @(posedge WWL[4]) begin
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mem_04 <= WBL | ~WBLb;
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end
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always @(posedge WWL[5]) begin
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mem_05 <= WBL | ~WBLb;
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end
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always @(posedge WWL[6]) begin
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mem_06 <= WBL | ~WBLb;
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end
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always @(posedge WWL[7]) begin
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mem_07 <= WBL | ~WBLb;
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end
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always @(posedge WWL[8]) begin
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mem_08 <= WBL | ~WBLb;
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end
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always @(posedge WWL[9]) begin
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mem_09 <= WBL | ~WBLb;
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end
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always @(posedge WWL[10]) begin
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mem_10 <= WBL | ~WBLb;
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end
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always @(posedge WWL[11]) begin
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mem_11 <= WBL | ~WBLb;
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end
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always @(posedge WWL[12]) begin
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mem_12 <= WBL | ~WBLb;
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end
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always @(posedge WWL[13]) begin
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mem_13 <= WBL | ~WBLb;
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end
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always @(posedge WWL[14]) begin
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mem_14 <= WBL | ~WBLb;
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end
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always @(posedge WWL[15]) begin
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mem_15 <= WBL | ~WBLb;
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end
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always @(posedge WWL[16]) begin
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mem_16 <= WBL | ~WBLb;
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end
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always @(posedge WWL[17]) begin
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mem_17 <= WBL | ~WBLb;
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end
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always @(posedge WWL[18]) begin
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mem_18 <= WBL | ~WBLb;
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end
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always @(posedge WWL[19]) begin
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mem_19 <= WBL | ~WBLb;
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end
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always @(posedge WWL[20]) begin
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mem_20 <= WBL | ~WBLb;
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end
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always @(posedge WWL[21]) begin
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mem_21 <= WBL | ~WBLb;
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end
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always @(posedge WWL[22]) begin
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mem_22 <= WBL | ~WBLb;
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end
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always @(posedge WWL[23]) begin
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mem_23 <= WBL | ~WBLb;
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end
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always @(posedge WWL[24]) begin
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mem_24 <= WBL | ~WBLb;
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end
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always @(posedge WWL[25]) begin
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mem_25 <= WBL | ~WBLb;
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end
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always @(posedge WWL[26]) begin
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mem_26 <= WBL | ~WBLb;
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end
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always @(posedge WWL[27]) begin
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mem_27 <= WBL | ~WBLb;
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end
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always @(posedge WWL[28]) begin
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mem_28 <= WBL | ~WBLb;
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end
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always @(posedge WWL[29]) begin
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mem_29 <= WBL | ~WBLb;
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end
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always @(posedge WWL[30]) begin
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mem_30 <= WBL | ~WBLb;
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end
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always @(posedge WWL[31]) begin
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mem_31 <= WBL | ~WBLb;
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end
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// assert errors (multiwrite, etc.)
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endmodule |