$date
	Thu May 26 11:53:41 2022
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module test_ra_sdr_64x72 $end
$var wire 32 ! bist_ctl [0:31] $end
$var wire 32 " bist_status [0:31] $end
$var wire 16 # cfg_dat [0:15] $end
$var wire 1 $ cfg_wr $end
$var wire 1 % clk $end
$var wire 6 & rd_adr_0 [0:5] $end
$var wire 6 ' rd_adr_1 [0:5] $end
$var wire 1 ( rd_enb_0 $end
$var wire 1 ) rd_enb_1 $end
$var wire 1 * reset $end
$var wire 6 + wr_adr_0 [0:5] $end
$var wire 72 , wr_dat_0 [0:71] $end
$var wire 1 - wr_enb_0 $end
$var wire 1 . strobe $end
$var wire 72 / rd_dat_1 [0:71] $end
$var wire 72 0 rd_dat_0 [0:71] $end
$var wire 1 1 mux_wr0_enb $end
$var wire 72 2 mux_wr0_dat [0:71] $end
$var wire 6 3 mux_wr0_adr [0:5] $end
$var wire 1 4 mux_rd1_enb $end
$var wire 6 5 mux_rd1_adr [0:5] $end
$var wire 1 6 mux_rd0_enb $end
$var wire 6 7 mux_rd0_adr [0:5] $end
$var wire 16 8 cfg [0:15] $end
$scope module bist $end
$var wire 6 9 bist_rd0_adr [5:0] $end
$var wire 1 : bist_rd0_enb $end
$var wire 6 ; bist_rd1_adr [5:0] $end
$var wire 1 < bist_rd1_enb $end
$var wire 6 = bist_wr0_adr [5:0] $end
$var wire 72 > bist_wr0_dat [71:0] $end
$var wire 1 ? bist_wr0_enb $end
$var wire 1 % clk $end
$var wire 32 @ ctl [31:0] $end
$var wire 6 A rd0_adr_in [5:0] $end
$var wire 1 ( rd0_enb_in $end
$var wire 6 B rd1_adr_in [5:0] $end
$var wire 1 ) rd1_enb_in $end
$var wire 1 * reset $end
$var wire 6 C seq_d [5:0] $end
$var wire 32 D status [31:0] $end
$var wire 6 E wr0_adr_in [5:0] $end
$var wire 72 F wr0_dat_in [71:0] $end
$var wire 1 - wr0_enb_in $end
$var wire 1 1 wr0_enb_out $end
$var wire 72 G wr0_dat_out [71:0] $end
$var wire 6 H wr0_adr_out [5:0] $end
$var wire 1 4 rd1_enb_out $end
$var wire 72 I rd1_dat [71:0] $end
$var wire 6 J rd1_adr_out [5:0] $end
$var wire 1 6 rd0_enb_out $end
$var wire 72 K rd0_dat [71:0] $end
$var wire 6 L rd0_adr_out [5:0] $end
$var wire 1 M active $end
$var reg 6 N seq_q [5:0] $end
$upscope $end
$scope module cfig $end
$var wire 16 O cfg [0:15] $end
$var wire 16 P cfg_dat [0:15] $end
$var wire 1 $ cfg_wr $end
$var wire 1 % clk $end
$var wire 1 * reset $end
$var wire 16 Q cfg_d [0:15] $end
$var reg 16 R cfg_q [0:15] $end
$upscope $end
$scope module lcb $end
$var wire 16 S cfg [0:15] $end
$var wire 1 % clk $end
$var wire 1 * reset $end
$var wire 1 . strobe $end
$scope begin genblk1 $end
$upscope $end
$upscope $end
$scope module ra $end
$var wire 1 % clk $end
$var wire 6 T rd_adr_0 [0:5] $end
$var wire 6 U rd_adr_1 [0:5] $end
$var wire 1 6 rd_enb_0 $end
$var wire 1 4 rd_enb_1 $end
$var wire 1 * reset $end
$var wire 1 . strobe $end
$var wire 1 V strobe_int $end
$var wire 6 W wr_adr_0 [0:5] $end
$var wire 72 X wr_dat_0 [0:71] $end
$var wire 1 1 wr_enb_0 $end
$var wire 1 Y wr0_na4_na5 $end
$var wire 1 Z wr0_na4_a5 $end
$var wire 1 [ wr0_na3 $end
$var wire 1 \ wr0_na1_na2 $end
$var wire 1 ] wr0_na1_a2 $end
$var wire 1 ^ wr0_c_na0 $end
$var wire 1 _ wr0_c_a0 $end
$var wire 1 ` wr0_a4_na5 $end
$var wire 1 a wr0_a4_a5 $end
$var wire 1 b wr0_a3 $end
$var wire 1 c wr0_a1_na2 $end
$var wire 1 d wr0_a1_a2 $end
$var wire 72 e rd_dat_1 [0:71] $end
$var wire 72 f rd_dat_0 [0:71] $end
$var wire 1 g rd1_na4_na5 $end
$var wire 1 h rd1_na4_a5 $end
$var wire 1 i rd1_na3 $end
$var wire 1 j rd1_na1_na2 $end
$var wire 1 k rd1_na1_a2 $end
$var wire 1 l rd1_c_na0 $end
$var wire 1 m rd1_c_a0 $end
$var wire 1 n rd1_a4_na5 $end
$var wire 1 o rd1_a4_a5 $end
$var wire 1 p rd1_a3 $end
$var wire 1 q rd1_a1_na2 $end
$var wire 1 r rd1_a1_a2 $end
$var wire 1 s rd0_na4_na5 $end
$var wire 1 t rd0_na4_a5 $end
$var wire 1 u rd0_na3 $end
$var wire 1 v rd0_na1_na2 $end
$var wire 1 w rd0_na1_a2 $end
$var wire 1 x rd0_c_na0 $end
$var wire 1 y rd0_c_a0 $end
$var wire 1 z rd0_a4_na5 $end
$var wire 1 { rd0_a4_a5 $end
$var wire 1 | rd0_a3 $end
$var wire 1 } rd0_a1_na2 $end
$var wire 1 ~ rd0_a1_a2 $end
$var wire 72 !" ra_rd_dat_1 [0:71] $end
$var wire 72 "" ra_rd_dat_0 [0:71] $end
$var reg 6 #" rd_adr_0_q [0:5] $end
$var reg 6 $" rd_adr_1_q [0:5] $end
$var reg 72 %" rd_dat_0_q [0:71] $end
$var reg 72 &" rd_dat_1_q [0:71] $end
$var reg 1 '" rd_enb_0_q $end
$var reg 1 (" rd_enb_1_q $end
$var reg 6 )" wr_adr_0_q [0:5] $end
$var reg 72 *" wr_dat_0_q [0:71] $end
$var reg 1 +" wr_enb_0_q $end
$scope begin genblk1 $end
$upscope $end
$scope begin genblk2 $end
$upscope $end
$scope module add_clk $end
$var wire 6 ," rd_adr_0 [0:5] $end
$var wire 6 -" rd_adr_1 [0:5] $end
$var wire 1 '" rd_enb_0 $end
$var wire 1 (" rd_enb_1 $end
$var wire 1 V strobe $end
$var wire 6 ." wr_adr_0 [0:5] $end
$var wire 1 +" wr_enb_0 $end
$var wire 1 Y wr0_na4_na5 $end
$var wire 1 Z wr0_na4_a5 $end
$var wire 1 [ wr0_na3 $end
$var wire 1 \ wr0_na1_na2 $end
$var wire 1 ] wr0_na1_a2 $end
$var wire 1 ^ wr0_c_na0 $end
$var wire 1 _ wr0_c_a0 $end
$var wire 1 ` wr0_a4_na5 $end
$var wire 1 a wr0_a4_a5 $end
$var wire 1 b wr0_a3 $end
$var wire 1 c wr0_a1_na2 $end
$var wire 1 d wr0_a1_a2 $end
$var wire 1 g rd1_na4_na5 $end
$var wire 1 h rd1_na4_a5 $end
$var wire 1 i rd1_na3 $end
$var wire 1 j rd1_na1_na2 $end
$var wire 1 k rd1_na1_a2 $end
$var wire 1 l rd1_c_na0 $end
$var wire 1 m rd1_c_a0 $end
$var wire 1 n rd1_a4_na5 $end
$var wire 1 o rd1_a4_a5 $end
$var wire 1 p rd1_a3 $end
$var wire 1 q rd1_a1_na2 $end
$var wire 1 r rd1_a1_a2 $end
$var wire 1 s rd0_na4_na5 $end
$var wire 1 t rd0_na4_a5 $end
$var wire 1 u rd0_na3 $end
$var wire 1 v rd0_na1_na2 $end
$var wire 1 w rd0_na1_a2 $end
$var wire 1 x rd0_c_na0 $end
$var wire 1 y rd0_c_a0 $end
$var wire 1 z rd0_a4_na5 $end
$var wire 1 { rd0_a4_a5 $end
$var wire 1 | rd0_a3 $end
$var wire 1 } rd0_a1_na2 $end
$var wire 1 ~ rd0_a1_a2 $end
$scope module predecode_r0 $end
$var wire 1 ~ a1_a2 $end
$var wire 1 } a1_na2 $end
$var wire 1 { a4_a5 $end
$var wire 1 z a4_na5 $end
$var wire 6 /" address [0:5] $end
$var wire 1 y c_a0 $end
$var wire 1 x c_na0 $end
$var wire 1 0" clock_enable $end
$var wire 1 '" enable $end
$var wire 1 w na1_a2 $end
$var wire 1 v na1_na2 $end
$var wire 1 t na4_a5 $end
$var wire 1 s na4_na5 $end
$var wire 1 V strobe $end
$var wire 1 u na3 $end
$var wire 6 1" inv_address [0:5] $end
$var wire 1 | a3 $end
$upscope $end
$scope module predecode_r1 $end
$var wire 1 r a1_a2 $end
$var wire 1 q a1_na2 $end
$var wire 1 o a4_a5 $end
$var wire 1 n a4_na5 $end
$var wire 6 2" address [0:5] $end
$var wire 1 m c_a0 $end
$var wire 1 l c_na0 $end
$var wire 1 3" clock_enable $end
$var wire 1 (" enable $end
$var wire 1 k na1_a2 $end
$var wire 1 j na1_na2 $end
$var wire 1 h na4_a5 $end
$var wire 1 g na4_na5 $end
$var wire 1 V strobe $end
$var wire 1 i na3 $end
$var wire 6 4" inv_address [0:5] $end
$var wire 1 p a3 $end
$upscope $end
$scope module predecode_w0 $end
$var wire 1 d a1_a2 $end
$var wire 1 c a1_na2 $end
$var wire 1 a a4_a5 $end
$var wire 1 ` a4_na5 $end
$var wire 6 5" address [0:5] $end
$var wire 1 _ c_a0 $end
$var wire 1 ^ c_na0 $end
$var wire 1 6" clock_enable $end
$var wire 1 +" enable $end
$var wire 1 ] na1_a2 $end
$var wire 1 \ na1_na2 $end
$var wire 1 Z na4_a5 $end
$var wire 1 Y na4_na5 $end
$var wire 1 V strobe $end
$var wire 1 [ na3 $end
$var wire 6 7" inv_address [0:5] $end
$var wire 1 b a3 $end
$upscope $end
$upscope $end
$scope module array0 $end
$var wire 1 8" rd0_a0 $end
$var wire 1 9" rd0_a1 $end
$var wire 1 ~ rd0_a1_a2 $end
$var wire 1 } rd0_a1_na2 $end
$var wire 1 :" rd0_a2 $end
$var wire 1 | rd0_a3 $end
$var wire 1 ;" rd0_a4 $end
$var wire 1 { rd0_a4_a5 $end
$var wire 1 z rd0_a4_na5 $end
$var wire 1 <" rd0_a5 $end
$var wire 1 y rd0_c_a0 $end
$var wire 1 x rd0_c_na0 $end
$var wire 1 =" rd0_enable $end
$var wire 1 w rd0_na1_a2 $end
$var wire 1 v rd0_na1_na2 $end
$var wire 1 u rd0_na3 $end
$var wire 1 t rd0_na4_a5 $end
$var wire 1 s rd0_na4_na5 $end
$var wire 1 >" rd1_a0 $end
$var wire 1 ?" rd1_a1 $end
$var wire 1 r rd1_a1_a2 $end
$var wire 1 q rd1_a1_na2 $end
$var wire 1 @" rd1_a2 $end
$var wire 1 p rd1_a3 $end
$var wire 1 A" rd1_a4 $end
$var wire 1 o rd1_a4_a5 $end
$var wire 1 n rd1_a4_na5 $end
$var wire 1 B" rd1_a5 $end
$var wire 1 m rd1_c_a0 $end
$var wire 1 l rd1_c_na0 $end
$var wire 1 C" rd1_enable $end
$var wire 1 k rd1_na1_a2 $end
$var wire 1 j rd1_na1_na2 $end
$var wire 1 i rd1_na3 $end
$var wire 1 h rd1_na4_a5 $end
$var wire 1 g rd1_na4_na5 $end
$var wire 1 D" wr0_a0 $end
$var wire 1 E" wr0_a1 $end
$var wire 1 d wr0_a1_a2 $end
$var wire 1 c wr0_a1_na2 $end
$var wire 1 F" wr0_a2 $end
$var wire 1 b wr0_a3 $end
$var wire 1 G" wr0_a4 $end
$var wire 1 a wr0_a4_a5 $end
$var wire 1 ` wr0_a4_na5 $end
$var wire 1 H" wr0_a5 $end
$var wire 1 _ wr0_c_a0 $end
$var wire 1 ^ wr0_c_na0 $end
$var wire 24 I" wr0_dat [0:23] $end
$var wire 1 J" wr0_enable $end
$var wire 1 ] wr0_na1_a2 $end
$var wire 1 \ wr0_na1_na2 $end
$var wire 1 [ wr0_na3 $end
$var wire 1 Z wr0_na4_a5 $end
$var wire 1 Y wr0_na4_na5 $end
$var wire 24 K" rd1_dat [0:23] $end
$var wire 24 L" rd0_dat [0:23] $end
$upscope $end
$scope module array1 $end
$var wire 1 M" rd0_a0 $end
$var wire 1 N" rd0_a1 $end
$var wire 1 ~ rd0_a1_a2 $end
$var wire 1 } rd0_a1_na2 $end
$var wire 1 O" rd0_a2 $end
$var wire 1 | rd0_a3 $end
$var wire 1 P" rd0_a4 $end
$var wire 1 { rd0_a4_a5 $end
$var wire 1 z rd0_a4_na5 $end
$var wire 1 Q" rd0_a5 $end
$var wire 1 y rd0_c_a0 $end
$var wire 1 x rd0_c_na0 $end
$var wire 1 R" rd0_enable $end
$var wire 1 w rd0_na1_a2 $end
$var wire 1 v rd0_na1_na2 $end
$var wire 1 u rd0_na3 $end
$var wire 1 t rd0_na4_a5 $end
$var wire 1 s rd0_na4_na5 $end
$var wire 1 S" rd1_a0 $end
$var wire 1 T" rd1_a1 $end
$var wire 1 r rd1_a1_a2 $end
$var wire 1 q rd1_a1_na2 $end
$var wire 1 U" rd1_a2 $end
$var wire 1 p rd1_a3 $end
$var wire 1 V" rd1_a4 $end
$var wire 1 o rd1_a4_a5 $end
$var wire 1 n rd1_a4_na5 $end
$var wire 1 W" rd1_a5 $end
$var wire 1 m rd1_c_a0 $end
$var wire 1 l rd1_c_na0 $end
$var wire 1 X" rd1_enable $end
$var wire 1 k rd1_na1_a2 $end
$var wire 1 j rd1_na1_na2 $end
$var wire 1 i rd1_na3 $end
$var wire 1 h rd1_na4_a5 $end
$var wire 1 g rd1_na4_na5 $end
$var wire 1 Y" wr0_a0 $end
$var wire 1 Z" wr0_a1 $end
$var wire 1 d wr0_a1_a2 $end
$var wire 1 c wr0_a1_na2 $end
$var wire 1 [" wr0_a2 $end
$var wire 1 b wr0_a3 $end
$var wire 1 \" wr0_a4 $end
$var wire 1 a wr0_a4_a5 $end
$var wire 1 ` wr0_a4_na5 $end
$var wire 1 ]" wr0_a5 $end
$var wire 1 _ wr0_c_a0 $end
$var wire 1 ^ wr0_c_na0 $end
$var wire 24 ^" wr0_dat [0:23] $end
$var wire 1 _" wr0_enable $end
$var wire 1 ] wr0_na1_a2 $end
$var wire 1 \ wr0_na1_na2 $end
$var wire 1 [ wr0_na3 $end
$var wire 1 Z wr0_na4_a5 $end
$var wire 1 Y wr0_na4_na5 $end
$var wire 24 `" rd1_dat [0:23] $end
$var wire 24 a" rd0_dat [0:23] $end
$upscope $end
$scope module array2 $end
$var wire 1 b" rd0_a0 $end
$var wire 1 c" rd0_a1 $end
$var wire 1 ~ rd0_a1_a2 $end
$var wire 1 } rd0_a1_na2 $end
$var wire 1 d" rd0_a2 $end
$var wire 1 | rd0_a3 $end
$var wire 1 e" rd0_a4 $end
$var wire 1 { rd0_a4_a5 $end
$var wire 1 z rd0_a4_na5 $end
$var wire 1 f" rd0_a5 $end
$var wire 1 y rd0_c_a0 $end
$var wire 1 x rd0_c_na0 $end
$var wire 1 g" rd0_enable $end
$var wire 1 w rd0_na1_a2 $end
$var wire 1 v rd0_na1_na2 $end
$var wire 1 u rd0_na3 $end
$var wire 1 t rd0_na4_a5 $end
$var wire 1 s rd0_na4_na5 $end
$var wire 1 h" rd1_a0 $end
$var wire 1 i" rd1_a1 $end
$var wire 1 r rd1_a1_a2 $end
$var wire 1 q rd1_a1_na2 $end
$var wire 1 j" rd1_a2 $end
$var wire 1 p rd1_a3 $end
$var wire 1 k" rd1_a4 $end
$var wire 1 o rd1_a4_a5 $end
$var wire 1 n rd1_a4_na5 $end
$var wire 1 l" rd1_a5 $end
$var wire 1 m rd1_c_a0 $end
$var wire 1 l rd1_c_na0 $end
$var wire 1 m" rd1_enable $end
$var wire 1 k rd1_na1_a2 $end
$var wire 1 j rd1_na1_na2 $end
$var wire 1 i rd1_na3 $end
$var wire 1 h rd1_na4_a5 $end
$var wire 1 g rd1_na4_na5 $end
$var wire 1 n" wr0_a0 $end
$var wire 1 o" wr0_a1 $end
$var wire 1 d wr0_a1_a2 $end
$var wire 1 c wr0_a1_na2 $end
$var wire 1 p" wr0_a2 $end
$var wire 1 b wr0_a3 $end
$var wire 1 q" wr0_a4 $end
$var wire 1 a wr0_a4_a5 $end
$var wire 1 ` wr0_a4_na5 $end
$var wire 1 r" wr0_a5 $end
$var wire 1 _ wr0_c_a0 $end
$var wire 1 ^ wr0_c_na0 $end
$var wire 24 s" wr0_dat [0:23] $end
$var wire 1 t" wr0_enable $end
$var wire 1 ] wr0_na1_a2 $end
$var wire 1 \ wr0_na1_na2 $end
$var wire 1 [ wr0_na3 $end
$var wire 1 Z wr0_na4_a5 $end
$var wire 1 Y wr0_na4_na5 $end
$var wire 24 u" rd1_dat [0:23] $end
$var wire 24 v" rd0_dat [0:23] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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