no drc errors, irsim looks ok
Bill Flynn
2 years ago
committed by
GitHub
parent
0b8ef24da7
commit
d8fc873c0a
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# magic -rcfile magic.tcl
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source ../magic/.magic_tech/.magicrc
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# openwrapper for non-cmdline
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set cmdline 0
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if {[catch {openwrapper}]} {
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set cmdline 1
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}
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gds read toysram_bit.gds
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load toysram_bit
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# quit if commandline
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if {$cmdline} {
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quit
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}
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# magic -rcfile magic.tcl
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source ../magic/.magic_tech/.magicrc
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# openwrapper for non-cmdline
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set cmdline 0
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if {[catch {openwrapper}]} {
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set cmdline 1
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}
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gds read toysram_bit.gds
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load toysram_bit
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select
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# create toysram_bit.ext
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extract cell toysram_bit
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# create toysram_bit.spice
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ext2spice scale off
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ext2spice -F -f ngspice
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# create toysram_bit.sim
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ext2sim -R -C
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# quit if commandline
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if {$cmdline} {
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quit
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}
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# magic -rcfile magic.tcl
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source ../magic/.magic_tech/.magicrc
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# openwrapper for non-cmdline
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set cmdline 0
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if {[catch {openwrapper}]} {
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set cmdline 1
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}
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gds read toysram_bit.gds
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load toysram_bit
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irsim $PDK_ROOT/sky130A/libs.tech/irsim/sky130A_1v98_27.prm toysram_bit.sim
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h VDD
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l GND_0
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l GND_1
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ana inv1_q inv2_q WWL WBL WBLb RWL0 RBL0 RWL1 RBL1
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h RWL0
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h RWL1
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s 100
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# write 1
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h WWL
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h WBL
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l WBLb
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# RBL's are floating except when pulled to 0 - force/release
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u RBL0
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u RBL1
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s 10
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x RBL0
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x RBL1
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s 10
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s 100
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s 100
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l WWL
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s 100
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# write 0
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h WWL
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l WBL
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h WBLb
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# RBL's are floating except when pulled to 0 - force/release
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u RBL0
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u RBL1
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s 10
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x RBL0
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x RBL1
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s 10
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s 100
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s 100
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l WWL
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s 100
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# write 1
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h WWL
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h WBL
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l WBLb
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# RBL's are floating except when pulled to 0 - force/release
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u RBL0
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u RBL1
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s 10
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x RBL0
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x RBL1
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s 10
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s 100
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s 100
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l WWL
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s 100
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# disable rwl's
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l RWL0
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l RWL1
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# RBL's are floating except when pulled to 0 - force/release
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u RBL0
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u RBL1
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s 10
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x RBL0
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x RBL1
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s 10
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s 100
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# quit if commandline
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if {$cmdline} {
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quit
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}
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# magic -dnull -noconsole -rcfile magicdrc_bit.tcl toysram_bit.gds
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# magic -rcfile magicdrc_bit.tcl toysram_bit.gds
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source ../magic/.magic_tech/.magicrc
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# openwrapper for non-cmdline
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set cmdline 0
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if {[catch {openwrapper}]} {
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set cmdline 1
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}
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# check drc
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gds read toysram_bit.gds
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load toysram_bit
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# for some reason these don't return values; just puts
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drc catchup
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drc statistics
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drc count total
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# console sees errors (drc count) but doesn't show why until manually 'select more' again
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select more
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drc why
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# quit if commandline
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if {$cmdline} {
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quit
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}
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timestamp 1400616048
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version 8.3
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tech sky130A
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style ngspice()
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scale 1000 1 500000
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resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
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parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
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parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
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port "RBL1" 11 644 22 644 22 m1
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port "WBLb" 9 196 22 196 22 m1
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port "RWL1" 15 899 90 933 124 m2
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port "GND_1" 6 672 221 672 221 m1
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port "VDD" 5 408 221 408 221 m1
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port "GND_0" 4 196 221 196 221 m1
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port "inv1_q" 7 126 175 126 175 li
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port "inv2_q" 3 196 333 196 333 li
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port "RWL0" 13 899 382 933 416 m2
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port "RBL0" 10 644 412 644 412 m1
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port "WWL" 8 0 384 0 384 m2
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port "WBL" 2 196 412 196 412 m1
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node "RBL1" 189 87.5434 644 22 m1 0 0 0 0 0 0 0 0 10836 424 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 12376 500 0 0 0 0 0 0 0 0 0 0
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node "WBLb" 144 101.825 196 22 m1 0 0 0 0 0 0 0 0 8820 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 13328 528 0 0 0 0 0 0 0 0 0 0
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node "RWL1" 482 250.377 899 90 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11704 744 0 0 4624 272 4624 272 4624 272 0 0 0 0 0 0 0 0
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node "a_672_120#" 213 0 672 120 ndif 0 0 0 0 0 0 0 0 8946 394 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "GND_1" 236 62.2221 672 221 m1 0 0 0 0 0 0 0 0 8568 388 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 18904 692 0 0 0 0 0 0 0 0 0 0
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node "VDD" 256 55.6586 408 221 m1 0 0 0 0 0 0 0 0 0 0 5712 304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 10540 446 0 0 0 0 0 0 0 0 0 0
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node "GND_0" 186 22.8207 196 221 m1 0 0 0 0 0 0 0 0 6664 332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 10472 444 0 0 0 0 0 0 0 0 0 0
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node "a_672_319#" 240 0 672 319 ndif 0 0 0 0 0 0 0 0 7938 378 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "inv1_q" 1824 366.094 126 175 li 0 0 0 0 0 0 0 0 6958 338 4956 286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24544 1600 0 0 22202 1306 0 0 0 0 0 0 0 0 0 0 0 0
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node "inv2_q" 1733 320.375 196 333 li 0 0 0 0 0 0 0 0 6174 322 5460 298 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22984 1496 0 0 21998 1294 0 0 0 0 0 0 0 0 0 0 0 0
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node "RWL0" 482 248.922 899 382 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11704 744 0 0 4624 272 4624 272 4624 272 0 0 0 0 0 0 0 0
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node "RBL0" 249 87.1885 644 412 m1 0 0 0 0 0 0 0 0 8064 380 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 12376 500 0 0 0 0 0 0 0 0 0 0
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node "WWL" 1419 687.379 0 384 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29048 1864 0 0 9248 544 9248 544 27608 948 0 0 0 0 0 0 0 0
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node "WBL" 186 79.5418 196 412 m1 0 0 0 0 0 0 0 0 6664 332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4624 272 11424 472 0 0 0 0 0 0 0 0 0 0
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node "w_420_92#" 1877 167.328 420 92 nw 0 0 0 0 55776 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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cap "WWL" "GND_1" 0.595193
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cap "GND_1" "inv1_q" 6.63401
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cap "RWL1" "a_672_120#" 2.86675
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cap "WBL" "GND_0" 46.2
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cap "inv2_q" "a_672_120#" 1.35302
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cap "w_420_92#" "GND_0" 1.09829
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cap "VDD" "w_420_92#" 10.2978
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cap "a_672_319#" "inv2_q" 3.30277
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cap "RWL1" "inv2_q" 12.8835
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cap "WBL" "RWL0" 0.250236
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cap "w_420_92#" "RWL0" 3.24793
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cap "GND_0" "WBLb" 43.3786
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cap "RBL0" "inv1_q" 4.50285
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cap "WWL" "RBL0" 0.465371
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cap "w_420_92#" "GND_1" 0.403507
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cap "RBL1" "WBLb" 15.9153
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cap "WWL" "a_672_120#" 1.38033
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cap "inv1_q" "a_672_120#" 1.58011
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cap "WWL" "a_672_319#" 0.744559
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cap "VDD" "GND_0" 58.3334
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cap "RWL1" "inv1_q" 0.888276
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cap "WWL" "RWL1" 12.992
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cap "inv1_q" "inv2_q" 219.557
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cap "WWL" "inv2_q" 63.2312
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cap "WBL" "RBL0" 14.7382
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cap "w_420_92#" "RBL0" 1.22486
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cap "RWL0" "RBL1" 0.179849
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cap "VDD" "GND_1" 23.0202
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cap "RBL1" "GND_1" 57.913
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cap "w_420_92#" "RWL1" 3.60183
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cap "WBL" "inv2_q" 58.88
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cap "RWL0" "GND_1" 46.2272
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cap "w_420_92#" "inv2_q" 12.8288
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cap "WWL" "inv1_q" 133.688
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cap "RWL1" "WBLb" 0.250411
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cap "WBLb" "inv2_q" 3.39991
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cap "RBL0" "RBL1" 3.2087
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cap "RBL0" "RWL0" 31.2871
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cap "WBL" "inv1_q" 2.83011
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cap "WBL" "WWL" 34.6896
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cap "w_420_92#" "WWL" 6.65585
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cap "w_420_92#" "inv1_q" 6.15947
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cap "RBL1" "a_672_120#" 7.22417
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cap "RBL0" "GND_1" 61.6797
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cap "GND_0" "inv2_q" 65.7033
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cap "VDD" "inv2_q" 116.878
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cap "GND_1" "a_672_120#" 7.22417
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cap "RWL0" "a_672_319#" 2.3207
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cap "RBL1" "RWL1" 26.7591
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cap "WBLb" "inv1_q" 56.8646
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cap "WWL" "WBLb" 8.81492
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cap "RBL1" "inv2_q" 4.72409
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cap "RWL0" "RWL1" 29.2937
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cap "RWL0" "inv2_q" 1.56669
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cap "a_672_319#" "GND_1" 6.47498
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cap "RWL1" "GND_1" 44.0225
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cap "w_420_92#" "WBL" 1.22486
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cap "GND_1" "inv2_q" 42.1495
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cap "WWL" "GND_0" 11.9395
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cap "GND_0" "inv1_q" 96.0803
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cap "VDD" "WWL" 1.45842
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cap "VDD" "inv1_q" 61.373
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cap "WBL" "WBLb" 1.60435
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cap "RBL1" "inv1_q" 0.291813
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cap "RBL0" "a_672_319#" 6.47498
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cap "RWL0" "inv1_q" 14.0317
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cap "WWL" "RWL0" 12.2666
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cap "RBL0" "RWL1" 0.179849
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cap "RBL0" "inv2_q" 0.45908
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device msubckt sky130_fd_pr__nfet_01v8 672 90 673 91 l=30 w=126 "VSUBS" "RWL1" 60 0 "RBL1" 126 10836,424 "a_672_120#" 126 4473,197
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device msubckt sky130_fd_pr__nfet_01v8 224 90 225 91 l=30 w=98 "VSUBS" "WWL" 60 0 "WBLb" 98 8820,376 "inv1_q" 98 3479,169
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device msubckt sky130_fd_pr__nfet_01v8 672 191 673 192 l=30 w=126 "VSUBS" "inv2_q" 60 0 "a_672_120#" 126 4473,197 "GND_1" 126 4284,194
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device msubckt sky130_fd_pr__pfet_01v8 462 191 463 192 l=30 w=84 "w_420_92#" "inv2_q" 60 0 "inv1_q" 84 4956,286 "VDD" 84 2856,152
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device msubckt sky130_fd_pr__nfet_01v8 224 191 225 192 l=30 w=98 "VSUBS" "inv2_q" 60 0 "inv1_q" 98 3479,169 "GND_0" 98 3332,166
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device msubckt sky130_fd_pr__nfet_01v8 672 289 673 290 l=30 w=126 "VSUBS" "inv1_q" 60 0 "GND_1" 126 4284,194 "a_672_319#" 126 3969,189
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device msubckt sky130_fd_pr__pfet_01v8 462 289 463 290 l=30 w=84 "w_420_92#" "inv1_q" 60 0 "VDD" 84 2856,152 "inv2_q" 84 5460,298
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device msubckt sky130_fd_pr__nfet_01v8 224 289 225 290 l=30 w=98 "VSUBS" "inv1_q" 60 0 "GND_0" 98 3332,166 "inv2_q" 98 3087,161
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device msubckt sky130_fd_pr__nfet_01v8 672 382 673 383 l=30 w=126 "VSUBS" "RWL0" 60 0 "a_672_319#" 126 3969,189 "RBL0" 126 8064,380
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device msubckt sky130_fd_pr__nfet_01v8 224 382 225 383 l=30 w=98 "VSUBS" "WWL" 60 0 "inv2_q" 98 3087,161 "WBL" 98 6664,332
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| units: 500000 tech: sky130A format: MIT
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x inv1_q VDD inv2_q w_420_92# s=2856,152 d=5460,298 l=30 w=84 x=462 y=289 sky130_fd_pr__pfet_01v8
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x inv1_q GND_0 inv2_q VSUBS s=3332,166 d=3087,161 l=30 w=98 x=224 y=289 sky130_fd_pr__nfet_01v8
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x RWL1 RBL1 a_672_120# VSUBS s=10836,424 d=4473,197 l=30 w=126 x=672 y=90 sky130_fd_pr__nfet_01v8
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x WWL WBLb inv1_q VSUBS s=8820,376 d=3479,169 l=30 w=98 x=224 y=90 sky130_fd_pr__nfet_01v8
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x inv2_q inv1_q VDD w_420_92# s=4956,286 d=2856,152 l=30 w=84 x=462 y=191 sky130_fd_pr__pfet_01v8
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x inv1_q GND_1 a_672_319# VSUBS s=4284,194 d=3969,189 l=30 w=126 x=672 y=289 sky130_fd_pr__nfet_01v8
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x inv2_q inv1_q GND_0 VSUBS s=3479,169 d=3332,166 l=30 w=98 x=224 y=191 sky130_fd_pr__nfet_01v8
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x WWL inv2_q WBL VSUBS s=3087,161 d=6664,332 l=30 w=98 x=224 y=382 sky130_fd_pr__nfet_01v8
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x inv2_q a_672_120# GND_1 VSUBS s=4473,197 d=4284,194 l=30 w=126 x=672 y=191 sky130_fd_pr__nfet_01v8
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x RWL0 a_672_319# RBL0 VSUBS s=3969,189 d=8064,380 l=30 w=126 x=672 y=382 sky130_fd_pr__nfet_01v8
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* NGSPICE file created from toysram_bit.ext - technology: sky130A
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.subckt toysram_bit WBL inv2_q GND_0 VDD GND_1 inv1_q WWL WBLb RBL0 RBL1 RWL0 RWL1
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X0 inv2_q inv1_q VDD w_420_92# sky130_fd_pr__pfet_01v8 ad=0.137 pd=1.49 as=0.0714 ps=0.76 w=0.42 l=0.15
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X1 inv2_q inv1_q GND_0 VSUBS sky130_fd_pr__nfet_01v8 ad=0.0772 pd=0.805 as=0.0833 ps=0.83 w=0.49 l=0.15
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X2 a_672_120# RWL1 RBL1 VSUBS sky130_fd_pr__nfet_01v8 ad=0.112 pd=0.985 as=0.271 ps=2.12 w=0.63 l=0.15
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X3 inv1_q WWL WBLb VSUBS sky130_fd_pr__nfet_01v8 ad=0.087 pd=0.845 as=0.221 ps=1.88 w=0.49 l=0.15
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X4 VDD inv2_q inv1_q w_420_92# sky130_fd_pr__pfet_01v8 ad=0.0714 pd=0.76 as=0.124 ps=1.43 w=0.42 l=0.15
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X5 a_672_319# inv1_q GND_1 VSUBS sky130_fd_pr__nfet_01v8 ad=0.0992 pd=0.945 as=0.107 ps=0.97 w=0.63 l=0.15
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X6 GND_0 inv2_q inv1_q VSUBS sky130_fd_pr__nfet_01v8 ad=0.0833 pd=0.83 as=0.087 ps=0.845 w=0.49 l=0.15
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X7 WBL WWL inv2_q VSUBS sky130_fd_pr__nfet_01v8 ad=0.167 pd=1.66 as=0.0772 ps=0.805 w=0.49 l=0.15
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X8 GND_1 inv2_q a_672_120# VSUBS sky130_fd_pr__nfet_01v8 ad=0.107 pd=0.97 as=0.112 ps=0.985 w=0.63 l=0.15
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X9 RBL0 RWL0 a_672_319# VSUBS sky130_fd_pr__nfet_01v8 ad=0.202 pd=1.9 as=0.0992 ps=0.945 w=0.63 l=0.15
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.ends
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