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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
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// repository except in compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
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// the work of authorship in physical form.
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//
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// Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
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// governing permissions and limitations under the License.
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//
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// Brief explanation of modifications:
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//
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// Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
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// it unambiguously permits a user to make and use the physical chip.
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// Behavioral for 16x12 toysram subarray
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`timescale 1 ps / 1 ps
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module toysram_16x12 (
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input [0:15] RWL0,
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input [0:15] RWL1,
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input [0:15] WWL,
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output [0:11] RBL0,
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output [0:11] RBL1,
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input [0:11] WBL,
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input [0:11] WBLb,
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);
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reg [0:11] mem[0:15];
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for (i = 0; i < 15; i = i + 1) begin
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always @(posedge WWL[i]) begin
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mem[i] <= not WBLb; // 00=1 01=0 10=1 11=0
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end
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end
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// word-select
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assign RBL0 = (mem[0] and {12{RWL0[0]}}) |
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(mem[1] and {12{RWL0[1]}}) |
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(mem[2] and {12{RWL0[2]}}) |
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(mem[3] and {12{RWL0[3]}}) |
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(mem[4] and {12{RWL0[4]}}) |
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(mem[5] and {12{RWL0[5]}}) |
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(mem[6] and {12{RWL0[6]}}) |
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(mem[7] and {12{RWL0[7]}}) |
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(mem[8] and {12{RWL0[8]}}) |
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(mem[9] and {12{RWL0[9]}}) |
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(mem[10] and {12{RWL0[10]}}) |
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(mem[11] and {12{RWL0[11]}}) |
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(mem[12] and {12{RWL0[12]}}) |
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(mem[13] and {12{RWL0[13]}}) |
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(mem[14] and {12{RWL0[14]}}) |
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(mem[15] and {12{RWL0[15]}});
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assign RBL1 = (mem[0] and {12{RWL1[0]}}) |
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(mem[1] and {12{RWL1[1]}}) |
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(mem[2] and {12{RWL1[2]}}) |
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(mem[3] and {12{RWL1[3]}}) |
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(mem[4] and {12{RWL1[4]}}) |
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(mem[5] and {12{RWL1[5]}}) |
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(mem[6] and {12{RWL1[6]}}) |
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(mem[7] and {12{RWL1[7]}}) |
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(mem[8] and {12{RWL1[8]}}) |
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(mem[9] and {12{RWL1[9]}}) |
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(mem[10] and {12{RWL1[10]}}) |
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(mem[11] and {12{RWL1[11]}}) |
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(mem[12] and {12{RWL1[12]}}) |
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(mem[13] and {12{RWL1[13]}}) |
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(mem[14] and {12{RWL1[14]}}) |
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(mem[15] and {12{RWL1[15]}});
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endmodule
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