# sdr ra
# make -f Makefile.icarus build  # rebuild and sim and fst
# make -f Makefile.icarus run    # sim and fst
# make -f Makefile.icarus        # sim

#COCOTB_LOG_LEVEL=DEBUG
#GPI_EXTRA=vpi

#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM

#SIM_BUILD ?= build
SIM ?= icarus

# options
#COCOTB_HDL_TIMEUNIT ?= 1ns
#COCOTB_HDL_TIMEPRECISION ?= 1ps
#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM

# icarus
#
VERILOG_COMMON = src/array
VERILOG_ROOT = src/array_shard

# CFGINIT
# only no delay works as-is in cycle sim
# 00000000 : disable delay
# 00000001 : enable delay, sdr
# 00000003 : enable delay, ddr
#
#COMPILE_ARGS = -y$(VERILOG_ROOT) -y$(VERILOG_COMMON) -DGENMODE=1 -DCFGINIT=1
COMPILE_ARGS = -y$(VERILOG_ROOT) -y$(VERILOG_COMMON) -DGENMODE=1

# other options

# rtl
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = ./tb_ra_64x72_2r1w.v $(VERILOG_ROOT)/sky130_hd.v
TOPLEVEL = tb_ra_64x72_2r1w

# python test
MODULE = tb_ra_64x72
TESTCASE = tb

# cocotb make rules
include $(shell cocotb-config --makefiles)/Makefile.sim

build: clean sim fst

run: sim fst

fst:
	vcd2fst tb_ra_64x72.vcd tb_ra_64x72.fst
	rm tb_ra_64x72.vcd
