## Logical Array Wrapper

* verilog is in rtl/src/array
* parameter determines sim vs tech during rtl compile

## Physical Array

* custom cell(s) to be designed
* custom/

## Test Site

* verilog is in rtl/src/site
* supporting logic for test and debug through available Caravel connections

## Verification

* rtl/sim/coco

## Caravel

* to be incorporated into https://github.com/efabless/caravel flow as a user project area
