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129 lines
4.4 KiB
Python
129 lines
4.4 KiB
Python
from amaranth import *
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from amaranth.asserts import *
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from .. import PowerFVCheck
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from ... import pfv, tb
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from ._fmt import *
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from ._insn import *
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__all__ = ["CRSpec", "CRCheck"]
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class CRSpec(Elaboratable):
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def __init__(self, insn_cls, post):
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self.insn_cls = insn_cls
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self.pfv = pfv.Interface()
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self.post = tb.Trigger(cycle=post)
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def triggers(self):
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yield self.post
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def elaborate(self, platform):
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m = Module()
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spec_insn = self.insn_cls()
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with m.If(self.post.stb):
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m.d.sync += [
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Assume(self.pfv.stb),
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Assume(self.pfv.insn[32:] == spec_insn),
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]
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# CR
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spec_cr_r_stb = Signal(8)
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spec_cr_w_stb = Signal(8)
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spec_cr_w_data = Signal(32)
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if isinstance(spec_insn, Instruction_XL_crl):
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ba_r_field = Signal(4)
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bb_r_field = Signal(4)
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bt_r_field = Signal(4)
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ba_r_bit = Signal()
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bb_r_bit = Signal()
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bt_w_bit = Signal()
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m.d.comb += [
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ba_r_field.eq(self.pfv.cr.r_data[::-1].word_select(spec_insn.ba[2:], width=4)),
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bb_r_field.eq(self.pfv.cr.r_data[::-1].word_select(spec_insn.bb[2:], width=4)),
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bt_r_field.eq(self.pfv.cr.r_data[::-1].word_select(spec_insn.bt[2:], width=4)),
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ba_r_bit.eq(ba_r_field.bit_select(spec_insn.ba[:2], width=1)),
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bb_r_bit.eq(bb_r_field.bit_select(spec_insn.bb[:2], width=1)),
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]
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if isinstance(spec_insn, CRAND):
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m.d.comb += bt_w_bit.eq(ba_r_bit & bb_r_bit)
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elif isinstance(spec_insn, CROR):
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m.d.comb += bt_w_bit.eq(ba_r_bit | bb_r_bit)
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elif isinstance(spec_insn, CRNAND):
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m.d.comb += bt_w_bit.eq(~(ba_r_bit & bb_r_bit))
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elif isinstance(spec_insn, CRXOR):
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m.d.comb += bt_w_bit.eq(ba_r_bit ^ bb_r_bit)
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elif isinstance(spec_insn, CRNOR):
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m.d.comb += bt_w_bit.eq(~(ba_r_bit | bb_r_bit))
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elif isinstance(spec_insn, CRANDC):
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m.d.comb += bt_w_bit.eq(ba_r_bit & ~bb_r_bit)
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elif isinstance(spec_insn, CREQV):
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m.d.comb += bt_w_bit.eq(ba_r_bit == bb_r_bit)
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elif isinstance(spec_insn, CRORC):
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m.d.comb += bt_w_bit.eq(ba_r_bit | ~bb_r_bit)
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else:
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assert False
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spec_bt_w_field = Signal(4)
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for i, spec_bt_w_bit in enumerate(spec_bt_w_field):
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bt_r_bit = bt_r_field[i]
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with m.If(spec_insn.bt[:2] == i):
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m.d.comb += spec_bt_w_bit.eq(bt_w_bit)
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with m.Else():
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m.d.comb += spec_bt_w_bit.eq(bt_r_bit)
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m.d.comb += [
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spec_cr_r_stb[::-1].bit_select(spec_insn.ba[2:], width=1).eq(1),
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spec_cr_r_stb[::-1].bit_select(spec_insn.bb[2:], width=1).eq(1),
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spec_cr_w_stb[::-1].bit_select(spec_insn.bt[2:], width=1).eq(1),
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spec_cr_w_data[::-1].eq(Repl(spec_bt_w_field, 8))
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]
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elif isinstance(spec_insn, MCRF):
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bfa_r_field = Signal(4)
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m.d.comb += [
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bfa_r_field.eq(self.pfv.cr.r_data[::-1].word_select(spec_insn.bfa, width=4)),
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spec_cr_r_stb[::-1].bit_select(spec_insn.bfa, width=1).eq(1),
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spec_cr_w_stb[::-1].bit_select(spec_insn.bf, width=1).eq(1),
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spec_cr_w_data[::-1].eq(Repl(bfa_r_field, 8)),
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]
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else:
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assert False
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with m.If(self.post.stb & ~self.pfv.intr):
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for i in range(8):
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spec_cr_w_field = spec_cr_w_data .word_select(i, width=4)
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pfv_cr_w_field = self.pfv.cr.w_data.word_select(i, width=4)
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m.d.sync += [
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Assert(spec_cr_r_stb[i].implies(self.pfv.cr.r_stb[i])),
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Assert(self.pfv.cr.w_stb[i] == spec_cr_w_stb[i]),
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Assert(spec_cr_w_stb[i].implies(pfv_cr_w_field == spec_cr_w_field)),
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]
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return m
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class CRCheck(PowerFVCheck, name="_insn_cr"):
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def __init_subclass__(cls, name, insn_cls):
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super().__init_subclass__(name)
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cls.insn_cls = insn_cls
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def get_testbench(self, dut, post):
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tb_spec = CRSpec(self.insn_cls, post)
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tb_top = tb.Testbench(tb_spec, dut)
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return tb_top
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