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112 lines
3.9 KiB
Python
112 lines
3.9 KiB
Python
from amaranth import *
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from amaranth.build import *
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from amaranth.lib.cdc import ResetSynchronizer
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from power_fv.check import PowerFVCheck
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__all__ = ["SymbiYosysPlatform"]
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class SymbiYosysPlatform(TemplatedPlatform):
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"""
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Required tools:
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* ``yosys``
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* ``sby``
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Required tools for VHDL support (experimental):
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* ``ghdl``
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* ``ghdl-yosys-plugin``
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Available overrides:
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* ``sby_opts``: adds extra options for sby (default: "-f").
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* ``sby_depth``: depth of the bounded model check in sby script.
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* ``sby_skip``: number of skipped time steps in sby script.
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* ``read_verilog_opts``: adds options for the ``read_verilog`` Yosys command.
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* ``ghdl_opts``: adds options for the ``ghdl`` Yosys command.
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* ``ghdl_top``: Top-level unit for the ``ghdl`` Yosys command (default: "top").
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* ``prep_opts``: adds options for the ``prep`` Yosys command (default: "-flatten -nordff").
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* ``script_before_read``: inserts commands before reading input files in Yosys script.
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* ``script_after_read``: inserts command after reading input files in Yosys script.
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* ``script_after_synth``: inserts command after ``prep`` in Yosys script.
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Build products:
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(TODO)
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"""
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toolchain = "oss-cad-suite"
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required_tools = [
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"yosys",
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"sby",
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]
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.il": r"""
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# {{autogenerated}}
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{{emit_rtlil()}}
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""",
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"{{name}}.sby": r"""
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# {{autogenerated}}
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[options]
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mode {{get_override("mode")|default("bmc")}}
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expect pass,fail
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append 0
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depth {{get_override("depth")}}
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skip {{get_override("skip")}}
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[engines]
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smtbmc boolector
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[files]
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{% for file in platform.iter_files(".il", ".v", ".sv", ".vhdl") -%}
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{{file}}
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{% endfor %}
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{{name}}.il
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[script]
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{% if platform.iter_files(".vhdl")|first is defined -%}
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plugin -i ghdl
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{% endif %}
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{{get_override("script_before_read")|default("# (script_before_read placeholder)")}}
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{% for file in platform.iter_files(".il") -%}
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read_ilang {{file}}
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{% endfor %}
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{% for file in platform.iter_files(".v", ".sv") -%}
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read_verilog {{get_override("read_verilog_opts")|default("-sv")}} {{file}}
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{% endfor %}
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{% if platform.iter_files(".vhdl")|first is defined -%}
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ghdl {{get_override("ghdl_opts")|options}} {{platform.iter_files(".vhdl")|join(" ")}} -e {{get_override("ghdl_top")|default("toplevel")}}
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{% endif %}
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read_ilang {{name}}.il
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delete w:$verilog_initial_trigger
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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prep {{get_override("prep_opts")|default("-nordff")}} -top {{name}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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""",
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}
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command_templates = [
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r"""
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{{invoke_tool("sby")}}
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{{get_override("sby_opts")|default("-f")}}
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--yosys={{invoke_tool("yosys")}}
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{{name}}.sby
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""",
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]
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default_clk = "clk"
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resources = [
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Resource("clk", 0, Pins("clk", dir="i"), Clock(1e6)),
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]
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connectors = []
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def create_missing_domain(self, name):
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if name == "sync":
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clk_i = self.request(self.default_clk).i
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rst_i = Const(0)
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m = Module()
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m.domains.sync = ClockDomain("sync")
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m.d.comb += ClockSignal("sync").eq(clk_i)
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m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
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return m
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