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365 lines
14 KiB
Python
365 lines
14 KiB
Python
import os
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import pathlib
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import textwrap
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from amaranth import *
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from amaranth.asserts import *
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from amaranth_soc import wishbone
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from power_fv import pfv
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from power_fv.core import PowerFVCore
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__all__ = ["MicrowattWrapper", "MicrowattCore"]
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class MicrowattWrapper(Elaboratable):
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@classmethod
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def add_check_arguments(cls, parser):
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group = parser.add_argument_group(title="microwatt options")
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group.add_argument(
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"--bus-fairness", action="store_true",
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help="add bus fairness constraints")
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group.add_argument(
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"--ex1-bypass", choices=("true","false"), default="true",
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help="(default: %(default)s)")
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group.add_argument(
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"--has-btc", choices=("true","false"), default="true",
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help="(default: %(default)s)")
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group.add_argument(
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"--icache-num-lines", type=int, default=2,
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help="(default: %(default)s)")
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group.add_argument(
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"--icache-num-ways", type=int, default=1,
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help="(default: %(default)s)")
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group.add_argument(
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"--icache-tlb-size", type=int, default=1,
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help="(default: %(default)s)")
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group.add_argument(
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"--dcache-num-lines", type=int, default=2,
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help="(default: %(default)s)")
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group.add_argument(
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"--dcache-num-ways", type=int, default=1,
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help="(default: %(default)s)")
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group.add_argument(
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"--dcache-tlb-set-size", type=int, default=1,
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help="(default: %(default)s)")
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group.add_argument(
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"--dcache-tlb-num-ways", type=int, default=1,
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help="(default: %(default)s)")
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# ghdl-yosys-plugin doesn't yet support setting instance parameters from outside VHDL
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# (see upstream issue 136).
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# As a workaround, we use a template to generate a VHDL toplevel at build-time, which
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# is instantiated in .elaborate().
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MICROWATT_TOPLEVEL = textwrap.dedent(r"""
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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use work.powerfv_types.all;
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entity toplevel is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Alternate reset (0xffff0000) for use by DRAM init fw
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alt_reset : in std_ulogic;
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-- Wishbone interface
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wishbone_insn_in : in wishbone_slave_out;
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wishbone_insn_out : out wishbone_master_out;
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wishbone_data_in : in wishbone_slave_out;
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wishbone_data_out : out wishbone_master_out;
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wb_snoop_in : in wishbone_master_out;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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ext_irq : in std_ulogic;
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terminated_out : out std_logic;
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pfv_out : out pfv_t
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);
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end entity toplevel;
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architecture behave of toplevel is
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signal pfv : pfv_t;
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begin
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core: entity work.core
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generic map (
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SIM => false,
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DISABLE_FLATTEN => false,
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EX1_BYPASS => {ex1_bypass},
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HAS_FPU => false,
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HAS_BTC => {has_btc},
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HAS_SHORT_MULT => false,
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HAS_POWERFV => true,
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HAS_ALTOPS => true,
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LOG_LENGTH => 0,
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ICACHE_NUM_LINES => {icache_num_lines},
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ICACHE_NUM_WAYS => {icache_num_ways},
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ICACHE_TLB_SIZE => {icache_tlb_size},
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DCACHE_NUM_LINES => {dcache_num_lines},
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DCACHE_NUM_WAYS => {dcache_num_ways},
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DCACHE_TLB_SET_SIZE => {dcache_tlb_set_size},
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DCACHE_TLB_NUM_WAYS => {dcache_tlb_num_ways}
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)
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port map (
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clk => clk,
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rst => rst,
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alt_reset => alt_reset,
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wishbone_insn_in => wishbone_insn_in,
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wishbone_insn_out => wishbone_insn_out,
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wishbone_data_in => wishbone_data_in,
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wishbone_data_out => wishbone_data_out,
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wb_snoop_in => wb_snoop_in,
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dmi_addr => dmi_addr,
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dmi_din => dmi_din,
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dmi_dout => dmi_dout,
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dmi_req => dmi_req,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_ack,
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ext_irq => ext_irq,
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terminated_out => terminated_out,
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pfv_out => pfv_out
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);
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end architecture behave;
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""")
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def __init__(self, *, bus_fairness=False, **kwargs):
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self.pfv = pfv.Interface(mem_alignment=0, illegal_insn_heai=False, muldiv_altops=True)
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self.wb_insn = wishbone.Interface(addr_width=29, data_width=64, granularity=8,
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features=("stall",))
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self.wb_data = wishbone.Interface(addr_width=29, data_width=64, granularity=8,
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features=("stall",))
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def keep_wb_fanout(wb_bus):
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for field_name in ("adr", "dat_w", "sel", "cyc", "stb", "we"):
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wb_bus[field_name].attrs["keep"] = True
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keep_wb_fanout(self.wb_insn)
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keep_wb_fanout(self.wb_data)
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self.bus_fairness = bus_fairness;
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self._toplevel_src = self.MICROWATT_TOPLEVEL.format(**kwargs)
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def elaborate(self, platform):
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m = Module()
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wb_snoop = wishbone.Interface(addr_width=29, data_width=64, granularity=8)
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dmi = Record([
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("addr", unsigned( 4)),
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("din", unsigned(64)),
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("dout", unsigned(64)),
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("req", unsigned( 1)),
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("wr", unsigned( 1)),
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("ack", unsigned( 1)),
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])
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terminated = Signal(attrs={"keep": True})
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dmi.dout.attrs["keep"] = True
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dmi.ack .attrs["keep"] = True
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m.d.comb += [
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self.wb_insn.dat_r.eq(AnySeq(64)),
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self.wb_insn.ack .eq(AnySeq( 1)),
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self.wb_insn.stall.eq(AnySeq( 1)),
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self.wb_data.dat_r.eq(AnySeq(64)),
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self.wb_data.ack .eq(AnySeq( 1)),
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self.wb_data.stall.eq(AnySeq( 1)),
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wb_snoop.adr .eq(AnySeq(29)),
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wb_snoop.dat_w.eq(AnySeq(64)),
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wb_snoop.sel .eq(AnySeq( 8)),
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wb_snoop.cyc .eq(AnySeq( 1)),
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wb_snoop.stb .eq(AnySeq( 1)),
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wb_snoop.we .eq(AnySeq( 1)),
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dmi.addr.eq(AnySeq( 4)),
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dmi.din .eq(AnySeq(64)),
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dmi.req .eq(AnySeq( 1)),
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dmi.wr .eq(AnySeq( 1)),
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]
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m.submodules.dut = Instance("toplevel",
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("i", "clk", ClockSignal()),
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("i", "rst", ResetSignal()),
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("i", "alt_reset", Const(0)),
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("i", "ext_irq", Const(0)),
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("i", "wishbone_insn_in.dat" , self.wb_insn.dat_r),
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("i", "wishbone_insn_in.ack" , self.wb_insn.ack ),
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("i", "wishbone_insn_in.stall", self.wb_insn.stall),
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("o", "wishbone_insn_out.adr" , self.wb_insn.adr ),
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("o", "wishbone_insn_out.dat" , self.wb_insn.dat_w),
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("o", "wishbone_insn_out.sel" , self.wb_insn.sel ),
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("o", "wishbone_insn_out.cyc" , self.wb_insn.cyc ),
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("o", "wishbone_insn_out.stb" , self.wb_insn.stb ),
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("o", "wishbone_insn_out.we" , self.wb_insn.we ),
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("i", "wishbone_data_in.dat" , self.wb_data.dat_r),
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("i", "wishbone_data_in.ack" , self.wb_data.ack ),
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("i", "wishbone_data_in.stall", self.wb_data.stall),
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("o", "wishbone_data_out.adr" , self.wb_data.adr ),
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("o", "wishbone_data_out.dat" , self.wb_data.dat_w),
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("o", "wishbone_data_out.sel" , self.wb_data.sel ),
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("o", "wishbone_data_out.cyc" , self.wb_data.cyc ),
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("o", "wishbone_data_out.stb" , self.wb_data.stb ),
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("o", "wishbone_data_out.we" , self.wb_data.we ),
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("i", "wb_snoop_in.adr", wb_snoop.adr ),
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("i", "wb_snoop_in.dat", wb_snoop.dat_w),
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("i", "wb_snoop_in.sel", wb_snoop.sel ),
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("i", "wb_snoop_in.cyc", wb_snoop.cyc ),
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("i", "wb_snoop_in.stb", wb_snoop.stb ),
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("i", "wb_snoop_in.we" , wb_snoop.we ),
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("i", "dmi_addr", dmi.addr),
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("i", "dmi_din" , dmi.din ),
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("o", "dmi_dout", dmi.dout),
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("i", "dmi_req" , dmi.req ),
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("i", "dmi_wr" , dmi.wr ),
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("o", "dmi_ack" , dmi.ack ),
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("o", "terminated_out", terminated),
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("o", "pfv_out.stb" , self.pfv.stb ),
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("o", "pfv_out.insn" , self.pfv.insn ),
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("o", "pfv_out.order", self.pfv.order),
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("o", "pfv_out.intr" , self.pfv.intr ),
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("o", "pfv_out.cia" , self.pfv.cia ),
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("o", "pfv_out.nia" , self.pfv.nia ),
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("o", "pfv_out.skip" , self.pfv.skip ),
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("o", "pfv_out.ra" , self.pfv.ra ),
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("o", "pfv_out.rb" , self.pfv.rb ),
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("o", "pfv_out.rs" , self.pfv.rs ),
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("o", "pfv_out.rt" , self.pfv.rt ),
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("o", "pfv_out.mem" , self.pfv.mem ),
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("o", "pfv_out.cr" , self.pfv.cr ),
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("o", "pfv_out.msr" , self.pfv.msr ),
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("o", "pfv_out.lr" , self.pfv.lr ),
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("o", "pfv_out.ctr" , self.pfv.ctr ),
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("o", "pfv_out.tar" , self.pfv.tar ),
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("o", "pfv_out.xer" , self.pfv.xer ),
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("o", "pfv_out.srr0" , self.pfv.srr0 ),
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("o", "pfv_out.srr1" , self.pfv.srr1 ),
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)
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m.d.comb += [
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Assume(~dmi.req),
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Assume(~terminated),
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]
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with m.If(self.pfv.stb):
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m.d.comb += [
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# no decrementer interrupts
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Assume(self.pfv.msr.w_mask.ee.implies(~self.pfv.msr.w_data.ee)),
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# no trace interrupts
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Assume(self.pfv.msr.w_mask.te[0].implies(~self.pfv.msr.w_data.te[0])),
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Assume(self.pfv.msr.w_mask.te[1].implies(~self.pfv.msr.w_data.te[1])),
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]
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if self.bus_fairness:
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ibus_wait = Signal(2)
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dbus_wait = Signal(2)
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with m.If(self.wb_insn.cyc & self.wb_insn.stb & ~self.wb_insn.ack):
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m.d.comb += Assume(self.wb_insn.stall)
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m.d.sync += ibus_wait.eq(ibus_wait + 1)
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with m.Else():
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m.d.sync += ibus_wait.eq(0)
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with m.If(self.wb_data.cyc & self.wb_data.stb & ~self.wb_data.ack):
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m.d.comb += Assume(self.wb_data.stall)
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m.d.sync += dbus_wait.eq(dbus_wait + 1)
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with m.Else():
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m.d.sync += dbus_wait.eq(0)
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m.d.comb += [
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Assume((ibus_wait < 2) & (dbus_wait < 2)),
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]
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return m
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class MicrowattCore(PowerFVCore):
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MICROWATT_FILES = (
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"cache_ram.vhdl",
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"common.vhdl",
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"control.vhdl",
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"core_debug.vhdl",
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"core.vhdl",
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"countbits.vhdl",
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"cr_file.vhdl",
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"crhelpers.vhdl",
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"dcache.vhdl",
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"decode1.vhdl",
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"decode2.vhdl",
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"decode_types.vhdl",
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"divider.vhdl",
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"execute1.vhdl",
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"fetch1.vhdl",
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"fpu.vhdl",
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"helpers.vhdl",
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"icache.vhdl",
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"insn_helpers.vhdl",
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"loadstore1.vhdl",
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"logical.vhdl",
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"mmu.vhdl",
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"multiply.vhdl",
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"nonrandom.vhdl",
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"plru.vhdl",
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"pmu.vhdl",
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"powerfv_types.vhdl",
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"powerfv.vhdl",
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"ppc_fx_insns.vhdl",
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"register_file.vhdl",
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"rotator.vhdl",
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"utils.vhdl",
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"wishbone_types.vhdl",
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"writeback.vhdl",
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)
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@classmethod
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def add_check_arguments(cls, parser):
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super().add_check_arguments(parser)
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MicrowattWrapper.add_check_arguments(parser)
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@classmethod
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def wrapper(cls, **kwargs):
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return MicrowattWrapper(**kwargs)
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@classmethod
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def add_build_arguments(cls, parser):
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super().add_build_arguments(parser)
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group = parser.add_argument_group(title="microwatt options")
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group.add_argument(
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"--src-dir", type=pathlib.Path, default=pathlib.Path("./src"),
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help="microwatt directory (default: %(default)s)")
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group.add_argument(
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"--ghdl-opts", type=str, default="--std=08",
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help="ghdl options (default: '%(default)s')")
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@classmethod
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def add_files(cls, platform, wrapper, *, src_dir, **kwargs):
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assert isinstance(wrapper, MicrowattWrapper)
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for filename in cls.MICROWATT_FILES:
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contents = open(os.path.join(src_dir, filename), "r")
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platform.add_file(filename, contents)
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top_filename = "top-powerfv.vhdl"
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top_contents = wrapper._toplevel_src
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platform.add_file(top_filename, top_contents)
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