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114 lines
4.2 KiB
Python
114 lines
4.2 KiB
Python
from amaranth import *
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from amaranth.asserts import *
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from power_fv import pfv
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__all__ = ["MicrowattWrapper"]
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class MicrowattWrapper(Elaboratable):
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def __init__(self):
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self.pfv = pfv.Interface()
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def elaborate(self, platform):
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m = Module()
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wb_insn_dat_r = AnySeq(64)
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wb_insn_ack = AnySeq( 1)
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wb_insn_stall = AnySeq( 1)
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wb_insn_adr = Signal(29, attrs={"keep": True})
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wb_insn_dat_w = Signal(64, attrs={"keep": True})
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wb_insn_sel = Signal( 8, attrs={"keep": True})
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wb_insn_cyc = Signal( attrs={"keep": True})
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wb_insn_stb = Signal( attrs={"keep": True})
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wb_insn_we = Signal( attrs={"keep": True})
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wb_data_dat_r = AnySeq(64)
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wb_data_ack = AnySeq( 1)
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wb_data_stall = AnySeq( 1)
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wb_data_adr = Signal(29, attrs={"keep": True})
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wb_data_dat_w = Signal(64, attrs={"keep": True})
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wb_data_sel = Signal( 8, attrs={"keep": True})
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wb_data_cyc = Signal( 1, attrs={"keep": True})
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wb_data_stb = Signal( 1, attrs={"keep": True})
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wb_data_we = Signal( 1, attrs={"keep": True})
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wb_snoop_adr = AnySeq(29)
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wb_snoop_dat_w = AnySeq(64)
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wb_snoop_sel = AnySeq( 8)
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wb_snoop_cyc = AnySeq( 1)
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wb_snoop_stb = AnySeq( 1)
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wb_snoop_we = AnySeq( 1)
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dmi_addr = AnySeq( 4)
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dmi_din = AnySeq(64)
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dmi_req = AnySeq( 1)
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dmi_wr = AnySeq( 1)
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dmi_dout = Signal(64, attrs={"keep": True})
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dmi_ack = Signal( attrs={"keep": True})
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terminated = Signal( attrs={"keep": True})
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# FIXME: ghdl-yosys-plugin doesn't yet support setting parameters (see issue 136).
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# As a workaround, use our own toplevel entity.
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m.submodules.toplevel = Instance("toplevel",
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("i", "clk", ClockSignal("sync")),
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("i", "rst", ResetSignal("sync")),
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("i", "alt_reset", Const(0)),
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("i", "ext_irq", Const(0)),
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("i", "wishbone_insn_in.dat", wb_insn_dat_r),
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("i", "wishbone_insn_in.ack", wb_insn_ack),
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("i", "wishbone_insn_in.stall", wb_insn_stall),
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("o", "wishbone_insn_out.adr", wb_insn_adr),
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("o", "wishbone_insn_out.dat", wb_insn_dat_w),
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("o", "wishbone_insn_out.sel", wb_insn_sel),
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("o", "wishbone_insn_out.cyc", wb_insn_cyc),
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("o", "wishbone_insn_out.stb", wb_insn_stb),
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("o", "wishbone_insn_out.we", wb_insn_we),
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("i", "wishbone_data_in.dat", wb_data_dat_r),
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("i", "wishbone_data_in.ack", wb_data_ack),
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("i", "wishbone_data_in.stall", wb_data_stall),
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("o", "wishbone_data_out.adr", wb_data_adr),
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("o", "wishbone_data_out.dat", wb_data_dat_w),
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("o", "wishbone_data_out.sel", wb_data_sel),
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("o", "wishbone_data_out.cyc", wb_data_cyc),
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("o", "wishbone_data_out.stb", wb_data_stb),
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("o", "wishbone_data_out.we", wb_data_we),
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("i", "wb_snoop_in.adr", wb_snoop_adr),
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("i", "wb_snoop_in.dat", wb_snoop_dat_w),
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("i", "wb_snoop_in.sel", wb_snoop_sel),
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("i", "wb_snoop_in.cyc", wb_snoop_cyc),
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("i", "wb_snoop_in.stb", wb_snoop_stb),
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("i", "wb_snoop_in.we", wb_snoop_we),
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("i", "dmi_addr", dmi_addr),
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("i", "dmi_din", dmi_din),
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("o", "dmi_dout", dmi_dout),
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("i", "dmi_req", dmi_req),
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("i", "dmi_wr", dmi_wr),
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("o", "dmi_ack", dmi_ack),
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("o", "terminated_out", terminated),
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("o", "pfv_out.stb", self.pfv.stb),
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("o", "pfv_out.insn", self.pfv.insn),
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("o", "pfv_out.order", self.pfv.order),
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("o", "pfv_out.intr", self.pfv.intr),
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("o", "pfv_out.cia", self.pfv.cia),
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("o", "pfv_out.nia", self.pfv.nia),
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)
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with m.If(Initial()):
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m.d.comb += Assume(~self.pfv.stb)
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m.d.comb += [
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Assume(~dmi_req),
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Assume(~terminated),
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]
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return m
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