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76 lines
2.1 KiB
Python
76 lines
2.1 KiB
Python
from abc import ABCMeta, abstractmethod
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from amaranth import *
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from amaranth.asserts import *
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from power_fv.check import PowerFVCheck
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__all__ = ["DataStorageCheck", "DataStorageModel", "DataStorageTestbench"]
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# TODO: add support for restricting addresses to non-cachable/write-through regions.
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class DataStorageCheck(PowerFVCheck):
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pass
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class DataStorageModel(metaclass=ABCMeta):
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@abstractmethod
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def connect(self, dut):
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raise NotImplementedError
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@abstractmethod
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def elaborate(self, platform):
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raise NotImplementedError
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class DataStorageTestbench(Elaboratable, metaclass=ABCMeta):
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def __init__(self, check):
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if not isinstance(check, DataStorageCheck):
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raise TypeError("Check must be an instance of DataStorageCheck, not {!r}"
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.format(check))
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self.check = check
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self.name = "storage_data_tb"
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@abstractmethod
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def storage(self):
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raise NotImplementedError
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def elaborate(self, platform):
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m = Module()
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m.submodules.dut = dut = self.check.dut
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m.submodules.storage = storage = self.storage()
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written = Signal(64 // 8)
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shadow = Signal(64)
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m.d.comb += storage.connect(dut)
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with m.If(dut.pfv.stb & dut.pfv.skip):
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m.d.comb += [
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Assert(~dut.pfv.mem.r_mask.any()),
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Assert(~dut.pfv.mem.w_mask.any()),
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]
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with m.If(dut.pfv.stb & (dut.pfv.mem.addr == storage.addr)):
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for i, byte_written in enumerate(written):
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byte_shadow = shadow[i*8:i*8+8]
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byte_w_stb = dut.pfv.mem.w_mask[i]
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byte_w_data = dut.pfv.mem.w_data[i*8:i*8+8]
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byte_r_stb = dut.pfv.mem.r_mask[i]
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byte_r_data = dut.pfv.mem.r_data[i*8:i*8+8]
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with m.If(byte_w_stb):
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m.d.sync += [
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byte_written.eq(1),
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byte_shadow .eq(byte_w_data),
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]
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with m.If(byte_r_stb & byte_written):
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m.d.comb += Assert(byte_r_data == byte_shadow)
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return m
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