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296 lines
10 KiB
Python
296 lines
10 KiB
Python
from amaranth import *
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from amaranth.asserts import Assume
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from power_fv import pfv
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from power_fv.insn.const import *
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from . import InsnSpec
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from .utils import iea
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__all__ = ["MultiplySpec", "DivideSpec"]
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class MultiplySpec(InsnSpec, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.insn .eq(self.pfv.insn[32:]),
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self.pfv.stb .eq(self.insn.is_valid() & ~self.pfv.insn[:32].any()),
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self.pfv.intr.eq(0),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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]
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src_a = Signal(64)
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src_b = Signal(64)
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result = Signal(64)
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ov_32 = Signal()
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# Operand A : (RA) or EXTS((RA)(32:63)) or EXTZ((RA)(32:63))
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m.d.comb += [
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self.pfv.ra.index.eq(self.insn.RA),
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self.pfv.ra.r_stb.eq(1),
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]
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if isinstance(self.insn, MULLI):
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m.d.comb += src_a.eq(self.pfv.ra.r_data)
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elif isinstance(self.insn, (
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MULLW , MULLW_ , MULLWO, MULLWO_,
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MULHW, MULHW_,
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)):
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m.d.comb += src_a.eq(self.pfv.ra.r_data[:32].as_signed())
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elif isinstance(self.insn, (MULHWU, MULHWU_)):
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m.d.comb += src_a.eq(self.pfv.ra.r_data[:32].as_unsigned())
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else:
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assert False
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# Operand B : EXTS(SI) or EXTS((RB)(32:63)) or EXTZ((RB)(32:63))
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if isinstance(self.insn, MULLI):
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m.d.comb += src_b.eq(self.insn.SI)
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elif isinstance(self.insn, (
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MULLW, MULLW_, MULLWO, MULLWO_,
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MULHW, MULHW_,
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)):
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m.d.comb += [
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self.pfv.rb.index .eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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src_b.eq(self.pfv.rb.r_data[:32].as_signed()),
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]
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elif isinstance(self.insn, (MULHWU, MULHWU_)):
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m.d.comb += [
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self.pfv.rb.index.eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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src_b.eq(self.pfv.rb.r_data[:32].as_unsigned())
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]
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else:
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assert False
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if self.pfv.muldiv_altops:
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altop_res = Signal(64)
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altop_mask = Signal(64)
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ca_32 = Signal()
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if isinstance(self.insn, MULLI):
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m.d.comb += altop_mask.eq(0xef31a883837039a0)
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elif isinstance(self.insn, (MULLW, MULLW_)):
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m.d.comb += altop_mask.eq(0x4931591f31f56de1)
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elif isinstance(self.insn, (MULLWO, MULLWO_)):
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m.d.comb += altop_mask.eq(0x37291ea821fbaf9d)
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elif isinstance(self.insn, (MULHW, MULHW_)):
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m.d.comb += altop_mask.eq(0x3426dcf55920989c)
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elif isinstance(self.insn, (MULHWU, MULHWU_)):
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m.d.comb += altop_mask.eq(0x491edb8a5f695d49)
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else:
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assert False
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# Result : (Operand A + Operand B) ^ Altop Mask
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m.d.comb += [
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altop_res.eq(src_a + src_b),
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ca_32.eq(altop_res[32] ^ src_a[32] ^ src_b[32]),
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ov_32.eq((ca_32 ^ altop_res[31]) & ~(src_a[31] ^ src_b[31])),
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result.eq(altop_res ^ altop_mask),
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]
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else:
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raise NotImplementedError
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# Write the result to RT
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m.d.comb += [
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self.pfv.rt.index .eq(self.insn.RT),
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self.pfv.rt.w_stb .eq(1),
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self.pfv.rt.w_data.eq(result),
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]
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# Set XER.{SO,OV,OV32} if the result overflows 32 bits
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if isinstance(self.insn, (MULLWO, MULLWO_)):
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m.d.comb += [
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self.pfv.xer.w_mask.ov .eq(1),
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self.pfv.xer.w_data.ov .eq(ov_32),
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self.pfv.xer.w_mask.ov32.eq(1),
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self.pfv.xer.w_data.ov32.eq(ov_32),
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]
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with m.If(ov_32):
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m.d.comb += [
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self.pfv.xer.w_mask.so.eq(1),
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self.pfv.xer.w_data.so.eq(1),
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]
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# Write CR0
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if isinstance(self.insn, (MULLW_, MULLWO_, MULHW_, MULHWU_)):
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cr0_w_mask = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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cr0_w_data = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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m.d.comb += [
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self.pfv.xer.r_mask.so.eq(1),
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cr0_w_mask .eq(0b1111),
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cr0_w_data.so .eq(Mux(self.pfv.xer.w_mask.so, self.pfv.xer.w_data.so, self.pfv.xer.r_data.so)),
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cr0_w_data.eq_.eq(~Mux(self.pfv.msr.r_data.sf, result[:64].any(), result[:32].any())),
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cr0_w_data.gt .eq(~(cr0_w_data.lt | cr0_w_data.eq_)),
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cr0_w_data.lt .eq(Mux(self.pfv.msr.r_data.sf, result[63], result[31])),
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self.pfv.cr.w_mask.cr0.eq(cr0_w_mask),
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self.pfv.cr.w_data.cr0.eq(cr0_w_data),
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]
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return m
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class DivideSpec(InsnSpec, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.insn .eq(self.pfv.insn[32:]),
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self.pfv.stb .eq(self.insn.is_valid() & ~self.pfv.insn[:32].any()),
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self.pfv.intr.eq(0),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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]
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dividend = Signal(64)
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divisor = Signal(64)
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result = Signal(64)
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ov_32 = Signal()
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# Dividend : (RA)(32:63) or (RA)(32:63)<<32
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m.d.comb += [
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self.pfv.ra.index.eq(self.insn.RA),
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self.pfv.ra.r_stb.eq(1),
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]
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if isinstance(self.insn, (DIVW, DIVW_, DIVWO, DIVWO_, MODSW)):
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m.d.comb += dividend.eq(self.pfv.ra.r_data[:32].as_signed())
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elif isinstance(self.insn, (DIVWU, DIVWU_, DIVWUO, DIVWUO_, MODUW)):
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m.d.comb += dividend.eq(self.pfv.ra.r_data[:32].as_unsigned())
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elif isinstance(self.insn, (
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DIVWE , DIVWE_ , DIVWEO , DIVWEO_ ,
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DIVWEU, DIVWEU_, DIVWEUO, DIVWEUO_,
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)):
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m.d.comb += dividend.eq(Cat(Const(0, 32), self.pfv.ra.r_data[:32]))
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else:
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assert False
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# Divisor : (RB)(32:63)
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m.d.comb += [
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self.pfv.rb.index.eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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]
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if isinstance(self.insn, (
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DIVW , DIVW_ , DIVWO , DIVWO_ ,
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DIVWE, DIVWE_, DIVWEO, DIVWEO_,
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MODSW,
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)):
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m.d.comb += divisor.eq(self.pfv.rb.r_data[:32].as_signed())
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elif isinstance(self.insn, (
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DIVWU , DIVWU_ , DIVWUO , DIVWUO_ ,
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DIVWEU, DIVWEU_, DIVWEUO, DIVWEUO_,
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MODUW ,
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)):
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m.d.comb += divisor.eq(self.pfv.rb.r_data[:32].as_unsigned())
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else:
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assert False
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if self.pfv.muldiv_altops:
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altop_mask = Signal(64)
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altop_res = Signal(signed(64))
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ca_32 = Signal()
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if isinstance(self.insn, (DIVW, DIVW_)):
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m.d.comb += altop_mask.eq(0x75a5d4895a3e15ba)
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elif isinstance(self.insn, (DIVWO, DIVWO_)):
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m.d.comb += altop_mask.eq(0x7098f59fd4822d48)
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elif isinstance(self.insn, (DIVWU, DIVWU_)):
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m.d.comb += altop_mask.eq(0x769c76af68d11402)
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elif isinstance(self.insn, (DIVWUO, DIVWUO_)):
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m.d.comb += altop_mask.eq(0x6ec48c33b1fe6a8f)
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elif isinstance(self.insn, (DIVWE, DIVWE_)):
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m.d.comb += altop_mask.eq(0xdfd9d577965d84d2)
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elif isinstance(self.insn, (DIVWEO, DIVWEO_)):
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m.d.comb += altop_mask.eq(0x88ec39a41f3b07fd)
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elif isinstance(self.insn, (DIVWEU, DIVWEU_)):
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m.d.comb += altop_mask.eq(0x8fc71f88b966fcf0)
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elif isinstance(self.insn, (DIVWEUO, DIVWEUO_)):
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m.d.comb += altop_mask.eq(0x893cca367133b0d3)
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elif isinstance(self.insn, MODSW):
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m.d.comb += altop_mask.eq(0x5ba1758b11ae4e43)
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elif isinstance(self.insn, MODUW):
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m.d.comb += altop_mask.eq(0x1feb9d95f9f0cea5)
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else:
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assert False
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# Result : (Dividend - Divisor) ^ Altop Mask
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m.d.comb += [
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altop_res.eq(dividend.as_signed() - divisor.as_signed()),
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ca_32.eq(altop_res[32] ^ dividend[32] ^ divisor[32]),
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ov_32.eq((ca_32 ^ altop_res[31]) & ~(dividend[31] ^ divisor[31])),
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result.eq(altop_res ^ altop_mask),
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]
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else:
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raise NotImplementedError
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# Write the result to RT
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m.d.comb += [
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self.pfv.rt.index .eq(self.insn.RT),
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self.pfv.rt.w_stb .eq(1),
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self.pfv.rt.w_data.eq(result),
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]
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# Set XER.{SO,OV,OV32} if the result overflows 32 bits
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if isinstance(self.insn, (
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DIVWO , DIVWO_ , DIVWUO , DIVWUO_ ,
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DIVWEO, DIVWEO_, DIVWEUO, DIVWEUO_,
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)):
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m.d.comb += [
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self.pfv.xer.w_mask.ov .eq(1),
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self.pfv.xer.w_data.ov .eq(ov_32),
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self.pfv.xer.w_mask.ov32.eq(1),
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self.pfv.xer.w_data.ov32.eq(ov_32),
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]
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with m.If(ov_32):
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m.d.comb += [
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self.pfv.xer.w_mask.so.eq(1),
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self.pfv.xer.w_data.so.eq(1),
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]
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# Write CR0
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if isinstance(self.insn, (
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DIVW_ , DIVWO_ , DIVWU_ , DIVWUO_ ,
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DIVWE_, DIVWEO_, DIVWEU_, DIVWEUO_,
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)):
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cr0_w_mask = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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cr0_w_data = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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m.d.comb += [
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self.pfv.xer.r_mask.so.eq(1),
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cr0_w_mask .eq(0b1111),
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cr0_w_data.so .eq(Mux(self.pfv.xer.w_mask.so, self.pfv.xer.w_data.so, self.pfv.xer.r_data.so)),
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cr0_w_data.eq_.eq(~Mux(self.pfv.msr.r_data.sf, result[:64].any(), result[:32].any())),
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cr0_w_data.gt .eq(~(cr0_w_data.lt | cr0_w_data.eq_)),
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cr0_w_data.lt .eq(Mux(self.pfv.msr.r_data.sf, result[63], result[31])),
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self.pfv.cr.w_mask.cr0.eq(cr0_w_mask),
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self.pfv.cr.w_data.cr0.eq(cr0_w_data),
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]
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return m
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