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125 lines
3.0 KiB
Python
125 lines
3.0 KiB
Python
from amaranth import *
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from amaranth.utils import log2_int
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__all__ = ["Interface"]
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class Interface(Record):
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"""Power-FV interface.
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The interface between the formal testbench and the processor-under-test.
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Attributes
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----------
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stb : Signal
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Instruction strobe. Asserted when the processor retires an instruction. Other signals are
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only valid when ``stb`` is asserted.
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"""
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def __init__(self, *, name=None, src_loc_at=0):
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layout = [
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("stb", 1),
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("insn", 64),
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("order", 64),
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("intr", 1),
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]
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# IA
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layout += [
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("cia", 64),
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("nia", 64),
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]
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# GPRs
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def gprf_port(access):
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assert access in ("r", "w", "rw")
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layout = [("index", 5)]
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if "r" in access:
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layout += [
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("r_stb", 1),
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("r_data", 64),
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]
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if "w" in access:
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layout += [
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("w_stb", 1),
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("w_data", 64),
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]
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return layout
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layout += [
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("ra", gprf_port("rw")),
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("rb", gprf_port("r")),
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("rs", gprf_port("r")),
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("rt", gprf_port("rw")),
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]
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# CR
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layout += [
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("cr", [
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("r_stb", 8),
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("r_data", 32),
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("w_stb", 8),
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("w_data", 32),
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]),
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]
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# MSR
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layout += [
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("msr", [
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("r_mask", 64),
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("r_data", 64),
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("w_mask", 64),
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("w_data", 64),
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]),
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]
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# SPRs
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layout += [
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(spr_name, [
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("r_mask", 64),
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("r_data", 64),
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("w_mask", 64),
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("w_data", 64),
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]) for spr_name in (
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"lr",
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"ctr",
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"tar",
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"xer",
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"srr0",
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"srr1",
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)
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]
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# Storage
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def mem_port(access, *, depth_log2=64, width=64, granularity=8):
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assert access in ("r", "rw")
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assert depth_log2 in (32, 64)
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assert width in (32, 64)
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assert granularity in (8, 16, 32, 64)
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assert width >= granularity
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granularity_bits = max(1, log2_int(width // granularity))
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layout = [
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("addr", depth_log2 - granularity_bits),
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("r_stb", granularity_bits),
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("r_data", width),
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]
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if "w" in access:
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layout += [
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("w_stb", granularity_bits),
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("w_data", width),
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]
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return layout
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layout += [
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("insn_mem", mem_port("r")),
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("data_mem", mem_port("rw")),
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]
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super().__init__(layout, name=name, src_loc_at=1 + src_loc_at)
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