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252 lines
8.3 KiB
Python
252 lines
8.3 KiB
Python
from amaranth import *
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from amaranth.asserts import *
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from .. import PowerFVCheck
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from ... import pfv, tb
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from ...utils import iea_mask
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from ._fmt import *
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from ._insn import *
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__all__ = ["BranchSpec", "BranchCheck"]
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class BranchSpec(Elaboratable):
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def __init__(self, insn_cls, post):
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self.insn_cls = insn_cls
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self.pfv = pfv.Interface()
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self.post = tb.Trigger(cycle=post)
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def triggers(self):
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yield self.post
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def elaborate(self, platform):
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m = Module()
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spec_insn = self.insn_cls()
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with m.If(self.post.stb):
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m.d.sync += [
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Assume(self.pfv.stb),
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Assume(self.pfv.insn[32:] == spec_insn),
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Assert(self.pfv.msr.w_mask[63 - 0]), # MSR.SF
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]
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msr_w_sf = Signal()
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m.d.comb += msr_w_sf.eq(self.pfv.msr.w_data[63 - 0])
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if isinstance(spec_insn, (Instruction_B, Instruction_XL_bc)):
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bo_valid_patterns = [
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"001--",
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"011--",
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"1-1--",
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]
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if not isinstance(spec_insn, (BCCTR, BCCTRL)):
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# bcctr/bcctrl forms with BO(2)=0 ("decrement and test CTR") are illegal.
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bo_valid_patterns += [
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"0000-",
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"0001-",
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"0100-",
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"0101-",
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"1-00-",
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"1-01-",
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]
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bo_invalid = Signal()
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m.d.comb += bo_invalid.eq(~spec_insn.bo.matches(*bo_valid_patterns))
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with m.If(self.post.stb):
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m.d.sync += Assert(bo_invalid.implies(self.pfv.intr))
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# NIA
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spec_nia = Signal(unsigned(64))
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taken = Signal()
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offset = Signal(signed(62))
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target = Signal(signed(64))
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += [
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taken .eq(1),
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offset.eq(spec_insn.li)
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]
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elif isinstance(spec_insn, (Instruction_B, Instruction_XL_bc)):
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cond_bit = Signal()
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ctr_any = Signal()
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cond_ok = Signal()
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ctr_ok = Signal()
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m.d.comb += [
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cond_bit.eq(self.pfv.cr.r_data[::-1].bit_select(spec_insn.bi, width=1)),
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ctr_any .eq( self.pfv.ctr.w_data[:32].any() |
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(self.pfv.ctr.w_data[32:].any() & msr_w_sf)),
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cond_ok .eq(spec_insn.bo[4-0] | (spec_insn.bo[4-1] == cond_bit)),
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ctr_ok .eq(spec_insn.bo[4-2] | (ctr_any ^ spec_insn.bo[4-3])),
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]
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if isinstance(spec_insn, (BCCTR, BCCTRL)):
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m.d.comb += taken.eq(cond_ok)
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else:
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m.d.comb += taken.eq(cond_ok & ctr_ok)
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if isinstance(spec_insn, Instruction_B):
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m.d.comb += offset.eq(spec_insn.bd)
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elif isinstance(spec_insn, (BCLR, BCLRL)):
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m.d.comb += offset.eq(self.pfv.lr .r_data[2:])
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elif isinstance(spec_insn, (BCCTR, BCCTRL)):
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m.d.comb += offset.eq(self.pfv.ctr.r_data[2:])
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elif isinstance(spec_insn, (BCTAR, BCTARL)):
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m.d.comb += offset.eq(self.pfv.tar.r_data[2:])
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else:
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assert False
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else:
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assert False
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with m.If(taken):
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if isinstance(spec_insn, (Instruction_I, Instruction_B)) and spec_insn.aa.value == 0:
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m.d.comb += target.eq(self.pfv.cia + (offset << 2))
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else:
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m.d.comb += target.eq(offset << 2)
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with m.Else():
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m.d.comb += target.eq(self.pfv.cia + 4)
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m.d.comb += spec_nia.eq(iea_mask(target, msr_w_sf))
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with m.If(self.post.stb & ~self.pfv.intr):
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m.d.sync += Assert(self.pfv.nia == spec_nia)
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# CR
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spec_cr_r_stb = Signal(8)
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += spec_cr_r_stb.eq(0)
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elif isinstance(spec_insn, (Instruction_B, Instruction_XL_bc)):
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m.d.comb += spec_cr_r_stb[::-1].bit_select(spec_insn.bi[2:], width=1).eq(1)
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else:
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assert False
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with m.If(self.post.stb & ~self.pfv.intr):
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for i, spec_cr_r_stb_bit in enumerate(spec_cr_r_stb):
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pfv_cr_r_stb_bit = self.pfv.cr.r_stb[i]
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m.d.sync += Assert(spec_cr_r_stb_bit.implies(pfv_cr_r_stb_bit))
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# LR
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spec_lr_r_stb = Signal()
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spec_lr_w_stb = Signal()
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spec_lr_r_mask = Signal(64)
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spec_lr_w_mask = Signal(64)
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spec_lr_w_data = Signal(64)
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if isinstance(spec_insn, (Instruction_I, Instruction_B)):
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m.d.comb += spec_lr_r_stb.eq(0)
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elif isinstance(spec_insn, (Instruction_XL_bc)):
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if isinstance(spec_insn, (BCLR, BCLRL)):
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m.d.comb += spec_lr_r_stb.eq(1)
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else:
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m.d.comb += spec_lr_r_stb.eq(0)
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else:
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assert False
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m.d.comb += spec_lr_w_stb.eq(spec_insn.lk)
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cia_4 = Signal(unsigned(64))
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m.d.comb += cia_4.eq(self.pfv.cia + 4)
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m.d.comb += [
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spec_lr_r_mask.eq(Repl(spec_lr_r_stb, 64)),
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spec_lr_w_mask.eq(Repl(spec_lr_w_stb, 64)),
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spec_lr_w_data.eq(iea_mask(cia_4, msr_w_sf)),
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]
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with m.If(self.post.stb & ~self.pfv.intr):
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m.d.sync += [
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Assert((self.pfv.lr.r_mask & spec_lr_r_mask) == spec_lr_r_mask),
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Assert(self.pfv.lr.w_mask == spec_lr_w_mask),
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Assert((self.pfv.lr.w_data & spec_lr_w_mask) == (spec_lr_w_data & spec_lr_w_mask)),
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]
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# CTR
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spec_ctr_r_stb = Signal()
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spec_ctr_w_stb = Signal()
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spec_ctr_r_mask = Signal(64)
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spec_ctr_w_mask = Signal(64)
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spec_ctr_w_data = Signal(64)
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += spec_ctr_r_stb.eq(0)
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elif isinstance(spec_insn, Instruction_B):
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m.d.comb += spec_ctr_r_stb.eq(~spec_insn.bo[4-2])
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elif isinstance(spec_insn, Instruction_XL_bc):
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if isinstance(spec_insn, (BCCTR, BCCTRL)):
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m.d.comb += spec_ctr_r_stb.eq(1)
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else:
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m.d.comb += spec_ctr_r_stb.eq(~spec_insn.bo[4-2])
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else:
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assert False
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if isinstance(spec_insn, Instruction_I):
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m.d.comb += spec_ctr_w_stb.eq(0)
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elif isinstance(spec_insn, Instruction_B):
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m.d.comb += spec_ctr_w_stb.eq(~spec_insn.bo[4-2])
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elif isinstance(spec_insn, Instruction_XL_bc):
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if isinstance(spec_insn, (BCCTR, BCCTRL)):
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m.d.comb += spec_ctr_w_stb.eq(0)
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else:
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m.d.comb += spec_ctr_w_stb.eq(~spec_insn.bo[4-2])
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else:
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assert False
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m.d.comb += [
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spec_ctr_r_mask.eq(Repl(spec_ctr_r_stb, 64)),
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spec_ctr_w_mask.eq(Repl(spec_ctr_w_stb, 64)),
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spec_ctr_w_data.eq(self.pfv.ctr.r_data - 1),
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]
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with m.If(self.post.stb & ~self.pfv.intr):
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m.d.sync += [
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Assert((self.pfv.ctr.r_mask & spec_ctr_r_mask) == spec_ctr_r_mask),
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Assert(self.pfv.ctr.w_mask == spec_ctr_w_mask),
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Assert((self.pfv.ctr.w_data & spec_ctr_w_mask) == (spec_ctr_w_data & spec_ctr_w_mask)),
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]
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# TAR
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spec_tar_r_stb = Signal()
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spec_tar_r_mask = Signal(64)
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if isinstance(spec_insn, (Instruction_I, Instruction_B)):
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m.d.comb += spec_tar_r_stb.eq(0)
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elif isinstance(spec_insn, (Instruction_XL_bc)):
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if isinstance(spec_insn, (BCTAR, BCTARL)):
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m.d.comb += spec_tar_r_stb.eq(1)
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else:
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m.d.comb += spec_tar_r_stb.eq(0)
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else:
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assert False
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m.d.comb += spec_tar_r_mask.eq(Repl(spec_tar_r_stb, 64))
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with m.If(self.post.stb & ~self.pfv.intr):
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m.d.sync += Assert((self.pfv.tar.r_mask & spec_tar_r_mask) == spec_tar_r_mask)
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return m
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class BranchCheck(PowerFVCheck, name="_insn_branch"):
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def __init_subclass__(cls, name, insn_cls):
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super().__init_subclass__(name)
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cls.insn_cls = insn_cls
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def get_testbench(self, dut, post):
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tb_spec = BranchSpec(self.insn_cls, post)
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tb_top = tb.Testbench(tb_spec, dut)
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return tb_top
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