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64 lines
1.9 KiB
Python
64 lines
1.9 KiB
Python
__all__ = [
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"Interrupt",
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"INTR_ALIGNMENT",
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"INTR_PROGRAM",
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"INTR_SYSTEM_CALL",
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]
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class Interrupt:
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def __init__(self, vector_addr, ir, dr, ee, ri, me, hv, s):
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self.vector_addr = vector_addr
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self.ir = ir
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self.dr = dr
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self.ee = ee
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self.ri = ri
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self.me = me
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self.hv = hv
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self.s = s
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def write_msr(self, msr):
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def _write_field(field, value):
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stmts = []
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if value is not None:
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stmts.append(getattr(msr.w_mask, field).eq(-1))
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stmts.append(getattr(msr.w_data, field).eq(value))
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return stmts
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# See PowerISA v3.1, Book III, Section 7.5, Figure 67
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stmts = [
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_write_field("ir" , self.ir),
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_write_field("dr" , self.dr),
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_write_field("fe0", 0),
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_write_field("fe1", 0),
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_write_field("ee" , self.ee),
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_write_field("ri" , self.ri),
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_write_field("me" , self.me),
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_write_field("hv" , self.hv),
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_write_field("s" , self.s),
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_write_field("pr" , 0),
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_write_field("pmm", 0),
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_write_field("te" , 0),
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_write_field("fp" , 0),
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_write_field("vec", 0),
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_write_field("vsx", 0),
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_write_field("sf" , 1),
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msr.w_mask[63- 5].eq(1),
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msr.w_data[63- 5].eq(0),
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msr.w_mask[63-31].eq(1),
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msr.w_data[63-31].eq(0),
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]
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return stmts
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# TODO:
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# - Support MSR.{IR,DR,HV,S,LE} bits, which depend on context (e.g. LPCR)
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# - Support LPCR.{AIL,HAIL} fields. For now, assume AIL=0 and HAIL=0
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# (i.e. interrupts always set IR/DR to 0).
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INTR_ALIGNMENT = Interrupt(0x600, ir=0, dr=0, ee=0, ri=0, me=None, hv=None, s=None)
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INTR_PROGRAM = Interrupt(0x700, ir=0, dr=0, ee=0, ri=0, me=None, hv=None, s=None)
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INTR_SYSTEM_CALL = Interrupt(0xC00, ir=0, dr=0, ee=0, ri=0, me=None, hv=None, s=None)
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