From 43c771bbffb891c6c8b1f9a4b4dea173a1830ef3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Wed, 6 Apr 2022 14:14:57 +0200 Subject: [PATCH] WIP --- core.vhdl | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/core.vhdl b/core.vhdl index cf730c5..3fb54b8 100644 --- a/core.vhdl +++ b/core.vhdl @@ -49,7 +49,9 @@ entity core is ext_irq : in std_ulogic; - terminated_out : out std_logic + terminated_out : out std_logic; + + complete_out : out instr_tag_t ); end core; @@ -187,6 +189,7 @@ architecture behave of core is begin core_rst <= dbg_core_rst or rst; + complete_out <= complete; resets: process(clk) begin -- 2.35.1