cores
/
power-fv
3
1
Fork 0
Code Issues 18 Pull Requests Projects Releases Wiki Activity
52 Commits
2 Branches
0 Tags
251 KiB
dinofly
main
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'baaac86be1'
${ noResults }
Commit Graph

6 Commits (baaac86be199e07de6f798f1654a12172ef0ca89)

Author SHA1 Message Date
Jean-François Nguyen a413025fcb Update SPR interface and split consistency check. 
* Use bitmasks to describe SPR accesses at the field granularity.

* Use separate checks for each SPR, instead of covering them all at
  once. Users may run them in the same batch, and know which SPR passes
  or fails its check.
 4 years ago
Jean-François Nguyen c6a74333e8 pfv: add MSR and SRR0/SRR1 SPRs. 4 years ago
Jean-François Nguyen 6ae4978f0c pfv: expose CR as a flat 32-bit value. 4 years ago
Jean-François Nguyen b84a23877a checks.gpr: add GPRCheck. 4 years ago
Jean-François Nguyen 7114ed807e pfv: add ports for IA,GPRs,CR,SPRs and storage. 4 years ago
Jean-François Nguyen 96bbd85e83 __init__: do not export sub-packages by default. 
Also, rename dut.py to pfv.py.
 4 years ago