10 Commits (main)

Author SHA1 Message Date
Jean-François Nguyen a2876b6a95 cores/microwatt: temporarily disable the liveness check. 1 year ago
Jean-François Nguyen 846d4f8a4c session: add an implicit exit at the end of the command file.
And remove the 'exit' command.
1 year ago
Jean-François Nguyen 749184e964 Add instruction storage check. 1 year ago
Jean-François Nguyen 9fde9f9786 Add liveness check. 1 year ago
Jean-François Nguyen 23f503549f Add causal consistency check. 1 year ago
Jean-François Nguyen a325393c42 Add checks for multiplication/division instructions. 1 year ago
Jean-François Nguyen c16e678c49 Add a --exclude parameter to the check command.
Also, remove the expand command; when a group of checks is selected by
the 'check' command, its members are immediately added to the session.
1 year ago
Jean-François Nguyen 5ca0001b4b Add data storage check.
This check is implemented in two parts:
- an implementation-dependant DataStorageModel, which is connected to
  the DUT and emulates bus accesses to a r/w memory.
- a DataStorageTestbench, which checks that a load from a given address
  returns the last value that was stored to it.
1 year ago
Jean-François Nguyen ec7cfdd719 cores/microwatt: move microwatt.py to its own python module.
* update dependencies.
* add amaranth-soc as a dependency, in order to reuse its bus
  interfaces (e.g. Wishbone).
* add a `prog` argument to PowerFVSession that overrides the name of
  its CLI.
1 year ago
Jean-François Nguyen dd6048f14b In-depth refactoring, improved user interface.
* A PowerFVSession class provides a REPL interface. Functionality is
  split into commands (e.g. add checks, build) which can be provided
  interactively or from a file.

  See cores/microwatt for an example of its integration.

* Instruction specifications are now separated from verification

  An InsnSpec class provides a behavioral model using the same PowerFV
  interface as a core. This interface is output-only for a core, but
  bidirectional for the InsnSpec:
    - fields related to context (e.g. read data) are inputs,
    - fields related to side-effects (e.g. write strobes) are outputs.

  The testbench is responsible for driving inputs to the same values
  as the core, then check outputs for equivalence. This decoupling
  provides a path towards using PowerFV in simulation.

* Instruction encodings are now defined by their fields, not their
  format (which was problematic e.g. X-form has dozens of variants).

  Field declarations can be preset to a value, or left undefined. In
  the latter case, they are implicitly cast to AnyConst (which is
  useful for arbitrary values like immediates).
1 year ago