diff --git a/power_fv/checks/insn/_addsub.py b/power_fv/checks/insn/_addsub.py new file mode 100644 index 0000000..fc29dff --- /dev/null +++ b/power_fv/checks/insn/_addsub.py @@ -0,0 +1,376 @@ +from amaranth import * +from amaranth.asserts import * + +from .. import PowerFVCheck +from ... import pfv, tb + +from ._fmt import * +from ._insn import * + + +__all__ = ["AddSubtractSpec", "AddSubtractCheck"] + + +class AddSubtractSpec(Elaboratable): + def __init__(self, insn_cls, post): + self.insn_cls = insn_cls + self.pfv = pfv.Interface() + self.post = tb.Trigger(cycle=post) + + def triggers(self): + yield self.post + + def elaborate(self, platform): + m = Module() + + spec_insn = self.insn_cls() + + with m.If(self.post.stb): + m.d.sync += [ + Assume(self.pfv.stb), + Assume(self.pfv.insn[32:] == spec_insn), + ] + + spec_ra_r_stb = Signal() + spec_rb_r_stb = Signal() + spec_rt_w_stb = Signal() + spec_rt_w_data = Signal(64) + spec_cr_w_stb = Signal( 8) + spec_cr_w_data = Signal(32) + spec_msr_r_mask = Signal(64) + spec_xer_r_mask = Signal(64) + spec_xer_w_mask = Signal(64) + spec_xer_w_data = Signal(64) + + src_a = Signal(signed(64)) + src_b = Signal(signed(64)) + src_c = Signal() + result = Signal(unsigned(65)) + + ca_64 = Signal() + ca_32 = Signal() + ov_64 = Signal() + ov_32 = Signal() + + # Operand A : (RA) or 0 or NIA or ~(RA) + + if isinstance(spec_insn, (ADDI, ADDIS)): + m.d.comb += [ + spec_ra_r_stb.eq(spec_insn.ra != 0), + src_a.eq(Mux(spec_insn.ra != 0, self.pfv.ra.r_data, 0)), + ] + elif isinstance(spec_insn, ADDPCIS): + m.d.comb += [ + spec_ra_r_stb.eq(0), + src_a.eq(self.pfv.nia), + ] + elif isinstance(spec_insn, ( + ADD , ADD_ , ADDO , ADDO_ , + ADDIC, ADDIC_, + ADDC , ADDC_ , ADDCO , ADDCO_ , + ADDE , ADDE_ , ADDEO , ADDEO_ , + ADDME, ADDME_, ADDMEO, ADDMEO_, + ADDZE, ADDZE_, ADDZEO, ADDZEO_, + ADDEX, + )): + m.d.comb += [ + spec_ra_r_stb.eq(1), + src_a.eq(self.pfv.ra.r_data), + ] + elif isinstance(spec_insn, ( + SUBF , SUBF_ , SUBFO , SUBFO_ , + SUBFIC, + SUBFC , SUBFC_ , SUBFCO , SUBFCO_ , + SUBFE , SUBFE_ , SUBFEO , SUBFEO_ , + SUBFME, SUBFME_, SUBFMEO, SUBFMEO_, + SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_, + NEG , NEG_ , NEGO , NEGO_ , + )): + m.d.comb += [ + spec_ra_r_stb.eq(1), + src_a.eq(~self.pfv.ra.r_data), + ] + else: + assert False + + # Operand B : SI or SI<<16 or D<<16 or (RB) or -1 or 0 + + if isinstance(spec_insn, (ADDI, ADDIC, ADDIC_, SUBFIC)): + m.d.comb += [ + spec_rb_r_stb.eq(0), + src_b.eq(spec_insn.si), + ] + elif isinstance(spec_insn, ADDIS): + m.d.comb += [ + spec_rb_r_stb.eq(0), + src_b.eq(Cat(Const(0, 16), spec_insn.si).as_signed()), + ] + elif isinstance(spec_insn, ADDPCIS): + imm_d = Signal(signed(16)) + m.d.comb += [ + spec_rb_r_stb.eq(0), + imm_d.eq(Cat(spec_insn.d2, spec_insn.d1, spec_insn.d0)), + src_b.eq(Cat(Const(0, 16), imm_d).as_signed()), + ] + elif isinstance(spec_insn, ( + ADD , ADD_ , ADDO , ADDO_ , + SUBF , SUBF_ , SUBFO , SUBFO_ , + ADDC , ADDC_ , ADDCO , ADDCO_ , + ADDE , ADDE_ , ADDEO , ADDEO_ , + SUBFC, SUBFC_, SUBFCO, SUBFCO_, + SUBFE, SUBFE_, SUBFEO, SUBFEO_, + ADDEX, + )): + m.d.comb += [ + spec_rb_r_stb.eq(1), + src_b.eq(self.pfv.rb.r_data), + ] + elif isinstance(spec_insn, ( + ADDME , ADDME_ , ADDMEO , ADDMEO_ , + SUBFME, SUBFME_, SUBFMEO, SUBFMEO_, + )): + m.d.comb += [ + spec_rb_r_stb.eq(0), + src_b.eq(-1), + ] + elif isinstance(spec_insn, ( + ADDZE , ADDZE_ , ADDZEO , ADDZEO_ , + SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_, + NEG , NEG_ , NEGO , NEGO_ , + )): + m.d.comb += [ + spec_rb_r_stb.eq(0), + src_b.eq(0), + ] + else: + assert False + + # Operand C : 0 or 1 or XER.CA or XER.OV + + if isinstance(spec_insn, ( + ADDI , ADDIS , ADDPCIS, + ADD , ADD_ , ADDO , ADDO_ , + ADDIC, ADDIC_, + ADDC , ADDC_ , ADDCO , ADDCO_, + )): + m.d.comb += src_c.eq(0) + elif isinstance(spec_insn, ( + SUBF , SUBF_ , SUBFO , SUBFO_ , + SUBFIC, + SUBFC , SUBFC_, SUBFCO, SUBFCO_, + NEG , NEG_ , NEGO , NEGO_ , + )): + m.d.comb += src_c.eq(1) + elif isinstance(spec_insn, ( + ADDE , ADDE_ , ADDEO , ADDEO_ , + SUBFE , SUBFE_ , SUBFEO , SUBFEO_ , + ADDME , ADDME_ , ADDMEO , ADDMEO_ , + ADDZE , ADDZE_ , ADDZEO , ADDZEO_ , + SUBFME, SUBFME_, SUBFMEO, SUBFMEO_, + SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_, + )): + m.d.comb += [ + spec_xer_r_mask[63 - 34].eq(1), # XER.CA + src_c.eq(self.pfv.xer.r_data[63 - 34]), + ] + elif isinstance(spec_insn, ADDEX): + m.d.comb += [ + spec_xer_r_mask[63 - 33].eq(1), # XER.OV + src_c.eq(self.pfv.xer.r_data[63 - 33]), + ] + else: + assert False + + # Result : Operand A + Operand B + Operand C + + tmp_a = Signal(unsigned(65)) + tmp_b = Signal(unsigned(65)) + + m.d.comb += [ + tmp_a .eq(src_a.as_unsigned()), + tmp_b .eq(src_b.as_unsigned()), + result.eq(tmp_a + tmp_b + src_c), + + ca_64.eq(result[64]), + ca_32.eq(result[32] ^ src_a[32] ^ src_b[32]), + ov_64.eq((ca_64 ^ result[63]) & ~(src_a[63] ^ src_b[63])), + ov_32.eq((ca_32 ^ result[31]) & ~(src_a[31] ^ src_b[31])), + ] + + # GPRs + + m.d.comb += [ + spec_rt_w_stb .eq(1), + spec_rt_w_data.eq(result[:64]), + ] + + with m.If(self.post.stb & ~self.pfv.intr): + m.d.sync += [ + Assert(spec_ra_r_stb.implies(self.pfv.ra.r_stb)), + Assert(spec_rb_r_stb.implies(self.pfv.rb.r_stb)), + Assert(self.pfv.rt.w_stb == spec_rt_w_stb), + Assert(spec_rt_w_stb.implies(self.pfv.rt.w_data == spec_rt_w_data)), + ] + + # MSR + + msr_r_sf = Signal() + + m.d.comb += [ + spec_msr_r_mask[63 - 0].eq(1), + msr_r_sf.eq(self.pfv.msr.r_data[63 - 0]), + ] + + with m.If(self.post.stb & ~self.pfv.intr): + m.d.sync += Assert((self.pfv.msr.r_mask & spec_msr_r_mask) == spec_msr_r_mask) + + # XER + + xer_r_so = Signal() + xer_w_so = Signal() + xer_w_ov = Signal() + xer_w_ca = Signal() + xer_w_ov32 = Signal() + xer_w_ca32 = Signal() + + m.d.comb += [ + xer_r_so .eq(self.pfv.xer.r_data[63 - 32]), + xer_w_so .eq(xer_w_ov), + xer_w_ov .eq(Mux(msr_r_sf, ov_64, ov_32)), + xer_w_ca .eq(Mux(msr_r_sf, ca_64, ca_32)), + xer_w_ov32.eq(ov_32), + xer_w_ca32.eq(ca_32), + ] + + if isinstance(spec_insn, ( + ADD_ , ADDO_ , ADDIC_ , + SUBF_ , SUBFO_ , + ADDC_ , ADDCO_ , ADDE_ , ADDEO_ , + SUBFC_ , SUBFCO_ , SUBFE_ , SUBFEO_ , + ADDME_ , ADDMEO_ , ADDZE_ , ADDZEO_ , + SUBFME_, SUBFMEO_, SUBFZE_, SUBFZEO_, + NEG_ , NEGO_ , + )): + # Read XER.SO (to update CR0) + m.d.comb += spec_xer_r_mask[63 - 32].eq(1) + + if isinstance(spec_insn, ( + ADDO , ADDO_ , SUBFO , SUBFO_ , + ADDCO , ADDCO_ , SUBFCO , SUBFCO_ , + ADDEO , ADDEO_ , SUBFEO , SUBFEO_ , + ADDMEO, ADDMEO_, SUBFMEO, SUBFMEO_, + ADDZEO, ADDZEO_, SUBFZEO, SUBFZEO_, + NEGO , NEGO_ , + )): + # Set XER.SO + m.d.comb += [ + spec_xer_w_mask[63 - 32].eq(xer_w_so), + spec_xer_w_data[63 - 32].eq(xer_w_so), + ] + + if isinstance(spec_insn, ( + ADDO , ADDO_ , SUBFO , SUBFO_ , + ADDCO , ADDCO_ , SUBFCO , SUBFCO_ , + ADDEO , ADDEO_ , SUBFEO , SUBFEO_ , + ADDMEO, ADDMEO_, SUBFMEO, SUBFMEO_, + ADDZEO, ADDZEO_, SUBFZEO, SUBFZEO_, + ADDEX , + NEGO , NEGO_ , + )): + # Write XER.OV and XER.OV32 + m.d.comb += [ + spec_xer_w_mask[63 - 33].eq(1), + spec_xer_w_data[63 - 33].eq(xer_w_ov), + spec_xer_w_mask[63 - 44].eq(1), + spec_xer_w_data[63 - 44].eq(xer_w_ov32), + ] + + if isinstance(spec_insn, ( + ADDIC , ADDIC_ , SUBFIC , + ADDC , ADDC_ , ADDCO , ADDCO_ , + SUBFC , SUBFC_ , SUBFCO , SUBFCO_ , + ADDE , ADDE_ , ADDEO , ADDEO_ , + SUBFE , SUBFE_ , SUBFEO , SUBFEO_ , + ADDME , ADDME_ , ADDMEO , ADDMEO_ , + SUBFME, SUBFME_, SUBFMEO, SUBFMEO_, + ADDZE , ADDZE_ , ADDZEO , ADDZEO_ , + SUBFZE, SUBFZE_, SUBFZEO, SUBFZEO_, + )): + # Write XER.CA and XER.CA32 + m.d.comb += [ + spec_xer_w_mask[63 - 34].eq(1), + spec_xer_w_data[63 - 34].eq(xer_w_ca), + spec_xer_w_mask[63 - 45].eq(1), + spec_xer_w_data[63 - 45].eq(xer_w_ca32), + ] + + keep_xer_w_mask = Signal(64) + keep_xer_w_data = Signal(64) + + m.d.comb += [ + keep_xer_w_mask.eq(self.pfv.xer.w_mask & ~spec_xer_w_mask), + keep_xer_w_data.eq(self.pfv.xer.r_data & keep_xer_w_mask), + ] + + with m.If(self.post.stb & ~self.pfv.intr): + m.d.sync += [ + Assert((self.pfv.xer.r_mask & spec_xer_r_mask) == spec_xer_r_mask), + Assert((self.pfv.xer.w_mask & spec_xer_w_mask) == spec_xer_w_mask), + Assert((self.pfv.xer.w_data & spec_xer_w_mask) == spec_xer_w_data), + Assert((self.pfv.xer.r_mask & keep_xer_w_mask) == keep_xer_w_mask), + Assert((self.pfv.xer.w_data & keep_xer_w_mask) == keep_xer_w_data), + ] + + # CR + + cr0_w_lt = Signal() + cr0_w_gt = Signal() + cr0_w_eq = Signal() + cr0_w_so = Signal() + + m.d.comb += [ + cr0_w_lt.eq(Mux(msr_r_sf, result[63], result[31])), + cr0_w_gt.eq(~(cr0_w_lt | cr0_w_eq)), + cr0_w_eq.eq(~Mux(msr_r_sf, result[:64].any(), result[:32].any())), + cr0_w_so.eq(Mux(spec_xer_w_mask[63 - 32], xer_w_so, xer_r_so)), + ] + + if isinstance(spec_insn, ( + ADD_ , ADDO_ , ADDIC_ , + SUBF_ , SUBFO_ , + ADDC_ , ADDCO_ , ADDE_ , ADDEO_ , + SUBFC_ , SUBFCO_ , SUBFE_ , SUBFEO_ , + ADDME_ , ADDMEO_ , ADDZE_ , ADDZEO_ , + SUBFME_, SUBFMEO_, SUBFZE_, SUBFZEO_, + NEG_ , NEGO_ , + )): + # Write CR0 + m.d.comb += [ + spec_cr_w_stb [ 7 - 0].eq(1), + spec_cr_w_data[31 - 0].eq(cr0_w_lt), + spec_cr_w_data[31 - 1].eq(cr0_w_gt), + spec_cr_w_data[31 - 2].eq(cr0_w_eq), + spec_cr_w_data[31 - 3].eq(cr0_w_so), + ] + + spec_cr_w_mask = Signal(32) + m.d.comb += spec_cr_w_mask.eq(Cat(Repl(s, 4) for s in spec_cr_w_stb)) + + with m.If(self.post.stb & ~self.pfv.intr): + m.d.sync += [ + Assert(self.pfv.cr.w_stb == spec_cr_w_stb), + Assert((self.pfv.cr.w_data & spec_cr_w_mask) == spec_cr_w_data), + ] + + return m + + +class AddSubtractCheck(PowerFVCheck, name="_insn_addsub"): + def __init_subclass__(cls, name, insn_cls): + super().__init_subclass__(name) + cls.insn_cls = insn_cls + + def get_testbench(self, dut, post): + tb_spec = AddSubtractSpec(self.insn_cls, post) + tb_top = tb.Testbench(tb_spec, dut) + return tb_top diff --git a/power_fv/checks/insn/_fmt.py b/power_fv/checks/insn/_fmt.py index a117947..1d5f605 100644 --- a/power_fv/checks/insn/_fmt.py +++ b/power_fv/checks/insn/_fmt.py @@ -6,10 +6,13 @@ from amaranth.hdl.ast import ValueCastable __all__ = [ "Instruction_I", "Instruction_B", - "Instruction_D_cmp", + "Instruction_D_add", "Instruction_D_cmp", + "Instruction_DX", "Instruction_X_cmp", "Instruction_XL_bc", "Instruction_XL_crl", "Instruction_XL_crf", "Instruction_XFX_spr", + "Instruction_XO", + "Instruction_Z23_add", ] @@ -130,6 +133,32 @@ class Instruction_XL_crf(ValueCastable): return Cat(self._3, self.xo, self._2, self._1, self.bfa, self._0, self.bf, self.po) +class Instruction_D_add(ValueCastable): + po = None + rt = None + ra = None + _i = None + + def __init_subclass__(cls, *, po): + cls.po = Const(po, unsigned(6)) + + def __init__(self): + self.rt = AnyConst(unsigned(5)) + self.ra = AnyConst(unsigned(5)) + self._i = AnyConst(16) + + @property + def si(self): + return self._i.as_signed() + + def ui(self): + return self._i.as_unsigned() + + @ValueCastable.lowermethod + def as_value(self): + return Cat(self._i, self.ra, self.rt, self.po) + + class Instruction_D_cmp(ValueCastable): po = None bf = None @@ -160,6 +189,29 @@ class Instruction_D_cmp(ValueCastable): return Cat(self._i, self.ra, self.l, self._0, self.bf, self.po) +class Instruction_DX(ValueCastable): + po = None + rt = None + d1 = None + d0 = None + xo = None + d2 = None + + def __init_subclass__(cls, *, po, xo): + cls.po = Const(po, unsigned(6)) + cls.xo = Const(xo, unsigned(5)) + + def __init__(self): + self.rt = AnyConst(unsigned( 5)) + self.d1 = AnyConst(unsigned( 5)) + self.d0 = AnyConst(unsigned(10)) + self.d2 = AnyConst(unsigned( 1)) + + @ValueCastable.lowermethod + def as_value(self): + return Cat(self.d2, self.xo, self.d0, self.d1, self.rt, self.po) + + class Instruction_X_cmp(ValueCastable): po = None bf = None @@ -214,3 +266,59 @@ class Instruction_XFX_spr(ValueCastable): @ValueCastable.lowermethod def as_value(self): return Cat(self._0, self.xo, self.spr, self._gpr, self.po) + + +class Instruction_XO(ValueCastable): + po = None + rt = None + ra = None + rb = None + oe = None + xo = None + rc = None + + def __init_subclass__(cls, *, po, xo, oe=None, rc=None): + cls.po = Const(po, unsigned(6)) + cls.xo = Const(xo, unsigned(9)) + if oe is not None: + cls.oe = Const(oe, unsigned(1)) + if rc is not None: + cls.rc = Const(rc, unsigned(1)) + + def __init__(self): + self.rt = AnyConst(unsigned(5)) + self.ra = AnyConst(unsigned(5)) + self.rb = AnyConst(unsigned(5)) + if self.oe is None: + self.oe = AnyConst(unsigned(1)) + if self.rc is None: + self.rc = AnyConst(unsigned(1)) + + @ValueCastable.lowermethod + def as_value(self): + return Cat(self.rc, self.xo, self.oe, self.rb, self.ra, self.rt, self.po) + + +class Instruction_Z23_add(ValueCastable): + po = None + rt = None + ra = None + rb = None + cy = None + xo = None + _0 = None + + def __init_subclass__(cls, *, po, xo, cy): + cls.po = Const(po, unsigned(6)) + cls.cy = Const(cy, unsigned(2)) + cls.xo = Const(xo, unsigned(8)) + + def __init__(self): + self.rt = AnyConst(unsigned(5)) + self.ra = AnyConst(unsigned(5)) + self.rb = AnyConst(unsigned(5)) + self._0 = AnyConst(unsigned(1)) + + @ValueCastable.lowermethod + def as_value(self): + return Cat(self._0, self.xo, self.cy, self.rb, self.ra, self.rt, self.po) diff --git a/power_fv/checks/insn/_insn.py b/power_fv/checks/insn/_insn.py index d95b68f..26b8bce 100644 --- a/power_fv/checks/insn/_insn.py +++ b/power_fv/checks/insn/_insn.py @@ -32,6 +32,60 @@ class CRORC (_fmt.Instruction_XL_crl, po=19, xo=417): pass class MCRF (_fmt.Instruction_XL_crf, po=19, xo=0): pass +# Add / Subtract from + +class ADDI (_fmt.Instruction_D_add, po=14): pass +class ADDIS (_fmt.Instruction_D_add, po=15): pass +class ADDPCIS (_fmt.Instruction_DX, po=19, xo= 2): pass +class ADD (_fmt.Instruction_XO, po=31, xo=266, oe=0, rc=0): pass +class ADD_ (_fmt.Instruction_XO, po=31, xo=266, oe=0, rc=1): pass +class ADDO (_fmt.Instruction_XO, po=31, xo=266, oe=1, rc=0): pass +class ADDO_ (_fmt.Instruction_XO, po=31, xo=266, oe=1, rc=1): pass +class ADDIC (_fmt.Instruction_D_add, po=12): pass +class ADDIC_ (_fmt.Instruction_D_add, po=13): pass +class SUBF (_fmt.Instruction_XO, po=31, xo= 40, oe=0, rc=0): pass +class SUBF_ (_fmt.Instruction_XO, po=31, xo= 40, oe=0, rc=1): pass +class SUBFO (_fmt.Instruction_XO, po=31, xo= 40, oe=1, rc=0): pass +class SUBFO_ (_fmt.Instruction_XO, po=31, xo= 40, oe=1, rc=1): pass +class SUBFIC (_fmt.Instruction_D_add, po= 8): pass +class ADDC (_fmt.Instruction_XO, po=31, xo= 10, oe=0, rc=0): pass +class ADDC_ (_fmt.Instruction_XO, po=31, xo= 10, oe=0, rc=1): pass +class ADDCO (_fmt.Instruction_XO, po=31, xo= 10, oe=1, rc=0): pass +class ADDCO_ (_fmt.Instruction_XO, po=31, xo= 10, oe=1, rc=1): pass +class ADDE (_fmt.Instruction_XO, po=31, xo=138, oe=0, rc=0): pass +class ADDE_ (_fmt.Instruction_XO, po=31, xo=138, oe=0, rc=1): pass +class ADDEO (_fmt.Instruction_XO, po=31, xo=138, oe=1, rc=0): pass +class ADDEO_ (_fmt.Instruction_XO, po=31, xo=138, oe=1, rc=1): pass +class SUBFC (_fmt.Instruction_XO, po=31, xo= 8, oe=0, rc=0): pass +class SUBFC_ (_fmt.Instruction_XO, po=31, xo= 8, oe=0, rc=1): pass +class SUBFCO (_fmt.Instruction_XO, po=31, xo= 8, oe=1, rc=0): pass +class SUBFCO_ (_fmt.Instruction_XO, po=31, xo= 8, oe=1, rc=1): pass +class SUBFE (_fmt.Instruction_XO, po=31, xo=136, oe=0, rc=0): pass +class SUBFE_ (_fmt.Instruction_XO, po=31, xo=136, oe=0, rc=1): pass +class SUBFEO (_fmt.Instruction_XO, po=31, xo=136, oe=1, rc=0): pass +class SUBFEO_ (_fmt.Instruction_XO, po=31, xo=136, oe=1, rc=1): pass +class ADDME (_fmt.Instruction_XO, po=31, xo=234, oe=0, rc=0): pass +class ADDME_ (_fmt.Instruction_XO, po=31, xo=234, oe=0, rc=1): pass +class ADDMEO (_fmt.Instruction_XO, po=31, xo=234, oe=1, rc=0): pass +class ADDMEO_ (_fmt.Instruction_XO, po=31, xo=234, oe=1, rc=1): pass +class ADDZE (_fmt.Instruction_XO, po=31, xo=202, oe=0, rc=0): pass +class ADDZE_ (_fmt.Instruction_XO, po=31, xo=202, oe=0, rc=1): pass +class ADDZEO (_fmt.Instruction_XO, po=31, xo=202, oe=1, rc=0): pass +class ADDZEO_ (_fmt.Instruction_XO, po=31, xo=202, oe=1, rc=1): pass +class SUBFME (_fmt.Instruction_XO, po=31, xo=232, oe=0, rc=0): pass +class SUBFME_ (_fmt.Instruction_XO, po=31, xo=232, oe=0, rc=1): pass +class SUBFMEO (_fmt.Instruction_XO, po=31, xo=232, oe=1, rc=0): pass +class SUBFMEO_ (_fmt.Instruction_XO, po=31, xo=232, oe=1, rc=1): pass +class SUBFZE (_fmt.Instruction_XO, po=31, xo=200, oe=0, rc=0): pass +class SUBFZE_ (_fmt.Instruction_XO, po=31, xo=200, oe=0, rc=1): pass +class SUBFZEO (_fmt.Instruction_XO, po=31, xo=200, oe=1, rc=0): pass +class SUBFZEO_ (_fmt.Instruction_XO, po=31, xo=200, oe=1, rc=1): pass +class ADDEX (_fmt.Instruction_Z23_add, po=31, xo=170, cy=0): pass +class NEG (_fmt.Instruction_XO, po=31, xo=104, oe=0, rc=0): pass +class NEG_ (_fmt.Instruction_XO, po=31, xo=104, oe=0, rc=1): pass +class NEGO (_fmt.Instruction_XO, po=31, xo=104, oe=1, rc=0): pass +class NEGO_ (_fmt.Instruction_XO, po=31, xo=104, oe=1, rc=1): pass + # Compare class CMPI (_fmt.Instruction_D_cmp, po=11): pass diff --git a/power_fv/checks/insn/all.py b/power_fv/checks/insn/all.py index 7154cba..f9273bc 100644 --- a/power_fv/checks/insn/all.py +++ b/power_fv/checks/insn/all.py @@ -1,6 +1,7 @@ from . import _insn from ._branch import BranchCheck from ._cr import CRCheck +from ._addsub import AddSubtractCheck from ._compare import CompareCheck from ._spr import SPRMoveCheck @@ -37,6 +38,60 @@ class CRORC (CRCheck, name="insn_crorc", insn_cls=_insn.CRORC ): pass class MCRF (CRCheck, name="insn_mcrf", insn_cls=_insn.MCRF ): pass +# Add / Subtract from + +class ADDI (AddSubtractCheck, name="insn_addi", insn_cls=_insn.ADDI ): pass +class ADDIS (AddSubtractCheck, name="insn_addis", insn_cls=_insn.ADDIS ): pass +class ADDPCIS (AddSubtractCheck, name="insn_addpcis", insn_cls=_insn.ADDPCIS ): pass +class ADD (AddSubtractCheck, name="insn_add", insn_cls=_insn.ADD ): pass +class ADD_ (AddSubtractCheck, name="insn_add.", insn_cls=_insn.ADD_ ): pass +class ADDO (AddSubtractCheck, name="insn_addo", insn_cls=_insn.ADDO ): pass +class ADDO_ (AddSubtractCheck, name="insn_addo.", insn_cls=_insn.ADDO_ ): pass +class ADDIC (AddSubtractCheck, name="insn_addic", insn_cls=_insn.ADDIC ): pass +class ADDIC_ (AddSubtractCheck, name="insn_addic.", insn_cls=_insn.ADDIC_ ): pass +class SUBF (AddSubtractCheck, name="insn_subf", insn_cls=_insn.SUBF ): pass +class SUBF_ (AddSubtractCheck, name="insn_subf.", insn_cls=_insn.SUBF_ ): pass +class SUBFO (AddSubtractCheck, name="insn_subfo", insn_cls=_insn.SUBFO ): pass +class SUBFO_ (AddSubtractCheck, name="insn_subfo.", insn_cls=_insn.SUBFO_ ): pass +class SUBFIC (AddSubtractCheck, name="insn_subfic", insn_cls=_insn.SUBFIC ): pass +class ADDC (AddSubtractCheck, name="insn_addc", insn_cls=_insn.ADDC ): pass +class ADDC_ (AddSubtractCheck, name="insn_addc.", insn_cls=_insn.ADDC_ ): pass +class ADDCO (AddSubtractCheck, name="insn_addco", insn_cls=_insn.ADDCO ): pass +class ADDCO_ (AddSubtractCheck, name="insn_addco.", insn_cls=_insn.ADDCO_ ): pass +class ADDE (AddSubtractCheck, name="insn_adde", insn_cls=_insn.ADDE ): pass +class ADDE_ (AddSubtractCheck, name="insn_adde.", insn_cls=_insn.ADDE_ ): pass +class ADDEO (AddSubtractCheck, name="insn_addeo", insn_cls=_insn.ADDEO ): pass +class ADDEO_ (AddSubtractCheck, name="insn_addeo.", insn_cls=_insn.ADDEO_ ): pass +class SUBFC (AddSubtractCheck, name="insn_subfc", insn_cls=_insn.SUBFC ): pass +class SUBFC_ (AddSubtractCheck, name="insn_subfc.", insn_cls=_insn.SUBFC_ ): pass +class SUBFCO (AddSubtractCheck, name="insn_subfco", insn_cls=_insn.SUBFCO ): pass +class SUBFCO_ (AddSubtractCheck, name="insn_subfco.", insn_cls=_insn.SUBFCO_ ): pass +class SUBFE (AddSubtractCheck, name="insn_subfe", insn_cls=_insn.SUBFE ): pass +class SUBFE_ (AddSubtractCheck, name="insn_subfe.", insn_cls=_insn.SUBFE_ ): pass +class SUBFEO (AddSubtractCheck, name="insn_subfeo", insn_cls=_insn.SUBFEO ): pass +class SUBFEO_ (AddSubtractCheck, name="insn_subfeo.", insn_cls=_insn.SUBFEO_ ): pass +class ADDME (AddSubtractCheck, name="insn_addme", insn_cls=_insn.ADDME ): pass +class ADDME_ (AddSubtractCheck, name="insn_addme.", insn_cls=_insn.ADDME_ ): pass +class ADDMEO (AddSubtractCheck, name="insn_addmeo", insn_cls=_insn.ADDMEO ): pass +class ADDMEO_ (AddSubtractCheck, name="insn_addmeo.", insn_cls=_insn.ADDMEO_ ): pass +class ADDZE (AddSubtractCheck, name="insn_addze", insn_cls=_insn.ADDZE ): pass +class ADDZE_ (AddSubtractCheck, name="insn_addze.", insn_cls=_insn.ADDZE_ ): pass +class ADDZEO (AddSubtractCheck, name="insn_addzeo", insn_cls=_insn.ADDZEO ): pass +class ADDZEO_ (AddSubtractCheck, name="insn_addzeo.", insn_cls=_insn.ADDZEO_ ): pass +class SUBFME (AddSubtractCheck, name="insn_subfme", insn_cls=_insn.SUBFME ): pass +class SUBFME_ (AddSubtractCheck, name="insn_subfme.", insn_cls=_insn.SUBFME_ ): pass +class SUBFMEO (AddSubtractCheck, name="insn_subfmeo", insn_cls=_insn.SUBFMEO ): pass +class SUBFMEO_ (AddSubtractCheck, name="insn_subfmeo.", insn_cls=_insn.SUBFMEO_): pass +class SUBFZE (AddSubtractCheck, name="insn_subfze", insn_cls=_insn.SUBFZE ): pass +class SUBFZE_ (AddSubtractCheck, name="insn_subfze.", insn_cls=_insn.SUBFZE_ ): pass +class SUBFZEO (AddSubtractCheck, name="insn_subfzeo", insn_cls=_insn.SUBFZEO ): pass +class SUBFZEO_ (AddSubtractCheck, name="insn_subfzeo.", insn_cls=_insn.SUBFZEO_): pass +class ADDEX (AddSubtractCheck, name="insn_addex", insn_cls=_insn.ADDEX ): pass +class NEG (AddSubtractCheck, name="insn_neg", insn_cls=_insn.NEG ): pass +class NEG_ (AddSubtractCheck, name="insn_neg.", insn_cls=_insn.NEG_ ): pass +class NEGO (AddSubtractCheck, name="insn_nego", insn_cls=_insn.NEGO ): pass +class NEGO_ (AddSubtractCheck, name="insn_nego.", insn_cls=_insn.NEGO_ ): pass + # Compare class CMPI (CompareCheck, name="insn_cmpi", insn_cls=_insn.CMPI ): pass