From ed2122d9406822b08098da4dcfae1bcb629768e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Wed, 11 May 2022 00:13:33 +0200 Subject: [PATCH] cores/microwatt: add support for SPRCheck. --- cores/microwatt/_wrapper.py | 20 ++++++++++++++ cores/microwatt/microwatt_top.vhdl | 42 +++++++++++++++++++++++++++++- cores/microwatt/run.py | 4 ++- 3 files changed, 64 insertions(+), 2 deletions(-) diff --git a/cores/microwatt/_wrapper.py b/cores/microwatt/_wrapper.py index 1cf8253..32098e5 100644 --- a/cores/microwatt/_wrapper.py +++ b/cores/microwatt/_wrapper.py @@ -160,6 +160,26 @@ class MicrowattWrapper(Elaboratable): ("o", "pfv_cr7_r_data", self.pfv.cr7.r_data), ("o", "pfv_cr7_w_stb", self.pfv.cr7.w_stb), ("o", "pfv_cr7_w_data", self.pfv.cr7.w_data), + + ("o", "pfv_lr_r_stb", self.pfv.lr.r_stb), + ("o", "pfv_lr_r_data", self.pfv.lr.r_data), + ("o", "pfv_lr_w_stb", self.pfv.lr.w_stb), + ("o", "pfv_lr_w_data", self.pfv.lr.w_data), + + ("o", "pfv_ctr_r_stb", self.pfv.ctr.r_stb), + ("o", "pfv_ctr_r_data", self.pfv.ctr.r_data), + ("o", "pfv_ctr_w_stb", self.pfv.ctr.w_stb), + ("o", "pfv_ctr_w_data", self.pfv.ctr.w_data), + + ("o", "pfv_xer_r_stb", self.pfv.xer.r_stb), + ("o", "pfv_xer_r_data", self.pfv.xer.r_data), + ("o", "pfv_xer_w_stb", self.pfv.xer.w_stb), + ("o", "pfv_xer_w_data", self.pfv.xer.w_data), + + ("o", "pfv_tar_r_stb", self.pfv.tar.r_stb), + ("o", "pfv_tar_r_data", self.pfv.tar.r_data), + ("o", "pfv_tar_w_stb", self.pfv.tar.w_stb), + ("o", "pfv_tar_w_data", self.pfv.tar.w_data), ) with m.If(Initial()): diff --git a/cores/microwatt/microwatt_top.vhdl b/cores/microwatt/microwatt_top.vhdl index 81181d8..db9b9a7 100644 --- a/cores/microwatt/microwatt_top.vhdl +++ b/cores/microwatt/microwatt_top.vhdl @@ -90,7 +90,27 @@ entity toplevel is pfv_cr7_r_stb : out std_ulogic; pfv_cr7_r_data : out std_ulogic_vector(3 downto 0); pfv_cr7_w_stb : out std_ulogic; - pfv_cr7_w_data : out std_ulogic_vector(3 downto 0) + pfv_cr7_w_data : out std_ulogic_vector(3 downto 0); + + pfv_lr_r_stb : out std_ulogic; + pfv_lr_r_data : out std_ulogic_vector(63 downto 0); + pfv_lr_w_stb : out std_ulogic; + pfv_lr_w_data : out std_ulogic_vector(63 downto 0); + + pfv_ctr_r_stb : out std_ulogic; + pfv_ctr_r_data : out std_ulogic_vector(63 downto 0); + pfv_ctr_w_stb : out std_ulogic; + pfv_ctr_w_data : out std_ulogic_vector(63 downto 0); + + pfv_xer_r_stb : out std_ulogic; + pfv_xer_r_data : out std_ulogic_vector(63 downto 0); + pfv_xer_w_stb : out std_ulogic; + pfv_xer_w_data : out std_ulogic_vector(63 downto 0); + + pfv_tar_r_stb : out std_ulogic; + pfv_tar_r_data : out std_ulogic_vector(63 downto 0); + pfv_tar_w_stb : out std_ulogic; + pfv_tar_w_data : out std_ulogic_vector(63 downto 0) ); end entity toplevel; @@ -192,4 +212,24 @@ begin pfv_cr7_w_stb <= pfv.cr(7).w_stb; pfv_cr7_w_data <= pfv.cr(7).w_data; + pfv_lr_r_stb <= pfv.lr.r_stb; + pfv_lr_r_data <= pfv.lr.r_data; + pfv_lr_w_stb <= pfv.lr.w_stb; + pfv_lr_w_data <= pfv.lr.w_data; + + pfv_ctr_r_stb <= pfv.ctr.r_stb; + pfv_ctr_r_data <= pfv.ctr.r_data; + pfv_ctr_w_stb <= pfv.ctr.w_stb; + pfv_ctr_w_data <= pfv.ctr.w_data; + + pfv_xer_r_stb <= pfv.xer.r_stb; + pfv_xer_r_data <= pfv.xer.r_data; + pfv_xer_w_stb <= pfv.xer.w_stb; + pfv_xer_w_data <= pfv.xer.w_data; + + pfv_tar_r_stb <= pfv.tar.r_stb; + pfv_tar_r_data <= pfv.tar.r_data; + pfv_tar_w_stb <= pfv.tar.w_stb; + pfv_tar_w_data <= pfv.tar.w_data; + end architecture behave; diff --git a/cores/microwatt/run.py b/cores/microwatt/run.py index 24858b4..9383b8c 100644 --- a/cores/microwatt/run.py +++ b/cores/microwatt/run.py @@ -14,7 +14,7 @@ from _wrapper import MicrowattWrapper if __name__ == "__main__": parser = argparse.ArgumentParser() - parser.add_argument("check", help="check", type=str, choices=("unique", "ia_fwd", "gpr", "cr")) + parser.add_argument("check", help="check", type=str, choices=("unique", "ia_fwd", "gpr", "cr", "spr")) parser.add_argument("--mode", help="mode", type=str, choices=("cover", "bmc"), default="bmc") parser.add_argument("--pre", help="pre-condition step, in clock cycles (default: 15)", type=int, default=15) parser.add_argument("--post", help="post-condition step, in clock cycles (default: 15)", type=int, default=15) @@ -30,6 +30,8 @@ if __name__ == "__main__": check = GPRCheck() if args.check == "cr": check = CRCheck() + if args.check == "spr": + check = SPRCheck() if args.mode == "bmc" else SPRCover() cpu = MicrowattWrapper() testbench = Testbench(check, cpu, t_pre=args.pre, t_post=args.post)