From e30ea40a8bb44cb29c4834878af07bc455f39e71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Fri, 4 Nov 2022 11:14:03 +0100 Subject: [PATCH] check.insn: ignore upper SPR 32-bits when pfv.gpr_width=32. --- power_fv/check/insn/__init__.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/power_fv/check/insn/__init__.py b/power_fv/check/insn/__init__.py index f8500fc..909cd6d 100644 --- a/power_fv/check/insn/__init__.py +++ b/power_fv/check/insn/__init__.py @@ -215,8 +215,9 @@ class _MemPortTest(Elaboratable): class _SysRegTest(Elaboratable): def __init__(self, check, *, reg): - self._dut = getattr(check.dut .pfv, reg) - self._spec = getattr(check.spec.pfv, reg) + self._dut = getattr(check.dut .pfv, reg) + self._spec = getattr(check.spec.pfv, reg) + self._width = check.dut.pfv.gpr_width self.valid = Record([ ("read" , [("r_mask", 1)]), @@ -238,6 +239,7 @@ class _SysRegTest(Elaboratable): ]) def contains(a, mask, b=None): + mask &= 2**self._width - 1 if b is None: b = mask return a & mask == b & mask