From c743c932e7643df4ddbf9026d19c39fb30bb69d5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= <jf@jfng.fr>
Date: Sat, 6 Aug 2022 06:07:04 +0200
Subject: [PATCH] compare: fix incorrect CR bit order.

The regression was introduced by b3255def.
---
 power_fv/insn/spec/compare.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/power_fv/insn/spec/compare.py b/power_fv/insn/spec/compare.py
index afc0b21..f9caaf2 100644
--- a/power_fv/insn/spec/compare.py
+++ b/power_fv/insn/spec/compare.py
@@ -26,10 +26,10 @@ class CompareSpec(InsnSpec, Elaboratable):
         src_a  = Signal(64)
         src_b  = Signal(64)
         result = Record([
-            ("lt",  1),
-            ("gt",  1),
-            ("eq_", 1),
             ("so",  1),
+            ("eq_", 1),
+            ("gt",  1),
+            ("lt",  1),
         ])
 
         # Operand A : (RA) or EXTS((RA)(32:63)) or EXTZ((RA)(32:63)) or EXTZ((RA)(56:63))