From a9a17377b706ab66f02d55b2c281805cf99f82db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Sat, 6 Aug 2022 06:03:41 +0200 Subject: [PATCH] intr: use 0 for IR/DR bits, until LPCR is supported. --- power_fv/intr.py | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/power_fv/intr.py b/power_fv/intr.py index d7b912d..ae5b1c2 100644 --- a/power_fv/intr.py +++ b/power_fv/intr.py @@ -53,8 +53,11 @@ class Interrupt: return stmts -# TODO: Support MSR.{IR,DR,HV,S,LE} bits, which depend on context (e.g. LPCR) - -INTR_ALIGNMENT = Interrupt(0x600, ir=None, dr=None, ee=0, ri=0, me=None, hv=None, s=None) -INTR_PROGRAM = Interrupt(0x700, ir=None, dr=None, ee=0, ri=0, me=None, hv=None, s=None) -INTR_SYSTEM_CALL = Interrupt(0xC00, ir=None, dr=None, ee=0, ri=0, me=None, hv=None, s=None) +# TODO: +# - Support MSR.{IR,DR,HV,S,LE} bits, which depend on context (e.g. LPCR) +# - Support LPCR.{AIL,HAIL} fields. For now, assume AIL=0 and HAIL=0 +# (i.e. interrupts always set IR/DR to 0). + +INTR_ALIGNMENT = Interrupt(0x600, ir=0, dr=0, ee=0, ri=0, me=None, hv=None, s=None) +INTR_PROGRAM = Interrupt(0x700, ir=0, dr=0, ee=0, ri=0, me=None, hv=None, s=None) +INTR_SYSTEM_CALL = Interrupt(0xC00, ir=0, dr=0, ee=0, ri=0, me=None, hv=None, s=None)