From 2e29794b7d7641eb7045ad2386e69f37a013419b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Mon, 25 Jul 2022 14:59:04 +0200 Subject: [PATCH] check.insn: use DUT parameters to configure the spec pfv.Interface. --- cores/microwatt/microwatt/core.py | 2 +- power_fv/check/insn/__init__.py | 2 +- power_fv/insn/spec/__init__.py | 16 +++++----------- power_fv/insn/spec/addsub.py | 4 ---- power_fv/insn/spec/bcd.py | 4 ---- power_fv/insn/spec/branch.py | 4 ---- power_fv/insn/spec/byterev.py | 4 ---- power_fv/insn/spec/compare.py | 4 ---- power_fv/insn/spec/cr.py | 4 ---- power_fv/insn/spec/loadstore.py | 11 +++-------- power_fv/insn/spec/logical.py | 4 ---- power_fv/insn/spec/msr.py | 4 ---- power_fv/insn/spec/rotate.py | 4 ---- power_fv/insn/spec/spr.py | 4 ---- power_fv/insn/spec/syscall.py | 4 ---- power_fv/insn/spec/trap.py | 4 ---- power_fv/pfv.py | 4 +++- 17 files changed, 13 insertions(+), 70 deletions(-) diff --git a/cores/microwatt/microwatt/core.py b/cores/microwatt/microwatt/core.py index afd5d70..f268b86 100644 --- a/cores/microwatt/microwatt/core.py +++ b/cores/microwatt/microwatt/core.py @@ -134,7 +134,7 @@ class MicrowattWrapper(Elaboratable): """) def __init__(self, **kwargs): - self.pfv = pfv.Interface() + self.pfv = pfv.Interface(mem_aligned=False) self.wb_insn = wishbone.Interface(addr_width=29, data_width=64, granularity=8, features=("stall",)) self.wb_data = wishbone.Interface(addr_width=29, data_width=64, granularity=8, diff --git a/power_fv/check/insn/__init__.py b/power_fv/check/insn/__init__.py index 2eec96f..320bedc 100644 --- a/power_fv/check/insn/__init__.py +++ b/power_fv/check/insn/__init__.py @@ -28,7 +28,7 @@ class InsnCheck(PowerFVCheck, metaclass=InsnCheckMeta): def __init__(self, *, depth, skip, core, **kwargs): super().__init__(depth=depth, skip=skip, core=core, **kwargs) self.insn = self.insn_cls() - self.spec = self.spec_cls(self.insn) + self.spec = self.spec_cls(self.insn, mem_aligned=self.dut.pfv.mem_aligned) def testbench(self): return InsnTestbench(self) diff --git a/power_fv/insn/spec/__init__.py b/power_fv/insn/spec/__init__.py index 6152000..c4dfb09 100644 --- a/power_fv/insn/spec/__init__.py +++ b/power_fv/insn/spec/__init__.py @@ -1,5 +1,6 @@ from abc import ABCMeta, abstractmethod +from power_fv import pfv from power_fv.insn import WordInsn @@ -7,20 +8,13 @@ __all__ = ["InsnSpec"] class InsnSpec(metaclass=ABCMeta): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - - @property - def insn(self): - return self._insn - - @insn.setter - def insn(self, insn): + def __init__(self, insn, **kwargs): if not isinstance(insn, WordInsn): raise TypeError("Instruction must be an instance of WordInsn, not {!r}" .format(insn)) - self._insn = insn + + self.insn = insn + self.pfv = pfv.Interface(**kwargs) @abstractmethod def elaborate(self, platform): diff --git a/power_fv/insn/spec/addsub.py b/power_fv/insn/spec/addsub.py index 6764736..4b0a675 100644 --- a/power_fv/insn/spec/addsub.py +++ b/power_fv/insn/spec/addsub.py @@ -11,10 +11,6 @@ __all__ = ["AddSubSpec"] class AddSubSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/bcd.py b/power_fv/insn/spec/bcd.py index 3b261ca..88b1b61 100644 --- a/power_fv/insn/spec/bcd.py +++ b/power_fv/insn/spec/bcd.py @@ -11,10 +11,6 @@ __all__ = ["BCDAssistSpec"] class BCDAssistSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/branch.py b/power_fv/insn/spec/branch.py index ea68e50..aa631d4 100644 --- a/power_fv/insn/spec/branch.py +++ b/power_fv/insn/spec/branch.py @@ -11,10 +11,6 @@ __all__ = ["BranchSpec"] class BranchSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/byterev.py b/power_fv/insn/spec/byterev.py index ee1170b..a084660 100644 --- a/power_fv/insn/spec/byterev.py +++ b/power_fv/insn/spec/byterev.py @@ -11,10 +11,6 @@ __all__ = ["ByteReverseSpec"] class ByteReverseSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/compare.py b/power_fv/insn/spec/compare.py index ace3778..29d6d6e 100644 --- a/power_fv/insn/spec/compare.py +++ b/power_fv/insn/spec/compare.py @@ -11,10 +11,6 @@ __all__ = ["CompareSpec"] class CompareSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/cr.py b/power_fv/insn/spec/cr.py index 738a1df..ff14ddb 100644 --- a/power_fv/insn/spec/cr.py +++ b/power_fv/insn/spec/cr.py @@ -14,10 +14,6 @@ __all__ = ["CRLogicalSpec", "CRMoveSpec"] class CRLogicalSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/loadstore.py b/power_fv/insn/spec/loadstore.py index 54e9d90..b7247df 100644 --- a/power_fv/insn/spec/loadstore.py +++ b/power_fv/insn/spec/loadstore.py @@ -12,11 +12,6 @@ __all__ = ["LoadStoreSpec"] class LoadStoreSpec(InsnSpec, Elaboratable): - def __init__(self, insn, *, dword_aligned=False): - self.pfv = pfv.Interface() - self.insn = insn - self.dword_aligned = dword_aligned - def elaborate(self, platform): m = Module() @@ -79,8 +74,8 @@ class LoadStoreSpec(InsnSpec, Elaboratable): m.d.comb += ea.eq(iea(ea_base + ea_offset, self.pfv.msr.r_data.sf)) - # If `dword_aligned` is set, `pfv.mem.addr` points to the dword containing EA. - # If `dword_aligned` is unset, `pfv.mem.addr` is equal to EA. + # If `pfv.mem_aligned` is set, `pfv.mem.addr` points to the dword containing EA. + # If `pfv.mem_aligned` is unset, `pfv.mem.addr` is equal to EA. byte_offset = Signal(3) half_offset = Signal(2) @@ -88,7 +83,7 @@ class LoadStoreSpec(InsnSpec, Elaboratable): m.d.comb += self.pfv.mem.addr[3:].eq(ea[3:]) - if self.dword_aligned: + if self.pfv.mem_aligned: m.d.comb += [ self.pfv.mem.addr[:3].eq(0), byte_offset.eq(ea[:3]), diff --git a/power_fv/insn/spec/logical.py b/power_fv/insn/spec/logical.py index 0eccdf3..4dc4d21 100644 --- a/power_fv/insn/spec/logical.py +++ b/power_fv/insn/spec/logical.py @@ -28,10 +28,6 @@ class _CountTrailingZeros(Elaboratable): class LogicalSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/msr.py b/power_fv/insn/spec/msr.py index 5427ed8..6491a4b 100644 --- a/power_fv/insn/spec/msr.py +++ b/power_fv/insn/spec/msr.py @@ -12,10 +12,6 @@ __all__ = ["MSRMoveSpec"] class MSRMoveSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/rotate.py b/power_fv/insn/spec/rotate.py index 5d7fbe8..cd529a4 100644 --- a/power_fv/insn/spec/rotate.py +++ b/power_fv/insn/spec/rotate.py @@ -11,10 +11,6 @@ __all__ = ["RotateShiftSpec"] class RotateShiftSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/spr.py b/power_fv/insn/spec/spr.py index a7e962d..edb9887 100644 --- a/power_fv/insn/spec/spr.py +++ b/power_fv/insn/spec/spr.py @@ -12,10 +12,6 @@ __all__ = ["SPRMoveSpec"] class SPRMoveSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/syscall.py b/power_fv/insn/spec/syscall.py index ec20f73..9614362 100644 --- a/power_fv/insn/spec/syscall.py +++ b/power_fv/insn/spec/syscall.py @@ -11,10 +11,6 @@ __all__ = ["SystemCallSpec"] class SystemCallSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/insn/spec/trap.py b/power_fv/insn/spec/trap.py index b243d4d..1b1e21c 100644 --- a/power_fv/insn/spec/trap.py +++ b/power_fv/insn/spec/trap.py @@ -11,10 +11,6 @@ __all__ = ["TrapSpec"] class TrapSpec(InsnSpec, Elaboratable): - def __init__(self, insn): - self.pfv = pfv.Interface() - self.insn = insn - def elaborate(self, platform): m = Module() diff --git a/power_fv/pfv.py b/power_fv/pfv.py index 51dde7b..24cda85 100644 --- a/power_fv/pfv.py +++ b/power_fv/pfv.py @@ -51,7 +51,9 @@ class Interface(Record): Instruction strobe. Asserted when the processor retires an instruction. Other signals are only valid when ``stb`` is asserted. """ - def __init__(self, *, name=None, src_loc_at=0): + def __init__(self, *, mem_aligned=False, name=None, src_loc_at=0): + self.mem_aligned = bool(mem_aligned) + layout = [ ("stb" , unsigned( 1)), ("insn" , unsigned(64)),