Add checks for Rotate/Shift instructions.
parent
aeed09092c
commit
23dcd80a9e
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from power_fv.insn import const
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from power_fv.insn.spec.rotate import RotateShiftSpec
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from power_fv.check.insn import InsnCheck
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__all__ = [
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"RLWINM", "RLWINM_", "RLWNM", "RLWNM_", "RLWIMI", "RLWIMI_",
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"SLW" , "SLW_" ,
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"SRW" , "SRW_" , "SRAWI", "SRAWI_", "SRAW" , "SRAW_" ,
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]
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class RLWINM (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.RLWINM ): pass
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class RLWINM_(InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.RLWINM_): pass
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class RLWNM (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.RLWNM ): pass
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class RLWNM_ (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.RLWNM_ ): pass
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class RLWIMI (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.RLWIMI ): pass
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class RLWIMI_(InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.RLWIMI_): pass
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class SLW (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SLW ): pass
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class SLW_ (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SLW_ ): pass
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class SRW (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SRW ): pass
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class SRW_ (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SRW_ ): pass
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class SRAWI (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SRAWI ): pass
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class SRAWI_ (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SRAWI_ ): pass
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class SRAW (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SRAW ): pass
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class SRAW_ (InsnCheck, spec_cls=RotateShiftSpec, insn_cls=const.SRAW_ ): pass
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@ -0,0 +1,156 @@
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from amaranth import *
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from power_fv import pfv
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from power_fv.insn.const import *
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from . import InsnSpec
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from .utils import iea
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__all__ = ["RotateShiftSpec"]
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class RotateShiftSpec(InsnSpec, Elaboratable):
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def __init__(self, insn):
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self.pfv = pfv.Interface()
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self.insn = insn
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def elaborate(self, platform):
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m = Module()
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m.d.comb += [
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self.pfv.stb .eq(1),
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self.pfv.insn.eq(Cat(Const(0, 32), self.insn.as_value())),
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self.pfv.intr.eq(0),
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self.pfv.nia .eq(iea(self.pfv.cia + 4, self.pfv.msr.r_data.sf)),
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self.pfv.msr.r_mask.sf.eq(1),
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]
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src = Signal(unsigned(64))
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shamt = Signal(unsigned( 6))
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rotl = Signal(unsigned(64))
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mask = Signal(unsigned(64))
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result = Signal(unsigned(64))
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# Source operand : (RS)(32:63)||(RS)(32:63)
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m.d.comb += [
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self.pfv.rs.index.eq(self.insn.RS),
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self.pfv.rs.r_stb.eq(1),
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src.eq(self.pfv.rs.r_data),
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]
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# Shift amount : SH or (RB)(59:63)
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if isinstance(self.insn, (RLWINM, RLWINM_, RLWIMI, RLWIMI_, SRAWI, SRAWI_)):
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m.d.comb += shamt.eq(self.insn.SH)
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elif isinstance(self.insn, (RLWNM, RLWNM_, SLW, SLW_, SRW, SRW_, SRAW, SRAW_)):
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m.d.comb += [
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self.pfv.rb.index.eq(self.insn.RB),
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self.pfv.rb.r_stb.eq(1),
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shamt.eq(self.pfv.rb.r_data[:6]),
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]
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else:
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assert False
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# Mask
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def _mask(mstart, mstop):
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mask = ((1 << 64-mstart) - 1) & ~((1 << 63-mstop ) - 1)
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mask_inv = ~((1 << 63-mstop ) - 1) | ((1 << 64-mstart) - 1)
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return Mux(mstart <= mstop, mask, mask_inv)
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if isinstance(self.insn, (RLWINM, RLWINM_, RLWNM, RLWNM_, RLWIMI, RLWIMI_)):
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m.d.comb += mask.eq(_mask(self.insn.MB+32, self.insn.ME+32))
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elif isinstance(self.insn, (SLW, SLW_)):
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m.d.comb += mask.eq(Mux(shamt[5], 0, _mask(32, 63-shamt)))
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elif isinstance(self.insn, (SRW, SRW_, SRAW, SRAW_)):
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m.d.comb += mask.eq(Mux(shamt[5], 0, _mask(shamt+32, 63)))
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elif isinstance(self.insn, (SRAWI, SRAWI_)):
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m.d.comb += mask.eq(_mask(shamt+32, 63))
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else:
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assert False
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# Rotation
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def _rotl32(src, n):
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v = Repl(src[:32], 2)
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return ((v << n) | (v >> 64-n)) & Repl(1, 64)
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if isinstance(self.insn, (
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RLWINM, RLWINM_, RLWNM, RLWNM_, RLWIMI, RLWIMI_,
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SLW, SLW_,
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)):
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m.d.comb += rotl.eq(_rotl32(src, shamt))
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elif isinstance(self.insn, (SRW, SRW_, SRAWI, SRAWI_, SRAW, SRAW_)):
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m.d.comb += rotl.eq(_rotl32(src, 64-shamt))
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else:
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assert False
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# Write result to RA
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m.d.comb += [
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self.pfv.ra.index .eq(self.insn.RA),
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self.pfv.ra.w_stb .eq(1),
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self.pfv.ra.w_data.eq(result),
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]
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if isinstance(self.insn, (RLWINM, RLWINM_, RLWNM, RLWNM_, SLW, SLW_, SRW, SRW_)):
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m.d.comb += result.eq(rotl & mask)
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elif isinstance(self.insn, (RLWIMI, RLWIMI_)):
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m.d.comb += self.pfv.ra.r_stb.eq(1)
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m.d.comb += result.eq(rotl & mask | self.pfv.ra.r_data & ~mask)
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elif isinstance(self.insn, (SRAWI, SRAWI_, SRAW, SRAW_)):
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m.d.comb += result.eq(rotl & mask | Repl(src[31], 64) & ~mask)
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else:
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assert False
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# Write CR0
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if isinstance(self.insn, (
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RLWINM_, RLWNM_, RLWIMI_, SLW_, SRW_, SRAWI_, SRAW_,
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)):
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cr0_w_mask = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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cr0_w_data = Record([("so", 1), ("eq_", 1), ("gt", 1), ("lt", 1)])
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m.d.comb += [
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self.pfv.xer.r_mask.so.eq(1),
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cr0_w_mask .eq(0b1111),
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cr0_w_data.so .eq(self.pfv.xer.r_data.so),
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cr0_w_data.eq_.eq(~Mux(self.pfv.msr.r_data.sf, result[:64].any(), result[:32].any())),
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cr0_w_data.gt .eq(~(cr0_w_data.lt | cr0_w_data.eq_)),
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cr0_w_data.lt .eq(Mux(self.pfv.msr.r_data.sf, result[63], result[31])),
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self.pfv.cr.w_mask.cr0.eq(cr0_w_mask),
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self.pfv.cr.w_data.cr0.eq(cr0_w_data),
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]
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# Write XER
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if isinstance(self.insn, (SRAWI, SRAWI_, SRAW, SRAW_)):
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carry = Signal()
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m.d.comb += [
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carry.eq(src[31] & (rotl & ~mask)[:32].any()),
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self.pfv.xer.w_mask.ca .eq(1),
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self.pfv.xer.w_data.ca .eq(carry),
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self.pfv.xer.w_mask.ca32.eq(1),
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self.pfv.xer.w_data.ca32.eq(carry),
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]
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# Interrupt causes
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intr = Record([
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("rotl32_mask", 1),
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])
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if isinstance(self.insn, (RLWINM, RLWINM_, RLWNM, RLWNM_, RLWIMI, RLWIMI_)):
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m.d.comb += intr.rotl32_mask.eq((self.insn.MB >= 32) | (self.insn.ME >= 32))
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else:
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m.d.comb += intr.rotl32_mask.eq(0)
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m.d.comb += self.pfv.intr.eq(intr.any())
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return m
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