From 1d8916f2dfee83b8cf28ab2020b5447f9c27b5c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Fri, 28 Oct 2022 17:09:50 +0200 Subject: [PATCH] insn.spec.compare: ignore upper 32-bits when pfv.gpr_width=32. --- power_fv/insn/spec/compare.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/power_fv/insn/spec/compare.py b/power_fv/insn/spec/compare.py index 286370a..31712a2 100644 --- a/power_fv/insn/spec/compare.py +++ b/power_fv/insn/spec/compare.py @@ -23,8 +23,8 @@ class CompareSpec(InsnSpec, Elaboratable): self.pfv.xer.r_mask.so.eq(1), ] - src_a = Signal(64) - src_b = Signal(64) + src_a = Signal(self.pfv.gpr_width) + src_b = Signal(self.pfv.gpr_width) result = Record([ ("so", 1), ("eq_", 1), @@ -120,7 +120,7 @@ class CompareSpec(InsnSpec, Elaboratable): elif isinstance(self.insn, CMPEQB): _match = 0 - for i in range(64//8): + for i in range(self.pfv.gpr_width//8): _match |= (src_a == src_b.word_select(i, width=8)) m.d.comb += result.eq(Cat(Const(0, 2), _match, Const(0, 1)))